opcodes/ChangeLog

   1 2017-11-07  Alan Modra  <amodra@gmail.com>
   2
   3         * opintl.h: Formatting, comment fixes.
   4         (gettext, ngettext): Redefine when ENABLE_NLS.
   5         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
   6         (_): Define using gettext.
   7         (textdomain, bindtextdomain): Use safer "do nothing".
   8
   9 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
  10
  11         * arc-dis.c (print_hex): New variable.
  12         (parse_option): Check for hex option.
  13         (print_insn_arc): Use hexadecimal representation for short
  14         immediate values when requested.
  15         (print_arc_disassembler_options): Add hex option to the list.
  16
  17 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
  18
  19         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
  20         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
  21         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
  22         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
  23         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
  24         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
  25         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
  26         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
  27         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
  28         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
  29         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
  30         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
  31         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
  32         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
  33         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
  34         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
  35         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
  36         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
  37         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
  38         Changed opcodes.
  39         (prealloc, prefetch*): Place them before ld instruction.
  40         * arc-opc.c (skip_this_opcode): Add ARITH class.
  41
  42 2017-10-25  Alan Modra  <amodra@gmail.com>
  43
  44         PR 22348
  45         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
  46         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
  47         (imm4flag, size_changed): Likewise.
  48         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
  49         (words, allWords, processing_argument_number): Likewise.
  50         (cst4flag, size_changed): Likewise.
  51         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
  52         (crx_cst4_maps): Rename from cst4_maps.
  53         (crx_no_op_insn): Rename from no_op_insn.
  54
  55 2017-10-24  Andrew Waterman  <andrew@sifive.com>
  56
  57         * riscv-opc.c (match_c_addi16sp) : New function.
  58         (match_c_addi4spn): New function.
  59         (match_c_lui): Don't allow 0-immediate encodings.
  60         (riscv_opcodes) <addi>: Use the above functions.
  61         <add>: Likewise.
  62         <c.addi4spn>: Likewise.
  63         <c.addi16sp>: Likewise.
  64
  65 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  66
  67         * i386-init.h: Regenerate
  68         * i386-tbl.h: Likewise
  69
  70 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  71
  72         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
  73         (enum): Add EVEX_W_0F3854_P_2.
  74         * i386-dis-evex.h (evex_table): Updated.
  75         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
  76         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  77         (cpu_flags): Add CpuAVX512_BITALG.
  78         * i386-opc.h (enum): Add CpuAVX512_BITALG.
  79         (i386_cpu_flags): Add cpuavx512_bitalg..
  80         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
  81         * i386-init.h: Regenerate.
  82         * i386-tbl.h: Likewise.
  83
  84 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  85
  86         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
  87         * i386-dis-evex.h (evex_table): Updated.
  88         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
  89         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  90         (cpu_flags): Add CpuAVX512_VNNI.
  91         * i386-opc.h (enum): Add CpuAVX512_VNNI.
  92         (i386_cpu_flags): Add cpuavx512_vnni.
  93         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
  94         * i386-init.h: Regenerate.
  95         * i386-tbl.h: Likewise.
  96
  97 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  98
  99         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 100         (enum): Remove VEX_LEN_0F3A44_P_2.
 101         (vex_len_table): Ditto.
 102         (enum): Remove VEX_W_0F3A44_P_2.
 103         (vew_w_table): Ditto.
 104         (prefix_table): Adjust instructions (see prefixes above).
 105         * i386-dis-evex.h (evex_table):
 106         Add new instructions (see prefixes above).
 107         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 108         (bitfield_cpu_flags): Ditto.
 109         * i386-opc.h (enum): Ditto.
 110         (i386_cpu_flags): Ditto.
 111         (CpuUnused): Comment out to avoid zero-width field problem.
 112         * i386-opc.tbl (vpclmulqdq): New instruction.
 113         * i386-init.h: Regenerate.
 114         * i386-tbl.h: Ditto.
 115
 116 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 117
 118         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 119         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 120         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 121         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 122         (vex_len_table): Ditto.
 123         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 124         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 125         (vew_w_table): Ditto.
 126         (prefix_table): Adjust instructions (see prefixes above).
 127         * i386-dis-evex.h (evex_table):
 128         Add new instructions (see prefixes above).
 129         * i386-gen.c (cpu_flag_init): Add VAES.
 130         (bitfield_cpu_flags): Ditto.
 131         * i386-opc.h (enum): Ditto.
 132         (i386_cpu_flags): Ditto.
 133         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 134         * i386-init.h: Regenerate.
 135         * i386-tbl.h: Ditto.
 136
 137 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 138
 139         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 140         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 141         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 142         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 143         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 144         (prefix_table): Updated (see prefixes above).
 145         (three_byte_table): Likewise.
 146         (vex_w_table): Likewise.
 147         * i386-dis-evex.h: Likewise.
 148         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 149         (cpu_flags): Add CpuGFNI.
 150         * i386-opc.h (enum): Add CpuGFNI.
 151         (i386_cpu_flags): Add cpugfni.
 152         * i386-opc.tbl: Add Intel GFNI instructions.
 153         * i386-init.h: Regenerate.
 154         * i386-tbl.h: Likewise.
 155
 156 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 157
 158         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 159         Define EXbScalar and EXwScalar for OP_EX.
 160         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 161         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 162         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 163         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 164         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 165         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 166         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 167         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 168         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 169         (OP_E_memory): Likewise.
 170         * i386-dis-evex.h: Updated.
 171         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 172         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 173         (cpu_flags): Add CpuAVX512_VBMI2.
 174         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 175         (i386_cpu_flags): Add cpuavx512_vbmi2.
 176         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 177         * i386-init.h: Regenerate.
 178         * i386-tbl.h: Likewise.
 179
 180 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 181
 182         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 183
 184 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 185
 186         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 187         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 188         K15. Add jmpix pattern.
 189
 190 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 191
 192         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 193
 194 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 195
 196         * s390-opc.c (INSTR_SI_RD): New macro.
 197         (INSTR_S_RD): Adjust example instruction.
 198         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 199         SI_RD.
 200
 201 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 202
 203         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 204         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 205         VLE multimple load/store instructions. Old e_ldm* variants are
 206         kept as aliases.
 207         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 208
 209 2017-09-27  Nick Clifton  <nickc@redhat.com>
 210
 211         PR 22179
 212         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 213         names for the fmv.x.s and fmv.s.x instructions respectively.
 214
 215 2017-09-26  do  <do@nerilex.org>
 216
 217         PR 22123
 218         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 219         be used on CPUs that have emacs support.
 220
 221 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 222
 223         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 224
 225 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 226
 227         * nds32-asm.c: Rename __BIT() to N32_BIT().
 228         * nds32-asm.h: Likewise.
 229         * nds32-dis.c: Likewise.
 230
 231 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         * i386-dis.c (last_active_prefix): Removed.
 234         (ckprefix): Don't set last_active_prefix.
 235         (NOTRACK_Fixup): Don't check last_active_prefix.
 236
 237 2017-08-31  Nick Clifton  <nickc@redhat.com>
 238
 239         * po/fr.po: Updated French translation.
 240
 241 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 242
 243         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 244         fields.
 245
 246 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 247             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 248
 249         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 250         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 251         New entries efs2 and spe2.
 252         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 253         (SPE2_OPCD_SEGS): New macro.
 254         (spe2_opcd_indices): New.
 255         (disassemble_init_powerpc): Handle SPE2 opcodes.
 256         (lookup_spe2): New function.
 257         (print_insn_powerpc): call lookup_spe2.
 258         * ppc-opc.c (insert_evuimm1_ex0): New function.
 259         (extract_evuimm1_ex0): Likewise.
 260         (insert_evuimm_lt8): Likewise.
 261         (extract_evuimm_lt8): Likewise.
 262         (insert_off_spe2): Likewise.
 263         (extract_off_spe2): Likewise.
 264         (insert_Ddd): Likewise.
 265         (extract_Ddd): Likewise.
 266         (DD): New operand.
 267         (EVUIMM_LT8): Likewise.
 268         (EVUIMM_LT16): Adjust.
 269         (MMMM): New operand.
 270         (EVUIMM_1): Likewise.
 271         (EVUIMM_1_EX0): Likewise.
 272         (EVUIMM_2): Adjust.
 273         (NNN): New operand.
 274         (VX_OFF_SPE2): Likewise.
 275         (BBB): Likewise.
 276         (DDD): Likewise.
 277         (VX_MASK_DDD): New mask.
 278         (HH): New operand.
 279         (VX_RA_CONST): New macro.
 280         (VX_RA_CONST_MASK): Likewise.
 281         (VX_RB_CONST): Likewise.
 282         (VX_RB_CONST_MASK): Likewise.
 283         (VX_OFF_SPE2_MASK): Likewise.
 284         (VX_SPE_CRFD): Likewise.
 285         (VX_SPE_CRFD_MASK VX): Likewise.
 286         (VX_SPE2_CLR): Likewise.
 287         (VX_SPE2_CLR_MASK): Likewise.
 288         (VX_SPE2_SPLATB): Likewise.
 289         (VX_SPE2_SPLATB_MASK): Likewise.
 290         (VX_SPE2_OCTET): Likewise.
 291         (VX_SPE2_OCTET_MASK): Likewise.
 292         (VX_SPE2_DDHH): Likewise.
 293         (VX_SPE2_DDHH_MASK): Likewise.
 294         (VX_SPE2_HH): Likewise.
 295         (VX_SPE2_HH_MASK): Likewise.
 296         (VX_SPE2_EVMAR): Likewise.
 297         (VX_SPE2_EVMAR_MASK): Likewise.
 298         (PPCSPE2): Likewise.
 299         (PPCEFS2): Likewise.
 300         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 301         (powerpc_macros): Map old SPE instructions have new names
 302         with the same opcodes. Add SPE2 instructions which just are
 303         mapped to SPE2.
 304         (spe2_opcodes): Add SPE2 opcodes.
 305
 306 2017-08-23  Alan Modra  <amodra@gmail.com>
 307
 308         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 309         extract functions earlier, deleting forward declarations.
 310         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 311         RA_MASK.
 312
 313 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 314
 315         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 316
 317 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 318             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 319
 320         * ppc-opc.c (insert_evuimm2_ex0): New function.
 321         (extract_evuimm2_ex0): Likewise.
 322         (insert_evuimm4_ex0): Likewise.
 323         (extract_evuimm4_ex0): Likewise.
 324         (insert_evuimm8_ex0): Likewise.
 325         (extract_evuimm8_ex0): Likewise.
 326         (insert_evuimm_lt16): Likewise.
 327         (extract_evuimm_lt16): Likewise.
 328         (insert_rD_rS_even): Likewise.
 329         (extract_rD_rS_even): Likewise.
 330         (insert_off_lsp): Likewise.
 331         (extract_off_lsp): Likewise.
 332         (RD_EVEN): New operand.
 333         (RS_EVEN): Likewise.
 334         (RSQ): Adjust.
 335         (EVUIMM_LT16): New operand.
 336         (HTM_SI): Adjust.
 337         (EVUIMM_2_EX0): New operand.
 338         (EVUIMM_4): Adjust.
 339         (EVUIMM_4_EX0): New operand.
 340         (EVUIMM_8): Adjust.
 341         (EVUIMM_8_EX0): New operand.
 342         (WS): Adjust.
 343         (VX_OFF): New operand.
 344         (VX_LSP): New macro.
 345         (VX_LSP_MASK): Likewise.
 346         (VX_LSP_OFF_MASK): Likewise.
 347         (PPC_OPCODE_LSP): Likewise.
 348         (vle_opcodes): Add LSP opcodes.
 349         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 350
 351 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 352
 353         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 354         register operands in CRC instructions.
 355         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 356         comments.
 357
 358 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 359
 360         * disassemble.c (disassembler): Mark big and mach with
 361         ATTRIBUTE_UNUSED.
 362
 363 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 364
 365         * disassemble.c (disassembler): Remove arch/mach/endian
 366         assertions.
 367
 368 2017-07-25  Nick Clifton  <nickc@redhat.com>
 369
 370         PR 21739
 371         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 372         message.
 373         (insert_r0): Likewise.
 374         (insert_r1): Likewise.
 375         (insert_r2): Likewise.
 376         (insert_r3): Likewise.
 377         (insert_sp): Likewise.
 378         (insert_gp): Likewise.
 379         (insert_pcl): Likewise.
 380         (insert_blink): Likewise.
 381         (insert_ilink1): Likewise.
 382         (insert_ilink2): Likewise.
 383         (insert_ras): Likewise.
 384         (insert_rbs): Likewise.
 385         (insert_rcs): Likewise.
 386         (insert_simm3s): Likewise.
 387         (insert_rrange): Likewise.
 388         (insert_r13el): Likewise.
 389         (insert_fpel): Likewise.
 390         (insert_blinkel): Likewise.
 391         (insert_pclel): Likewise.
 392         (insert_nps_bitop_size_2b): Likewise.
 393         (insert_nps_imm_offset): Likewise.
 394         (insert_nps_imm_entry): Likewise.
 395         (insert_nps_size_16bit): Likewise.
 396         (insert_nps_##NAME##_pos): Likewise.
 397         (insert_nps_##NAME): Likewise.
 398         (insert_nps_bitop_ins_ext): Likewise.
 399         (insert_nps_##NAME): Likewise.
 400         (insert_nps_min_hofs): Likewise.
 401         (insert_nps_##NAME): Likewise.
 402         (insert_nps_rbdouble_64): Likewise.
 403         (insert_nps_misc_imm_offset): Likewise.
 404         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 405         option description.
 406
 407 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 408             Jiong Wang  <jiong.wang@arm.com>
 409
 410         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 411         correct the print.
 412         * aarch64-dis-2.c: Regenerated.
 413
 414 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 415
 416         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 417         table.
 418
 419 2017-07-20  Nick Clifton  <nickc@redhat.com>
 420
 421         * po/de.po: Updated German translation.
 422
 423 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 424
 425         * arc-regs.h (sec_stat): New aux register.
 426         (aux_kernel_sp): Likewise.
 427         (aux_sec_u_sp): Likewise.
 428         (aux_sec_k_sp): Likewise.
 429         (sec_vecbase_build): Likewise.
 430         (nsc_table_top): Likewise.
 431         (nsc_table_base): Likewise.
 432         (ersec_stat): Likewise.
 433         (aux_sec_except): Likewise.
 434
 435 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 436
 437         * arc-opc.c (extract_uimm12_20): New function.
 438         (UIMM12_20): New operand.
 439         (SIMM3_5_S): Adjust.
 440         * arc-tbl.h (sjli): Add new instruction.
 441
 442 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 443             John Eric Martin  <John.Martin@emmicro-us.com>
 444
 445         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 446         (UIMM3_23): Adjust accordingly.
 447         * arc-regs.h: Add/correct jli_base register.
 448         * arc-tbl.h (jli_s): Likewise.
 449
 450 2017-07-18  Nick Clifton  <nickc@redhat.com>
 451
 452         PR 21775
 453         * aarch64-opc.c: Fix spelling typos.
 454         * i386-dis.c: Likewise.
 455
 456 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 457
 458         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 459         max_addr_offset and octets variables to size_t.
 460
 461 2017-07-12  Alan Modra  <amodra@gmail.com>
 462
 463         * po/da.po: Update from translationproject.org/latest/opcodes/.
 464         * po/de.po: Likewise.
 465         * po/es.po: Likewise.
 466         * po/fi.po: Likewise.
 467         * po/fr.po: Likewise.
 468         * po/id.po: Likewise.
 469         * po/it.po: Likewise.
 470         * po/nl.po: Likewise.
 471         * po/pt_BR.po: Likewise.
 472         * po/ro.po: Likewise.
 473         * po/sv.po: Likewise.
 474         * po/tr.po: Likewise.
 475         * po/uk.po: Likewise.
 476         * po/vi.po: Likewise.
 477         * po/zh_CN.po: Likewise.
 478
 479 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 480             Alan Modra  <amodra@gmail.com>
 481
 482         * cgen.sh: Mark generated files read-only.
 483         * epiphany-asm.c: Regenerate.
 484         * epiphany-desc.c: Regenerate.
 485         * epiphany-desc.h: Regenerate.
 486         * epiphany-dis.c: Regenerate.
 487         * epiphany-ibld.c: Regenerate.
 488         * epiphany-opc.c: Regenerate.
 489         * epiphany-opc.h: Regenerate.
 490         * fr30-asm.c: Regenerate.
 491         * fr30-desc.c: Regenerate.
 492         * fr30-desc.h: Regenerate.
 493         * fr30-dis.c: Regenerate.
 494         * fr30-ibld.c: Regenerate.
 495         * fr30-opc.c: Regenerate.
 496         * fr30-opc.h: Regenerate.
 497         * frv-asm.c: Regenerate.
 498         * frv-desc.c: Regenerate.
 499         * frv-desc.h: Regenerate.
 500         * frv-dis.c: Regenerate.
 501         * frv-ibld.c: Regenerate.
 502         * frv-opc.c: Regenerate.
 503         * frv-opc.h: Regenerate.
 504         * ip2k-asm.c: Regenerate.
 505         * ip2k-desc.c: Regenerate.
 506         * ip2k-desc.h: Regenerate.
 507         * ip2k-dis.c: Regenerate.
 508         * ip2k-ibld.c: Regenerate.
 509         * ip2k-opc.c: Regenerate.
 510         * ip2k-opc.h: Regenerate.
 511         * iq2000-asm.c: Regenerate.
 512         * iq2000-desc.c: Regenerate.
 513         * iq2000-desc.h: Regenerate.
 514         * iq2000-dis.c: Regenerate.
 515         * iq2000-ibld.c: Regenerate.
 516         * iq2000-opc.c: Regenerate.
 517         * iq2000-opc.h: Regenerate.
 518         * lm32-asm.c: Regenerate.
 519         * lm32-desc.c: Regenerate.
 520         * lm32-desc.h: Regenerate.
 521         * lm32-dis.c: Regenerate.
 522         * lm32-ibld.c: Regenerate.
 523         * lm32-opc.c: Regenerate.
 524         * lm32-opc.h: Regenerate.
 525         * lm32-opinst.c: Regenerate.
 526         * m32c-asm.c: Regenerate.
 527         * m32c-desc.c: Regenerate.
 528         * m32c-desc.h: Regenerate.
 529         * m32c-dis.c: Regenerate.
 530         * m32c-ibld.c: Regenerate.
 531         * m32c-opc.c: Regenerate.
 532         * m32c-opc.h: Regenerate.
 533         * m32r-asm.c: Regenerate.
 534         * m32r-desc.c: Regenerate.
 535         * m32r-desc.h: Regenerate.
 536         * m32r-dis.c: Regenerate.
 537         * m32r-ibld.c: Regenerate.
 538         * m32r-opc.c: Regenerate.
 539         * m32r-opc.h: Regenerate.
 540         * m32r-opinst.c: Regenerate.
 541         * mep-asm.c: Regenerate.
 542         * mep-desc.c: Regenerate.
 543         * mep-desc.h: Regenerate.
 544         * mep-dis.c: Regenerate.
 545         * mep-ibld.c: Regenerate.
 546         * mep-opc.c: Regenerate.
 547         * mep-opc.h: Regenerate.
 548         * mt-asm.c: Regenerate.
 549         * mt-desc.c: Regenerate.
 550         * mt-desc.h: Regenerate.
 551         * mt-dis.c: Regenerate.
 552         * mt-ibld.c: Regenerate.
 553         * mt-opc.c: Regenerate.
 554         * mt-opc.h: Regenerate.
 555         * or1k-asm.c: Regenerate.
 556         * or1k-desc.c: Regenerate.
 557         * or1k-desc.h: Regenerate.
 558         * or1k-dis.c: Regenerate.
 559         * or1k-ibld.c: Regenerate.
 560         * or1k-opc.c: Regenerate.
 561         * or1k-opc.h: Regenerate.
 562         * or1k-opinst.c: Regenerate.
 563         * xc16x-asm.c: Regenerate.
 564         * xc16x-desc.c: Regenerate.
 565         * xc16x-desc.h: Regenerate.
 566         * xc16x-dis.c: Regenerate.
 567         * xc16x-ibld.c: Regenerate.
 568         * xc16x-opc.c: Regenerate.
 569         * xc16x-opc.h: Regenerate.
 570         * xstormy16-asm.c: Regenerate.
 571         * xstormy16-desc.c: Regenerate.
 572         * xstormy16-desc.h: Regenerate.
 573         * xstormy16-dis.c: Regenerate.
 574         * xstormy16-ibld.c: Regenerate.
 575         * xstormy16-opc.c: Regenerate.
 576         * xstormy16-opc.h: Regenerate.
 577
 578 2017-07-07  Alan Modra  <amodra@gmail.com>
 579
 580         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 581         * m32c-dis.c: Regenerate.
 582         * mep-dis.c: Regenerate.
 583
 584 2017-07-05  Borislav Petkov  <bp@suse.de>
 585
 586         * i386-dis.c: Enable ModRM.reg /6 aliases.
 587
 588 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 589
 590         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 591         with vmrs and vmsr.
 592
 593 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 594
 595         * configure: Regenerate.
 596
 597 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 598
 599         * po/opcodes.pot: Regenerate.
 600
 601 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 602
 603         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 604         entries to the MSA ASE instruction block.
 605
 606 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 607             Maciej W. Rozycki  <macro@imgtec.com>
 608
 609         * micromips-opc.c (XPA, XPAVZ): New macros.
 610         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 611         "mthgc0".
 612
 613 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 614             Maciej W. Rozycki  <macro@imgtec.com>
 615
 616         * micromips-opc.c (I36): New macro.
 617         (micromips_opcodes): Add "eretnc".
 618
 619 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 620             Andrew Bennett  <andrew.bennett@imgtec.com>
 621
 622         * mips-dis.c (mips_calculate_combination_ases): Handle the
 623         ASE_XPA_VIRT flag.
 624         (parse_mips_ase_option): New function.
 625         (parse_mips_dis_option): Factor out ASE option handling to the
 626         new function.  Call `mips_calculate_combination_ases'.
 627         * mips-opc.c (XPAVZ): New macro.
 628         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 629         "mfhgc0", "mthc0" and "mthgc0".
 630
 631 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 632
 633         * mips-dis.c (mips_calculate_combination_ases): New function.
 634         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 635         calculation to the new function.
 636         (set_default_mips_dis_options): Call the new function.
 637
 638 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 639
 640         * arc-dis.c (parse_disassembler_options): Use
 641         FOR_EACH_DISASSEMBLER_OPTION.
 642
 643 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 644
 645         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 646         disassembler option strings.
 647         (parse_cpu_option): Likewise.
 648
 649 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 650
 651         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 652         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 653         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 654         (aarch64_feature_dotprod, DOT_INSN): New.
 655         (udot, sdot): New.
 656         * aarch64-dis-2.c: Regenerated.
 657
 658 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 659
 660         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 661
 662 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 663             Matthew Fortune  <matthew.fortune@imgtec.com>
 664             Andrew Bennett  <andrew.bennett@imgtec.com>
 665
 666         * mips-formats.h (INT_BIAS): New macro.
 667         (INT_ADJ): Redefine in INT_BIAS terms.
 668         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 669         (mips_print_save_restore): New function.
 670         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 671         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 672         call.
 673         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 674         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 675         OP_SAVE_RESTORE_LIST handling, factored out from here.
 676         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 677         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 678         (mips_builtin_opcodes): Add "restore" and "save" entries.
 679         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 680         (IAMR2): New macro.
 681         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 682
 683 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 684
 685         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 686         alias; do not mark SLTI instruction as an alias.
 687
 688 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 689
 690         * i386-dis.c (RM_0FAE_REG_5): Removed.
 691         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 692         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 693         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 694         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 695         PREFIX_MOD_3_0F01_REG_5_RM_0.
 696         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 697         PREFIX_MOD_3_0FAE_REG_5.
 698         (mod_table): Update MOD_0FAE_REG_5.
 699         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 700         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 701         * i386-tbl.h: Regenerated.
 702
 703 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 704
 705         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 706         * i386-opc.tbl: Likewise.
 707         * i386-tbl.h: Regenerated.
 708
 709 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 710
 711         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 712         and "jmp{&|}".
 713         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 714         prefix.
 715
 716 2017-06-19  Nick Clifton  <nickc@redhat.com>
 717
 718         PR binutils/21614
 719         * score-dis.c (score_opcodes): Add sentinel.
 720
 721 2017-06-16  Alan Modra  <amodra@gmail.com>
 722
 723         * rx-decode.c: Regenerate.
 724
 725 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 726
 727         PR binutils/21594
 728         * i386-dis.c (OP_E_register): Check valid bnd register.
 729         (OP_G): Likewise.
 730
 731 2017-06-15  Nick Clifton  <nickc@redhat.com>
 732
 733         PR binutils/21595
 734         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 735         range value.
 736
 737 2017-06-15  Nick Clifton  <nickc@redhat.com>
 738
 739         PR binutils/21588
 740         * rl78-decode.opc (OP_BUF_LEN): Define.
 741         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 742         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 743         array.
 744         * rl78-decode.c: Regenerate.
 745
 746 2017-06-15  Nick Clifton  <nickc@redhat.com>
 747
 748         PR binutils/21586
 749         * bfin-dis.c (gregs): Clip index to prevent overflow.
 750         (regs): Likewise.
 751         (regs_lo): Likewise.
 752         (regs_hi): Likewise.
 753
 754 2017-06-14  Nick Clifton  <nickc@redhat.com>
 755
 756         PR binutils/21576
 757         * score7-dis.c (score_opcodes): Add sentinel.
 758
 759 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 760
 761         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 762         * arm-dis.c: Likewise.
 763         * ia64-dis.c: Likewise.
 764         * mips-dis.c: Likewise.
 765         * spu-dis.c: Likewise.
 766         * disassemble.h (print_insn_aarch64): New declaration, moved from
 767         include/dis-asm.h.
 768         (print_insn_big_arm, print_insn_big_mips): Likewise.
 769         (print_insn_i386, print_insn_ia64): Likewise.
 770         (print_insn_little_arm, print_insn_little_mips): Likewise.
 771
 772 2017-06-14  Nick Clifton  <nickc@redhat.com>
 773
 774         PR binutils/21587
 775         * rx-decode.opc: Include libiberty.h
 776         (GET_SCALE): New macro - validates access to SCALE array.
 777         (GET_PSCALE): New macro - validates access to PSCALE array.
 778         (DIs, SIs, S2Is, rx_disp): Use new macros.
 779         * rx-decode.c: Regenerate.
 780
 781 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 782
 783         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 784
 785 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 786
 787         * arc-dis.c (enforced_isa_mask): Declare.
 788         (cpu_types): Likewise.
 789         (parse_cpu_option): New function.
 790         (parse_disassembler_options): Use it.
 791         (print_insn_arc): Use enforced_isa_mask.
 792         (print_arc_disassembler_options): Document new options.
 793
 794 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 795
 796         * alpha-dis.c: Include disassemble.h, don't include
 797         dis-asm.h.
 798         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 799         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 800         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 801         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 802         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 803         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 804         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 805         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 806         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 807         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 808         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 809         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 810         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 811         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 812         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 813         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 814         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 815         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 816         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 817         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 818         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 819         * z80-dis.c, z8k-dis.c: Likewise.
 820         * disassemble.h: New file.
 821
 822 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 823
 824         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 825         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 826
 827 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 828
 829         * disassemble.c (disassembler): Add arguments a, big and mach.
 830         Use them.
 831
 832 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 833
 834         * i386-dis.c (NOTRACK_Fixup): New.
 835         (NOTRACK): Likewise.
 836         (NOTRACK_PREFIX): Likewise.
 837         (last_active_prefix): Likewise.
 838         (reg_table): Use NOTRACK on indirect call and jmp.
 839         (ckprefix): Set last_active_prefix.
 840         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 841         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 842         * i386-opc.h (NoTrackPrefixOk): New.
 843         (i386_opcode_modifier): Add notrackprefixok.
 844         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 845         Add notrack.
 846         * i386-tbl.h: Regenerated.
 847
 848 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 849
 850         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 851         (X_IMM2): Define.
 852         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 853         bfd_mach_sparc_v9m8.
 854         (print_insn_sparc): Handle new operand types.
 855         * sparc-opc.c (MASK_M8): Define.
 856         (v6): Add MASK_M8.
 857         (v6notlet): Likewise.
 858         (v7): Likewise.
 859         (v8): Likewise.
 860         (v9): Likewise.
 861         (v9a): Likewise.
 862         (v9b): Likewise.
 863         (v9c): Likewise.
 864         (v9d): Likewise.
 865         (v9e): Likewise.
 866         (v9v): Likewise.
 867         (v9m): Likewise.
 868         (v9andleon): Likewise.
 869         (m8): Define.
 870         (HWS_VM8): Define.
 871         (HWS2_VM8): Likewise.
 872         (sparc_opcode_archs): Add entry for "m8".
 873         (sparc_opcodes): Add OSA2017 and M8 instructions
 874         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 875         fpx{ll,ra,rl}64x,
 876         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 877         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 878         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 879         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 880         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 881         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 882         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 883         ASI_CORE_SELECT_COMMIT_NHT.
 884
 885 2017-05-18  Alan Modra  <amodra@gmail.com>
 886
 887         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 888         * aarch64-dis.c: Likewise.
 889         * aarch64-gen.c: Likewise.
 890         * aarch64-opc.c: Likewise.
 891
 892 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 893             Matthew Fortune  <matthew.fortune@imgtec.com>
 894
 895         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 896         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 897         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 898         (print_insn_arg) <OP_REG28>: Add handler.
 899         (validate_insn_args) <OP_REG28>: Handle.
 900         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 901         32-bit encoding and 9-bit immediates.
 902         (print_insn_mips16): Handle MIPS16 instructions that require
 903         32-bit encoding and MFC0/MTC0 operand decoding.
 904         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 905         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 906         (RD_C0, WR_C0, E2, E2MT): New macros.
 907         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 908         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 909         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 910         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 911         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 912         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 913         instructions, "swl", "swr", "sync" and its "sync_acquire",
 914         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 915         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 916         regular/extended entries for original MIPS16 ISA revision
 917         instructions whose extended forms are subdecoded in the MIPS16e2
 918         ISA revision: "li", "sll" and "srl".
 919
 920 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 921
 922         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 923         reference in CP0 move operand decoding.
 924
 925 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 926
 927         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 928         type to hexadecimal.
 929         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 930
 931 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 932
 933         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 934         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 935         "sync_rmb" and "sync_wmb" as aliases.
 936         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 937         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 938
 939 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 940
 941         * arc-dis.c (parse_option): Update quarkse_em option..
 942         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 943         QUARKSE1.
 944         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 945
 946 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 947
 948         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 949
 950 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 951
 952         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 953         register.
 954
 955 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 956
 957         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 958         and branches and not synthetic data instructions.
 959
 960 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 961
 962         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 963
 964 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 965
 966         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 967         * arc-opc.c (insert_r13el): New function.
 968         (R13_EL): Define.
 969         * arc-tbl.h: Add new enter/leave variants.
 970
 971 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 972
 973         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 974
 975 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 976
 977         * mips-dis.c (print_mips_disassembler_options): Add
 978         `no-aliases'.
 979
 980 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 981
 982         * mips16-opc.c (AL): New macro.
 983         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 984         of "ld" and "lw" as aliases.
 985
 986 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 987
 988         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 989         arguments.
 990
 991 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 992             Alan Modra  <amodra@gmail.com>
 993
 994         * ppc-opc.c (ELEV): Define.
 995         (vle_opcodes): Add se_rfgi and e_sc.
 996         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 997         for E200Z4.
 998
 999 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1000
1001         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1002
1003 2017-04-21  Nick Clifton  <nickc@redhat.com>
1004
1005         PR binutils/21380
1006         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1007         LD3R and LD4R.
1008
1009 2017-04-13  Alan Modra  <amodra@gmail.com>
1010
1011         * epiphany-desc.c: Regenerate.
1012         * fr30-desc.c: Regenerate.
1013         * frv-desc.c: Regenerate.
1014         * ip2k-desc.c: Regenerate.
1015         * iq2000-desc.c: Regenerate.
1016         * lm32-desc.c: Regenerate.
1017         * m32c-desc.c: Regenerate.
1018         * m32r-desc.c: Regenerate.
1019         * mep-desc.c: Regenerate.
1020         * mt-desc.c: Regenerate.
1021         * or1k-desc.c: Regenerate.
1022         * xc16x-desc.c: Regenerate.
1023         * xstormy16-desc.c: Regenerate.
1024
1025 2017-04-11  Alan Modra  <amodra@gmail.com>
1026
1027         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1028         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1029         PPC_OPCODE_TMR for e6500.
1030         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1031         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1032         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1033         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1034         (PPCHTM): Define as PPC_OPCODE_POWER8.
1035         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1036
1037 2017-04-10  Alan Modra  <amodra@gmail.com>
1038
1039         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1040         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1041         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1042         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1043
1044 2017-04-09  Pip Cet  <pipcet@gmail.com>
1045
1046         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1047         appropriate floating-point precision directly.
1048
1049 2017-04-07  Alan Modra  <amodra@gmail.com>
1050
1051         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1052         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1053         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1054         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1055         vector instructions with E6500 not PPCVEC2.
1056
1057 2017-04-06  Pip Cet  <pipcet@gmail.com>
1058
1059         * Makefile.am: Add wasm32-dis.c.
1060         * configure.ac: Add wasm32-dis.c to wasm32 target.
1061         * disassemble.c: Add wasm32 disassembler code.
1062         * wasm32-dis.c: New file.
1063         * Makefile.in: Regenerate.
1064         * configure: Regenerate.
1065         * po/POTFILES.in: Regenerate.
1066         * po/opcodes.pot: Regenerate.
1067
1068 2017-04-05  Pedro Alves  <palves@redhat.com>
1069
1070         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1071         * arm-dis.c (parse_arm_disassembler_options): Constify.
1072         * ppc-dis.c (powerpc_init_dialect): Constify local.
1073         * vax-dis.c (parse_disassembler_options): Constify.
1074
1075 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1076
1077         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1078         RISCV_GP_SYMBOL.
1079
1080 2017-03-30  Pip Cet  <pipcet@gmail.com>
1081
1082         * configure.ac: Add (empty) bfd_wasm32_arch target.
1083         * configure: Regenerate
1084         * po/opcodes.pot: Regenerate.
1085
1086 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1087
1088         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1089         OSA2015.
1090         * opcodes/sparc-opc.c (asi_table): New ASIs.
1091
1092 2017-03-29  Alan Modra  <amodra@gmail.com>
1093
1094         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1095         "raw" option.
1096         (lookup_powerpc): Don't special case -1 dialect.  Handle
1097         PPC_OPCODE_RAW.
1098         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1099         lookup_powerpc call, pass it on second.
1100
1101 2017-03-27  Alan Modra  <amodra@gmail.com>
1102
1103         PR 21303
1104         * ppc-dis.c (struct ppc_mopt): Comment.
1105         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1106
1107 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1108
1109         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1110         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1111         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1112         (insert_nps_misc_imm_offset): New function.
1113         (extract_nps_misc imm_offset): New function.
1114         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1115         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1116
1117 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1118
1119         * s390-mkopc.c (main): Remove vx2 check.
1120         * s390-opc.txt: Remove vx2 instruction flags.
1121
1122 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1123
1124         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1125         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1126         (insert_nps_imm_offset): New function.
1127         (extract_nps_imm_offset): New function.
1128         (insert_nps_imm_entry): New function.
1129         (extract_nps_imm_entry): New function.
1130
1131 2017-03-17  Alan Modra  <amodra@gmail.com>
1132
1133         PR 21248
1134         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1135         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1136         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1137
1138 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1139
1140         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1141         <c.andi>: Likewise.
1142         <c.addiw> Likewise.
1143
1144 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1145
1146         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1147
1148 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1149
1150         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1151         <srl> Likewise.
1152         <srai> Likewise.
1153         <sra> Likewise.
1154
1155 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1156
1157         * i386-gen.c (opcode_modifiers): Replace S with Load.
1158         * i386-opc.h (S): Removed.
1159         (Load): New.
1160         (i386_opcode_modifier): Replace s with load.
1161         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1162         and {evex}.  Replace S with Load.
1163         * i386-tbl.h: Regenerated.
1164
1165 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1166
1167         * i386-opc.tbl: Use CpuCET on rdsspq.
1168         * i386-tbl.h: Regenerated.
1169
1170 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1171
1172         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1173         <vsx>: Do not use PPC_OPCODE_VSX3;
1174
1175 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1176
1177         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1178
1179 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1180
1181         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1182         (MOD_0F1E_PREFIX_1): Likewise.
1183         (MOD_0F38F5_PREFIX_2): Likewise.
1184         (MOD_0F38F6_PREFIX_0): Likewise.
1185         (RM_0F1E_MOD_3_REG_7): Likewise.
1186         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1187         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1188         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1189         (PREFIX_0F1E): Likewise.
1190         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1191         (PREFIX_0F38F5): Likewise.
1192         (dis386_twobyte): Use PREFIX_0F1E.
1193         (reg_table): Add REG_0F1E_MOD_3.
1194         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1195         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1196         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1197         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1198         (three_byte_table): Use PREFIX_0F38F5.
1199         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1200         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1201         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1202         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1203         PREFIX_MOD_3_0F01_REG_5_RM_2.
1204         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1205         (cpu_flags): Add CpuCET.
1206         * i386-opc.h (CpuCET): New enum.
1207         (CpuUnused): Commented out.
1208         (i386_cpu_flags): Add cpucet.
1209         * i386-opc.tbl: Add Intel CET instructions.
1210         * i386-init.h: Regenerated.
1211         * i386-tbl.h: Likewise.
1212
1213 2017-03-06  Alan Modra  <amodra@gmail.com>
1214
1215         PR 21124
1216         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1217         (extract_raq, extract_ras, extract_rbx): New functions.
1218         (powerpc_operands): Use opposite corresponding insert function.
1219         (Q_MASK): Define.
1220         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1221         register restriction.
1222
1223 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1224
1225         * disassemble.c Include "safe-ctype.h".
1226         (disassemble_init_for_target): Handle s390 init.
1227         (remove_whitespace_and_extra_commas): New function.
1228         (disassembler_options_cmp): Likewise.
1229         * arm-dis.c: Include "libiberty.h".
1230         (NUM_ELEM): Delete.
1231         (regnames): Use long disassembler style names.
1232         Add force-thumb and no-force-thumb options.
1233         (NUM_ARM_REGNAMES): Rename from this...
1234         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1235         (get_arm_regname_num_options): Delete.
1236         (set_arm_regname_option): Likewise.
1237         (get_arm_regnames): Likewise.
1238         (parse_disassembler_options): Likewise.
1239         (parse_arm_disassembler_option): Rename from this...
1240         (parse_arm_disassembler_options): ...to this.  Make static.
1241         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1242         (print_insn): Use parse_arm_disassembler_options.
1243         (disassembler_options_arm): New function.
1244         (print_arm_disassembler_options): Handle updated regnames.
1245         * ppc-dis.c: Include "libiberty.h".
1246         (ppc_opts): Add "32" and "64" entries.
1247         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1248         (powerpc_init_dialect): Add break to switch statement.
1249         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1250         (disassembler_options_powerpc): New function.
1251         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1252         Remove printing of "32" and "64".
1253         * s390-dis.c: Include "libiberty.h".
1254         (init_flag): Remove unneeded variable.
1255         (struct s390_options_t): New structure type.
1256         (options): New structure.
1257         (init_disasm): Rename from this...
1258         (disassemble_init_s390): ...to this.  Add initializations for
1259         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1260         (print_insn_s390): Delete call to init_disasm.
1261         (disassembler_options_s390): New function.
1262         (print_s390_disassembler_options): Print using information from
1263         struct 'options'.
1264         * po/opcodes.pot: Regenerate.
1265
1266 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1267
1268         * i386-dis.c (PCMPESTR_Fixup): New.
1269         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1270         (prefix_table): Use PCMPESTR_Fixup.
1271         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1272         PCMPESTR_Fixup.
1273         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1274         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1275         Split 64-bit and non-64-bit variants.
1276         * opcodes/i386-tbl.h: Re-generate.
1277
1278 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1279
1280         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1281         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1282         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1283         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1284         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1285         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1286         (OP_SVE_V_HSD): New macros.
1287         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1288         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1289         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1290         (aarch64_opcode_table): Add new SVE instructions.
1291         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1292         for rotation operands.  Add new SVE operands.
1293         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1294         (ins_sve_quad_index): Likewise.
1295         (ins_imm_rotate): Split into...
1296         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1297         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1298         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1299         functions.
1300         (aarch64_ins_sve_addr_ri_s4): New function.
1301         (aarch64_ins_sve_quad_index): Likewise.
1302         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1303         * aarch64-asm-2.c: Regenerate.
1304         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1305         (ext_sve_quad_index): Likewise.
1306         (ext_imm_rotate): Split into...
1307         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1308         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1309         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1310         functions.
1311         (aarch64_ext_sve_addr_ri_s4): New function.
1312         (aarch64_ext_sve_quad_index): Likewise.
1313         (aarch64_ext_sve_index): Allow quad indices.
1314         (do_misc_decoding): Likewise.
1315         * aarch64-dis-2.c: Regenerate.
1316         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1317         aarch64_field_kinds.
1318         (OPD_F_OD_MASK): Widen by one bit.
1319         (OPD_F_NO_ZR): Bump accordingly.
1320         (get_operand_field_width): New function.
1321         * aarch64-opc.c (fields): Add new SVE fields.
1322         (operand_general_constraint_met_p): Handle new SVE operands.
1323         (aarch64_print_operand): Likewise.
1324         * aarch64-opc-2.c: Regenerate.
1325
1326 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1327
1328         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1329         (aarch64_feature_compnum): ...this.
1330         (SIMD_V8_3): Replace with...
1331         (COMPNUM): ...this.
1332         (CNUM_INSN): New macro.
1333         (aarch64_opcode_table): Use it for the complex number instructions.
1334
1335 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1336
1337         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1338
1339 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1340
1341         Add support for associating SPARC ASIs with an architecture level.
1342         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1343         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1344         decoding of SPARC ASIs.
1345
1346 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1347
1348         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1349         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1350
1351 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1352
1353         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1354         1 (instead of to itself). Correct typo.
1355
1356 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1357
1358         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1359         pseudoinstructions.
1360
1361 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1362
1363         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1364         (aarch64_sys_reg_supported_p): Handle them.
1365
1366 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1367
1368         * arc-opc.c (UIMM6_20R): Define.
1369         (SIMM12_20): Use above.
1370         (SIMM12_20R): Define.
1371         (SIMM3_5_S): Use above.
1372         (UIMM7_A32_11R_S): Define.
1373         (UIMM7_9_S): Use above.
1374         (UIMM3_13R_S): Define.
1375         (SIMM11_A32_7_S): Use above.
1376         (SIMM9_8R): Define.
1377         (UIMM10_A32_8_S): Use above.
1378         (UIMM8_8R_S): Define.
1379         (W6): Use above.
1380         (arc_relax_opcodes): Use all above defines.
1381
1382 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1383
1384         * arc-regs.h: Distinguish some of the registers different on
1385         ARC700 and HS38 cpus.
1386
1387 2017-02-14  Alan Modra  <amodra@gmail.com>
1388
1389         PR 21118
1390         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1391         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1392
1393 2017-02-11  Stafford Horne  <shorne@gmail.com>
1394             Alan Modra  <amodra@gmail.com>
1395
1396         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1397         Use insn_bytes_value and insn_int_value directly instead.  Don't
1398         free allocated memory until function exit.
1399
1400 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1401
1402         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1403
1404 2017-02-03  Nick Clifton  <nickc@redhat.com>
1405
1406         PR 21096
1407         * aarch64-opc.c (print_register_list): Ensure that the register
1408         list index will fir into the tb buffer.
1409         (print_register_offset_address): Likewise.
1410         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1411
1412 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1413
1414         PR 21056
1415         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1416         instructions when the previous fetch packet ends with a 32-bit
1417         instruction.
1418
1419 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1420
1421         * pru-opc.c: Remove vague reference to a future GDB port.
1422
1423 2017-01-20  Nick Clifton  <nickc@redhat.com>
1424
1425         * po/ga.po: Updated Irish translation.
1426
1427 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1428
1429         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1430
1431 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1432
1433         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1434         if FETCH_DATA returns 0.
1435         (m68k_scan_mask): Likewise.
1436         (print_insn_m68k): Update code to handle -1 return value.
1437
1438 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1439
1440         * m68k-dis.c (enum print_insn_arg_error): New.
1441         (NEXTBYTE): Replace -3 with
1442         PRINT_INSN_ARG_MEMORY_ERROR.
1443         (NEXTULONG): Likewise.
1444         (NEXTSINGLE): Likewise.
1445         (NEXTDOUBLE): Likewise.
1446         (NEXTDOUBLE): Likewise.
1447         (NEXTPACKED): Likewise.
1448         (FETCH_ARG): Likewise.
1449         (FETCH_DATA): Update comments.
1450         (print_insn_arg): Update comments. Replace magic numbers with
1451         enum.
1452         (match_insn_m68k): Likewise.
1453
1454 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1455
1456         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1457         * i386-dis-evex.h (evex_table): Updated.
1458         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1459         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1460         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1461         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1462         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1463         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1464         * i386-init.h: Regenerate.
1465         * i386-tbl.h: Ditto.
1466
1467 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1468
1469         * msp430-dis.c (msp430_singleoperand): Return -1 if
1470         msp430dis_opcode_signed returns false.
1471         (msp430_doubleoperand): Likewise.
1472         (msp430_branchinstr): Return -1 if
1473         msp430dis_opcode_unsigned returns false.
1474         (msp430x_calla_instr): Likewise.
1475         (print_insn_msp430): Likewise.
1476
1477 2017-01-05  Nick Clifton  <nickc@redhat.com>
1478
1479         PR 20946
1480         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1481         could not be matched.
1482         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1483         NULL.
1484
1485 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1486
1487         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1488         (aarch64_opcode_table): Use RCPC_INSN.
1489
1490 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1491
1492         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1493         extension.
1494         * riscv-opcodes/all-opcodes: Likewise.
1495
1496 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1497
1498         * riscv-dis.c (print_insn_args): Add fall through comment.
1499
1500 2017-01-03  Nick Clifton  <nickc@redhat.com>
1501
1502         * po/sr.po: New Serbian translation.
1503         * configure.ac (ALL_LINGUAS): Add sr.
1504         * configure: Regenerate.
1505
1506 2017-01-02  Alan Modra  <amodra@gmail.com>
1507
1508         * epiphany-desc.h: Regenerate.
1509         * epiphany-opc.h: Regenerate.
1510         * fr30-desc.h: Regenerate.
1511         * fr30-opc.h: Regenerate.
1512         * frv-desc.h: Regenerate.
1513         * frv-opc.h: Regenerate.
1514         * ip2k-desc.h: Regenerate.
1515         * ip2k-opc.h: Regenerate.
1516         * iq2000-desc.h: Regenerate.
1517         * iq2000-opc.h: Regenerate.
1518         * lm32-desc.h: Regenerate.
1519         * lm32-opc.h: Regenerate.
1520         * m32c-desc.h: Regenerate.
1521         * m32c-opc.h: Regenerate.
1522         * m32r-desc.h: Regenerate.
1523         * m32r-opc.h: Regenerate.
1524         * mep-desc.h: Regenerate.
1525         * mep-opc.h: Regenerate.
1526         * mt-desc.h: Regenerate.
1527         * mt-opc.h: Regenerate.
1528         * or1k-desc.h: Regenerate.
1529         * or1k-opc.h: Regenerate.
1530         * xc16x-desc.h: Regenerate.
1531         * xc16x-opc.h: Regenerate.
1532         * xstormy16-desc.h: Regenerate.
1533         * xstormy16-opc.h: Regenerate.
1534
1535 2017-01-02  Alan Modra  <amodra@gmail.com>
1536
1537         Update year range in copyright notice of all files.
1538
1539 For older changes see ChangeLog-2016
1540 \f
1541 Copyright (C) 2017 Free Software Foundation, Inc.
1542
1543 Copying and distribution of this file, with or without modification,
1544 are permitted in any medium without royalty provided the copyright
1545 notice and this notice are preserved.
1546
1547 Local Variables:
1548 mode: change-log
1549 left-margin: 8
1550 fill-column: 74
1551 version-control: never
1552 End: