opcodes/ChangeLog

   1 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
   2
   3         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
   4         changed.
   5
   6 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
   7
   8         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
   9         c.mv/c.li if rs1 is zero.
  10
  11 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
  12
  13         * i386-gen.c (cpu_flag_init): Replace CpuABM with
  14         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
  15         CPU_POPCNT_FLAGS.
  16         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
  17         * i386-opc.h (CpuABM): Removed.
  18         (CpuPOPCNT): New.
  19         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  20         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  21         popcnt.  Remove CpuABM from lzcnt.
  22         * i386-init.h: Regenerated.
  23         * i386-tbl.h: Likewise.
  24
  25 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
  28         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
  29         VexW1 instead of open-coding them.
  30         * i386-tbl.h: Re-generate.
  31
  32 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-opc.tbl (AddrPrefixOpReg): Define.
  35         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
  36         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
  37         templates. Drop NoRex64.
  38         * i386-tbl.h: Re-generate.
  39
  40 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  41
  42         PR gas/6518
  43         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  44         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
  45         into Intel syntax instance (with Unpsecified) and AT&T one
  46         (without).
  47         (vcvtneps2bf16): Likewise, along with folding the two so far
  48         separate ones.
  49         * i386-tbl.h: Re-generate.
  50
  51 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  52
  53         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
  54         CPU_ANY_SSE4A_FLAGS.
  55
  56 2020-02-17  Alan Modra  <amodra@gmail.com>
  57
  58         * i386-gen.c (cpu_flag_init): Correct last change.
  59
  60 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  61
  62         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
  63         CPU_ANY_SSE4_FLAGS.
  64
  65 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         * i386-opc.tbl (movsx): Remove Intel syntax comments.
  68         (movzx): Likewise.
  69
  70 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  71
  72         PR gas/25438
  73         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  74         destination for Cpu64-only variant.
  75         (movzx): Fold patterns.
  76         * i386-tbl.h: Re-generate.
  77
  78 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  81         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  82         CPU_ANY_SSE4_FLAGS entry.
  83         * i386-init.h: Re-generate.
  84
  85 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  88         with Unspecified, making the present one AT&T syntax only.
  89         * i386-tbl.h: Re-generate.
  90
  91 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  94         * i386-tbl.h: Re-generate.
  95
  96 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  97
  98         PR gas/24546
  99         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 100         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 101         Amd64 and Intel64 templates.
 102         (call, jmp): Likewise for far indirect variants. Dro
 103         Unspecified.
 104         * i386-tbl.h: Re-generate.
 105
 106 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 107
 108         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 109         * i386-opc.h (ShortForm): Delete.
 110         (struct i386_opcode_modifier): Remove shortform field.
 111         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 112         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 113         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 114         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 115         Drop ShortForm.
 116         * i386-tbl.h: Re-generate.
 117
 118 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 119
 120         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 121         fucompi): Drop ShortForm from operand-less templates.
 122         * i386-tbl.h: Re-generate.
 123
 124 2020-02-11  Alan Modra  <amodra@gmail.com>
 125
 126         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 127         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 128         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 129         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 130         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 131
 132 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 133
 134         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 135         (cde_opcodes): Add VCX* instructions.
 136
 137 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 138             Matthew Malcomson  <matthew.malcomson@arm.com>
 139
 140         * arm-dis.c (struct cdeopcode32): New.
 141         (CDE_OPCODE): New macro.
 142         (cde_opcodes): New disassembly table.
 143         (regnames): New option to table.
 144         (cde_coprocs): New global variable.
 145         (print_insn_cde): New
 146         (print_insn_thumb32): Use print_insn_cde.
 147         (parse_arm_disassembler_options): Parse coprocN args.
 148
 149 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         PR gas/25516
 152         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 153         with ISA64.
 154         * i386-opc.h (AMD64): Removed.
 155         (Intel64): Likewose.
 156         (AMD64): New.
 157         (INTEL64): Likewise.
 158         (INTEL64ONLY): Likewise.
 159         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 160         * i386-opc.tbl (Amd64): New.
 161         (Intel64): Likewise.
 162         (Intel64Only): Likewise.
 163         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 164         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 165         * i386-tbl.h: Regenerated.
 166
 167 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 168
 169         PR 25469
 170         * z80-dis.c: Add support for GBZ80 opcodes.
 171
 172 2020-02-04  Alan Modra  <amodra@gmail.com>
 173
 174         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 175
 176 2020-02-03  Alan Modra  <amodra@gmail.com>
 177
 178         * m32c-ibld.c: Regenerate.
 179
 180 2020-02-01  Alan Modra  <amodra@gmail.com>
 181
 182         * frv-ibld.c: Regenerate.
 183
 184 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 187         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 188         (OP_E_memory): Replace xmm_mdq_mode case label by
 189         vex_scalar_w_dq_mode one.
 190         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 191
 192 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 193
 194         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 195         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 196         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 197         (intel_operand_size): Drop vex_w_dq_mode case label.
 198
 199 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 200
 201         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 202         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 203
 204 2020-01-30  Alan Modra  <amodra@gmail.com>
 205
 206         * m32c-ibld.c: Regenerate.
 207
 208 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 209
 210         * bpf-opc.c: Regenerate.
 211
 212 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 213
 214         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 215         (dis386): Use them to replace C2/C3 table entries.
 216         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 217         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 218         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 219         * i386-tbl.h: Re-generate.
 220
 221 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 224         forms.
 225         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 226         DefaultSize.
 227         * i386-tbl.h: Re-generate.
 228
 229 2020-01-30  Alan Modra  <amodra@gmail.com>
 230
 231         * tic4x-dis.c (tic4x_dp): Make unsigned.
 232
 233 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 234             Jan Beulich  <jbeulich@suse.com>
 235
 236         PR binutils/25445
 237         * i386-dis.c (MOVSXD_Fixup): New function.
 238         (movsxd_mode): New enum.
 239         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 240         (intel_operand_size): Handle movsxd_mode.
 241         (OP_E_register): Likewise.
 242         (OP_G): Likewise.
 243         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 244         register on movsxd.  Add movsxd with 16-bit destination register
 245         for AMD64 and Intel64 ISAs.
 246         * i386-tbl.h: Regenerated.
 247
 248 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 249
 250         PR 25403
 251         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 252         * aarch64-asm-2.c: Regenerate
 253         * aarch64-dis-2.c: Likewise.
 254         * aarch64-opc-2.c: Likewise.
 255
 256 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-opc.tbl (sysret): Drop DefaultSize.
 259         * i386-tbl.h: Re-generate.
 260
 261 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 262
 263         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 264         Dword.
 265         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 266         * i386-tbl.h: Re-generate.
 267
 268 2020-01-20  Nick Clifton  <nickc@redhat.com>
 269
 270         * po/de.po: Updated German translation.
 271         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 272         * po/uk.po: Updated Ukranian translation.
 273
 274 2020-01-20  Alan Modra  <amodra@gmail.com>
 275
 276         * hppa-dis.c (fput_const): Remove useless cast.
 277
 278 2020-01-20  Alan Modra  <amodra@gmail.com>
 279
 280         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 281
 282 2020-01-18  Nick Clifton  <nickc@redhat.com>
 283
 284         * configure: Regenerate.
 285         * po/opcodes.pot: Regenerate.
 286
 287 2020-01-18  Nick Clifton  <nickc@redhat.com>
 288
 289         Binutils 2.34 branch created.
 290
 291 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 292
 293         * opintl.h: Fix spelling error (seperate).
 294
 295 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 296
 297         * i386-opc.tbl: Add {vex} pseudo prefix.
 298         * i386-tbl.h: Regenerated.
 299
 300 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 301
 302         PR 25376
 303         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 304         (neon_opcodes): Likewise.
 305         (select_arm_features): Make sure we enable MVE bits when selecting
 306         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 307         any architecture.
 308
 309 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-opc.tbl: Drop stale comment from XOP section.
 312
 313 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 316         (extractps): Add VexWIG to SSE2AVX forms.
 317         * i386-tbl.h: Re-generate.
 318
 319 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 322         Size64 from and use VexW1 on SSE2AVX forms.
 323         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 324         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 325         * i386-tbl.h: Re-generate.
 326
 327 2020-01-15  Alan Modra  <amodra@gmail.com>
 328
 329         * tic4x-dis.c (tic4x_version): Make unsigned long.
 330         (optab, optab_special, registernames): New file scope vars.
 331         (tic4x_print_register): Set up registernames rather than
 332         malloc'd registertable.
 333         (tic4x_disassemble): Delete optable and optable_special.  Use
 334         optab and optab_special instead.  Throw away old optab,
 335         optab_special and registernames when info->mach changes.
 336
 337 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 338
 339         PR 25377
 340         * z80-dis.c (suffix): Use .db instruction to generate double
 341         prefix.
 342
 343 2020-01-14  Alan Modra  <amodra@gmail.com>
 344
 345         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 346         values to unsigned before shifting.
 347
 348 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 349
 350         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 351         flow instructions.
 352         (print_insn_thumb16, print_insn_thumb32): Likewise.
 353         (print_insn): Initialize the insn info.
 354         * i386-dis.c (print_insn): Initialize the insn info fields, and
 355         detect jumps.
 356
 357 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 358
 359         * arc-opc.c (C_NE): Make it required.
 360
 361 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 362
 363         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 364         reserved register name.
 365
 366 2020-01-13  Alan Modra  <amodra@gmail.com>
 367
 368         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 369         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 370
 371 2020-01-13  Alan Modra  <amodra@gmail.com>
 372
 373         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 374         result of wasm_read_leb128 in a uint64_t and check that bits
 375         are not lost when copying to other locals.  Use uint32_t for
 376         most locals.  Use PRId64 when printing int64_t.
 377
 378 2020-01-13  Alan Modra  <amodra@gmail.com>
 379
 380         * score-dis.c: Formatting.
 381         * score7-dis.c: Formatting.
 382
 383 2020-01-13  Alan Modra  <amodra@gmail.com>
 384
 385         * score-dis.c (print_insn_score48): Use unsigned variables for
 386         unsigned values.  Don't left shift negative values.
 387         (print_insn_score32): Likewise.
 388         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 389
 390 2020-01-13  Alan Modra  <amodra@gmail.com>
 391
 392         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 393
 394 2020-01-13  Alan Modra  <amodra@gmail.com>
 395
 396         * fr30-ibld.c: Regenerate.
 397
 398 2020-01-13  Alan Modra  <amodra@gmail.com>
 399
 400         * xgate-dis.c (print_insn): Don't left shift signed value.
 401         (ripBits): Formatting, use 1u.
 402
 403 2020-01-10  Alan Modra  <amodra@gmail.com>
 404
 405         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 406         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 407
 408 2020-01-10  Alan Modra  <amodra@gmail.com>
 409
 410         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 411         and XRREG value earlier to avoid a shift with negative exponent.
 412         * m10200-dis.c (disassemble): Similarly.
 413
 414 2020-01-09  Nick Clifton  <nickc@redhat.com>
 415
 416         PR 25224
 417         * z80-dis.c (ld_ii_ii): Use correct cast.
 418
 419 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 420
 421         PR 25224
 422         * z80-dis.c (ld_ii_ii): Use character constant when checking
 423         opcode byte value.
 424
 425 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 426
 427         * i386-dis.c (SEP_Fixup): New.
 428         (SEP): Define.
 429         (dis386_twobyte): Use it for sysenter/sysexit.
 430         (enum x86_64_isa): Change amd64 enumerator to value 1.
 431         (OP_J): Compare isa64 against intel64 instead of amd64.
 432         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 433         forms.
 434         * i386-tbl.h: Re-generate.
 435
 436 2020-01-08  Alan Modra  <amodra@gmail.com>
 437
 438         * z8k-dis.c: Include libiberty.h
 439         (instr_data_s): Make max_fetched unsigned.
 440         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 441         Don't exceed byte_info bounds.
 442         (output_instr): Make num_bytes unsigned.
 443         (unpack_instr): Likewise for nibl_count and loop.
 444         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 445         idx unsigned.
 446         * z8k-opc.h: Regenerate.
 447
 448 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 449
 450         * arc-tbl.h (llock): Use 'LLOCK' as class.
 451         (llockd): Likewise.
 452         (scond): Use 'SCOND' as class.
 453         (scondd): Likewise.
 454         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 455         (scondd): Likewise.
 456
 457 2020-01-06  Alan Modra  <amodra@gmail.com>
 458
 459         * m32c-ibld.c: Regenerate.
 460
 461 2020-01-06  Alan Modra  <amodra@gmail.com>
 462
 463         PR 25344
 464         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 465         Peek at next byte to prevent recursion on repeated prefix bytes.
 466         Ensure uninitialised "mybuf" is not accessed.
 467         (print_insn_z80): Don't zero n_fetch and n_used here,..
 468         (print_insn_z80_buf): ..do it here instead.
 469
 470 2020-01-04  Alan Modra  <amodra@gmail.com>
 471
 472         * m32r-ibld.c: Regenerate.
 473
 474 2020-01-04  Alan Modra  <amodra@gmail.com>
 475
 476         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 477
 478 2020-01-04  Alan Modra  <amodra@gmail.com>
 479
 480         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 481
 482 2020-01-04  Alan Modra  <amodra@gmail.com>
 483
 484         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 485
 486 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 487
 488         * aarch64-tbl.h (aarch64_opcode_table): Use
 489         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 490
 491 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 492
 493         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 494         forms of SUDOT and USDOT.
 495
 496 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 497
 498         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 499         uzip{1,2}.
 500         * opcodes/aarch64-dis-2.c: Re-generate.
 501
 502 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 503
 504         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 505         FMMLA encoding.
 506         * opcodes/aarch64-dis-2.c: Re-generate.
 507
 508 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 509
 510         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 511
 512 2020-01-01  Alan Modra  <amodra@gmail.com>
 513
 514         Update year range in copyright notice of all files.
 515
 516 For older changes see ChangeLog-2019
 517 \f
 518 Copyright (C) 2020 Free Software Foundation, Inc.
 519
 520 Copying and distribution of this file, with or without modification,
 521 are permitted in any medium without royalty provided the copyright
 522 notice and this notice are preserved.
 523
 524 Local Variables:
 525 mode: change-log
 526 left-margin: 8
 527 fill-column: 74
 528 version-control: never
 529 End: