opcodes/ChangeLog

   1 2017-12-01  Peter Bergner  <bergner@vnet.ibm.com>
   2
   3         * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
   4         (operand_value_powerpc): Update return and argument type.
   5         <value, top>: Update type.
   6         (skip_optional_operands): Update argument type.
   7         (lookup_powerpc): Likewise.
   8         (lookup_vle): Likewise.
   9         <table_opcd, table_mask, insn2>: Update type.
  10         (lookup_spe2): Update argument type.
  11         <table_opcd, table_mask, insn2>: Update type.
  12         (print_insn_powerpc) <insn, value>: Update type.
  13         Use PPC_INT_FMT for printing instructions and operands.
  14         * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
  15         insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
  16         insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
  17         extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
  18         extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
  19         insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
  20         extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
  21         insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
  22         extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
  23         insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
  24         extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
  25         insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
  26         extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
  27         insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
  28         extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
  29         insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
  30         extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
  31         insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
  32         extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
  33         extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
  34         extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
  35         insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
  36         extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
  37         insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
  38         extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
  39         extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
  40         (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
  41         BD24, BBO, Y_MASK  , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
  42         DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
  43         SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
  44         VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
  45         VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
  46         VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
  47         XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
  48         XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
  49         XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
  50         XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
  51
  52 2017-11-29  Jan Beulich  <jbeulich@suse.com>
  53
  54         * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
  55         New.
  56         (output_cpu_flags): Update active_cpu_flags.
  57         (process_i386_opcode_modifier): Update active_isstring.
  58         (output_operand_type): Rename "macro"   parameter to "stage",
  59         changing its type.
  60         (process_i386_operand_type): Likewise. Track presence of
  61         BaseIndex and emit DispN accordingly.
  62         (output_i386_opcode, process_i386_registers,
  63         process_i386_initializers): Adjust calls to
  64         process_i386_operand_type() for its changed parameter type.
  65         * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
  66         all insns operands having BaseIndex set.
  67         * i386-tbl.h: Re-generate.
  68
  69 2017-11-29  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
  72         entry.
  73         (operand_types): Remove Vec_Disp8 entry.
  74         * i386-opc.h (Vec_Disp8): Delete.
  75         (union i386_operand_type): Remove vec_disp8.
  76         (i386-opc.tbl): Remove Vec_Disp8.
  77         * i386-init.h, i386-tbl.h: Re-generate.
  78
  79 2017-11-29  Stefan Stroe  <stroestefan@gmail.com>
  80
  81         * po/Make-in (datadir): Define as @datadir@.
  82         (localedir): Define as @localedir@.
  83         (gnulocaledir, gettextsrcdir): Use @datarootdir@.
  84
  85 2017-11-27  Nick Clifton  <nickc@redhat.com>
  86
  87         * po/zh_CN.po: Updated simplified Chinese translation.
  88
  89 2017-11-24  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
  92         "df" groups.
  93
  94 2017-11-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  95
  96         * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
  97         * i386-tbl.h: Regenerate.
  98
  99 2017-11-23  Jan Beulich  <jbeulich@suse.com>
 100
 101         * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
 102         the 16-bit addressing case.
 103
 104 2017-11-23  Jan Beulich  <jbeulich@suse.com>
 105
 106         * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
 107         (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
 108         * i386-opc.tbl (ud1, ud2b): Add operands.
 109         (ud0): New.
 110         * i386-tbl.h: Re-generate.
 111
 112 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 113
 114         * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
 115         * i386-tbl.h: Regenerate.
 116
 117 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 118
 119         * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
 120         * i386-tbl.h: Regenerate.
 121
 122 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 123
 124         *arc-opc (insert_rhv2): Check h-regs range.
 125
 126 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
 127
 128         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
 129         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
 130
 131 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
 132
 133         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
 134         and AARCH64_FEATURE_F16.
 135
 136 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
 137
 138         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
 139         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
 140         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
 141         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
 142         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
 143         (ldapur, ldapursw, stlur): New.
 144         * aarch64-dis-2.c: Regenerate.
 145
 146 2017-11-16  Jan Beulich  <jbeulich@suse.com>
 147
 148         (get_valid_dis386): Never flag bad opcode when
 149         vex.register_specifier is beyond 7. Always store all four
 150         bits of it. Move 16-/32-bit override in EVEX handling after
 151         all to be overridden bits have been set.
 152         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
 153         Use rex to determine GPR register set.
 154         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
 155         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
 156
 157 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
 160         determine GPR register set.
 161
 162 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
 165         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
 166         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
 167         pass.
 168         (OP_REG_VexI4): Drop low 4 bits check.
 169
 170 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 171
 172         * i386-reg.tbl (axl): Remove Acc and Byte.
 173         * i386-tbl.h: Re-generate.
 174
 175 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
 178         (vex_len_table): Use VPCOM.
 179
 180 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
 183         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
 184         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
 185         vpcmpw): Move up.
 186         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
 187         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
 188         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
 189         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
 190         vpcmpnltuw): New.
 191         * i386-tbl.h: Re-generate.
 192
 193 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
 196         smov, ssca, stos, ssto, xlat): Drop Disp*.
 197         * i386-tbl.h: Re-generate.
 198
 199 2017-11-13  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
 202         xsaveopt64): Add No_qSuf.
 203         * i386-tbl.h: Re-generate.
 204
 205 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 206
 207         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
 208         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
 209         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
 210         sder32_el2, vncr_el2.
 211         (aarch64_sys_reg_supported_p): Likewise.
 212         (aarch64_pstatefields): Add dit register.
 213         (aarch64_pstatefield_supported_p): Likewise.
 214         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
 215         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
 216         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
 217         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
 218         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
 219         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
 220         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 221
 222 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 223
 224         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 225         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 226         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 227         (QL_STLW, QL_STLX): New.
 228
 229 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 230
 231         * aarch64-asm.h (ins_addr_offset): New.
 232         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 233         (aarch64_ins_addr_offset): New.
 234         * aarch64-asm-2.c: Regenerate.
 235         * aarch64-dis.h (ext_addr_offset): New.
 236         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 237         (aarch64_ext_addr_offset): New.
 238         * aarch64-dis-2.c: Regenerate.
 239         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 240         FLD_imm4_2 and FLD_SM3_imm2.
 241         * aarch64-opc.c (fields): Add FLD_imm6_2,
 242         FLD_imm4_2 and FLD_SM3_imm2.
 243         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 244         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 245         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 246         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 247         * aarch64-tbl.h
 248         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 249
 250 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 251
 252         * aarch64-tbl.h
 253         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 254         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 255         (aarch64_feature_fp_16_v8_2): New.
 256         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 257         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 258         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 259
 260 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 261
 262         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 263         (aarch64_feature_sha2, aarch64_feature_aes): New.
 264         (SHA2, AES): New.
 265         (AES_INSN, SHA2_INSN): New.
 266         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 267         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 268          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 269         Change to SHA2_INS.
 270
 271 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 272             Tamar Christina <tamar.christina@arm.com>
 273
 274         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 275         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 276
 277 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 278
 279         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 280
 281 2017-11-07  Alan Modra  <amodra@gmail.com>
 282
 283         * opintl.h: Formatting, comment fixes.
 284         (gettext, ngettext): Redefine when ENABLE_NLS.
 285         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 286         (_): Define using gettext.
 287         (textdomain, bindtextdomain): Use safer "do nothing".
 288
 289 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 290
 291         * arc-dis.c (print_hex): New variable.
 292         (parse_option): Check for hex option.
 293         (print_insn_arc): Use hexadecimal representation for short
 294         immediate values when requested.
 295         (print_arc_disassembler_options): Add hex option to the list.
 296
 297 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 298
 299         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 300         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 301         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 302         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 303         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 304         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 305         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 306         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 307         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 308         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 309         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 310         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 311         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 312         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 313         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 314         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 315         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 316         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 317         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 318         Changed opcodes.
 319         (prealloc, prefetch*): Place them before ld instruction.
 320         * arc-opc.c (skip_this_opcode): Add ARITH class.
 321
 322 2017-10-25  Alan Modra  <amodra@gmail.com>
 323
 324         PR 22348
 325         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 326         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 327         (imm4flag, size_changed): Likewise.
 328         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 329         (words, allWords, processing_argument_number): Likewise.
 330         (cst4flag, size_changed): Likewise.
 331         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 332         (crx_cst4_maps): Rename from cst4_maps.
 333         (crx_no_op_insn): Rename from no_op_insn.
 334
 335 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 336
 337         * riscv-opc.c (match_c_addi16sp) : New function.
 338         (match_c_addi4spn): New function.
 339         (match_c_lui): Don't allow 0-immediate encodings.
 340         (riscv_opcodes) <addi>: Use the above functions.
 341         <add>: Likewise.
 342         <c.addi4spn>: Likewise.
 343         <c.addi16sp>: Likewise.
 344
 345 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 346
 347         * i386-init.h: Regenerate
 348         * i386-tbl.h: Likewise
 349
 350 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 351
 352         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 353         (enum): Add EVEX_W_0F3854_P_2.
 354         * i386-dis-evex.h (evex_table): Updated.
 355         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 356         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 357         (cpu_flags): Add CpuAVX512_BITALG.
 358         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 359         (i386_cpu_flags): Add cpuavx512_bitalg..
 360         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 361         * i386-init.h: Regenerate.
 362         * i386-tbl.h: Likewise.
 363
 364 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 365
 366         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 367         * i386-dis-evex.h (evex_table): Updated.
 368         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 369         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 370         (cpu_flags): Add CpuAVX512_VNNI.
 371         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 372         (i386_cpu_flags): Add cpuavx512_vnni.
 373         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 374         * i386-init.h: Regenerate.
 375         * i386-tbl.h: Likewise.
 376
 377 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 378
 379         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 380         (enum): Remove VEX_LEN_0F3A44_P_2.
 381         (vex_len_table): Ditto.
 382         (enum): Remove VEX_W_0F3A44_P_2.
 383         (vew_w_table): Ditto.
 384         (prefix_table): Adjust instructions (see prefixes above).
 385         * i386-dis-evex.h (evex_table):
 386         Add new instructions (see prefixes above).
 387         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 388         (bitfield_cpu_flags): Ditto.
 389         * i386-opc.h (enum): Ditto.
 390         (i386_cpu_flags): Ditto.
 391         (CpuUnused): Comment out to avoid zero-width field problem.
 392         * i386-opc.tbl (vpclmulqdq): New instruction.
 393         * i386-init.h: Regenerate.
 394         * i386-tbl.h: Ditto.
 395
 396 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 397
 398         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 399         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 400         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 401         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 402         (vex_len_table): Ditto.
 403         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 404         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 405         (vew_w_table): Ditto.
 406         (prefix_table): Adjust instructions (see prefixes above).
 407         * i386-dis-evex.h (evex_table):
 408         Add new instructions (see prefixes above).
 409         * i386-gen.c (cpu_flag_init): Add VAES.
 410         (bitfield_cpu_flags): Ditto.
 411         * i386-opc.h (enum): Ditto.
 412         (i386_cpu_flags): Ditto.
 413         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 414         * i386-init.h: Regenerate.
 415         * i386-tbl.h: Ditto.
 416
 417 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 418
 419         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 420         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 421         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 422         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 423         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 424         (prefix_table): Updated (see prefixes above).
 425         (three_byte_table): Likewise.
 426         (vex_w_table): Likewise.
 427         * i386-dis-evex.h: Likewise.
 428         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 429         (cpu_flags): Add CpuGFNI.
 430         * i386-opc.h (enum): Add CpuGFNI.
 431         (i386_cpu_flags): Add cpugfni.
 432         * i386-opc.tbl: Add Intel GFNI instructions.
 433         * i386-init.h: Regenerate.
 434         * i386-tbl.h: Likewise.
 435
 436 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 437
 438         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 439         Define EXbScalar and EXwScalar for OP_EX.
 440         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 441         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 442         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 443         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 444         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 445         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 446         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 447         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 448         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 449         (OP_E_memory): Likewise.
 450         * i386-dis-evex.h: Updated.
 451         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 452         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 453         (cpu_flags): Add CpuAVX512_VBMI2.
 454         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 455         (i386_cpu_flags): Add cpuavx512_vbmi2.
 456         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 457         * i386-init.h: Regenerate.
 458         * i386-tbl.h: Likewise.
 459
 460 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 461
 462         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 463
 464 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 465
 466         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 467         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 468         K15. Add jmpix pattern.
 469
 470 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 471
 472         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 473
 474 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 475
 476         * s390-opc.c (INSTR_SI_RD): New macro.
 477         (INSTR_S_RD): Adjust example instruction.
 478         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 479         SI_RD.
 480
 481 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 482
 483         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 484         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 485         VLE multimple load/store instructions. Old e_ldm* variants are
 486         kept as aliases.
 487         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 488
 489 2017-09-27  Nick Clifton  <nickc@redhat.com>
 490
 491         PR 22179
 492         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 493         names for the fmv.x.s and fmv.s.x instructions respectively.
 494
 495 2017-09-26  do  <do@nerilex.org>
 496
 497         PR 22123
 498         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 499         be used on CPUs that have emacs support.
 500
 501 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 502
 503         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 504
 505 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 506
 507         * nds32-asm.c: Rename __BIT() to N32_BIT().
 508         * nds32-asm.h: Likewise.
 509         * nds32-dis.c: Likewise.
 510
 511 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 512
 513         * i386-dis.c (last_active_prefix): Removed.
 514         (ckprefix): Don't set last_active_prefix.
 515         (NOTRACK_Fixup): Don't check last_active_prefix.
 516
 517 2017-08-31  Nick Clifton  <nickc@redhat.com>
 518
 519         * po/fr.po: Updated French translation.
 520
 521 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 522
 523         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 524         fields.
 525
 526 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 527             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 528
 529         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 530         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 531         New entries efs2 and spe2.
 532         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 533         (SPE2_OPCD_SEGS): New macro.
 534         (spe2_opcd_indices): New.
 535         (disassemble_init_powerpc): Handle SPE2 opcodes.
 536         (lookup_spe2): New function.
 537         (print_insn_powerpc): call lookup_spe2.
 538         * ppc-opc.c (insert_evuimm1_ex0): New function.
 539         (extract_evuimm1_ex0): Likewise.
 540         (insert_evuimm_lt8): Likewise.
 541         (extract_evuimm_lt8): Likewise.
 542         (insert_off_spe2): Likewise.
 543         (extract_off_spe2): Likewise.
 544         (insert_Ddd): Likewise.
 545         (extract_Ddd): Likewise.
 546         (DD): New operand.
 547         (EVUIMM_LT8): Likewise.
 548         (EVUIMM_LT16): Adjust.
 549         (MMMM): New operand.
 550         (EVUIMM_1): Likewise.
 551         (EVUIMM_1_EX0): Likewise.
 552         (EVUIMM_2): Adjust.
 553         (NNN): New operand.
 554         (VX_OFF_SPE2): Likewise.
 555         (BBB): Likewise.
 556         (DDD): Likewise.
 557         (VX_MASK_DDD): New mask.
 558         (HH): New operand.
 559         (VX_RA_CONST): New macro.
 560         (VX_RA_CONST_MASK): Likewise.
 561         (VX_RB_CONST): Likewise.
 562         (VX_RB_CONST_MASK): Likewise.
 563         (VX_OFF_SPE2_MASK): Likewise.
 564         (VX_SPE_CRFD): Likewise.
 565         (VX_SPE_CRFD_MASK VX): Likewise.
 566         (VX_SPE2_CLR): Likewise.
 567         (VX_SPE2_CLR_MASK): Likewise.
 568         (VX_SPE2_SPLATB): Likewise.
 569         (VX_SPE2_SPLATB_MASK): Likewise.
 570         (VX_SPE2_OCTET): Likewise.
 571         (VX_SPE2_OCTET_MASK): Likewise.
 572         (VX_SPE2_DDHH): Likewise.
 573         (VX_SPE2_DDHH_MASK): Likewise.
 574         (VX_SPE2_HH): Likewise.
 575         (VX_SPE2_HH_MASK): Likewise.
 576         (VX_SPE2_EVMAR): Likewise.
 577         (VX_SPE2_EVMAR_MASK): Likewise.
 578         (PPCSPE2): Likewise.
 579         (PPCEFS2): Likewise.
 580         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 581         (powerpc_macros): Map old SPE instructions have new names
 582         with the same opcodes. Add SPE2 instructions which just are
 583         mapped to SPE2.
 584         (spe2_opcodes): Add SPE2 opcodes.
 585
 586 2017-08-23  Alan Modra  <amodra@gmail.com>
 587
 588         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 589         extract functions earlier, deleting forward declarations.
 590         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 591         RA_MASK.
 592
 593 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 594
 595         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 596
 597 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 598             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 599
 600         * ppc-opc.c (insert_evuimm2_ex0): New function.
 601         (extract_evuimm2_ex0): Likewise.
 602         (insert_evuimm4_ex0): Likewise.
 603         (extract_evuimm4_ex0): Likewise.
 604         (insert_evuimm8_ex0): Likewise.
 605         (extract_evuimm8_ex0): Likewise.
 606         (insert_evuimm_lt16): Likewise.
 607         (extract_evuimm_lt16): Likewise.
 608         (insert_rD_rS_even): Likewise.
 609         (extract_rD_rS_even): Likewise.
 610         (insert_off_lsp): Likewise.
 611         (extract_off_lsp): Likewise.
 612         (RD_EVEN): New operand.
 613         (RS_EVEN): Likewise.
 614         (RSQ): Adjust.
 615         (EVUIMM_LT16): New operand.
 616         (HTM_SI): Adjust.
 617         (EVUIMM_2_EX0): New operand.
 618         (EVUIMM_4): Adjust.
 619         (EVUIMM_4_EX0): New operand.
 620         (EVUIMM_8): Adjust.
 621         (EVUIMM_8_EX0): New operand.
 622         (WS): Adjust.
 623         (VX_OFF): New operand.
 624         (VX_LSP): New macro.
 625         (VX_LSP_MASK): Likewise.
 626         (VX_LSP_OFF_MASK): Likewise.
 627         (PPC_OPCODE_LSP): Likewise.
 628         (vle_opcodes): Add LSP opcodes.
 629         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 630
 631 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 632
 633         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 634         register operands in CRC instructions.
 635         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 636         comments.
 637
 638 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 639
 640         * disassemble.c (disassembler): Mark big and mach with
 641         ATTRIBUTE_UNUSED.
 642
 643 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 644
 645         * disassemble.c (disassembler): Remove arch/mach/endian
 646         assertions.
 647
 648 2017-07-25  Nick Clifton  <nickc@redhat.com>
 649
 650         PR 21739
 651         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 652         message.
 653         (insert_r0): Likewise.
 654         (insert_r1): Likewise.
 655         (insert_r2): Likewise.
 656         (insert_r3): Likewise.
 657         (insert_sp): Likewise.
 658         (insert_gp): Likewise.
 659         (insert_pcl): Likewise.
 660         (insert_blink): Likewise.
 661         (insert_ilink1): Likewise.
 662         (insert_ilink2): Likewise.
 663         (insert_ras): Likewise.
 664         (insert_rbs): Likewise.
 665         (insert_rcs): Likewise.
 666         (insert_simm3s): Likewise.
 667         (insert_rrange): Likewise.
 668         (insert_r13el): Likewise.
 669         (insert_fpel): Likewise.
 670         (insert_blinkel): Likewise.
 671         (insert_pclel): Likewise.
 672         (insert_nps_bitop_size_2b): Likewise.
 673         (insert_nps_imm_offset): Likewise.
 674         (insert_nps_imm_entry): Likewise.
 675         (insert_nps_size_16bit): Likewise.
 676         (insert_nps_##NAME##_pos): Likewise.
 677         (insert_nps_##NAME): Likewise.
 678         (insert_nps_bitop_ins_ext): Likewise.
 679         (insert_nps_##NAME): Likewise.
 680         (insert_nps_min_hofs): Likewise.
 681         (insert_nps_##NAME): Likewise.
 682         (insert_nps_rbdouble_64): Likewise.
 683         (insert_nps_misc_imm_offset): Likewise.
 684         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 685         option description.
 686
 687 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 688             Jiong Wang  <jiong.wang@arm.com>
 689
 690         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 691         correct the print.
 692         * aarch64-dis-2.c: Regenerated.
 693
 694 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 695
 696         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 697         table.
 698
 699 2017-07-20  Nick Clifton  <nickc@redhat.com>
 700
 701         * po/de.po: Updated German translation.
 702
 703 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 704
 705         * arc-regs.h (sec_stat): New aux register.
 706         (aux_kernel_sp): Likewise.
 707         (aux_sec_u_sp): Likewise.
 708         (aux_sec_k_sp): Likewise.
 709         (sec_vecbase_build): Likewise.
 710         (nsc_table_top): Likewise.
 711         (nsc_table_base): Likewise.
 712         (ersec_stat): Likewise.
 713         (aux_sec_except): Likewise.
 714
 715 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 716
 717         * arc-opc.c (extract_uimm12_20): New function.
 718         (UIMM12_20): New operand.
 719         (SIMM3_5_S): Adjust.
 720         * arc-tbl.h (sjli): Add new instruction.
 721
 722 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 723             John Eric Martin  <John.Martin@emmicro-us.com>
 724
 725         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 726         (UIMM3_23): Adjust accordingly.
 727         * arc-regs.h: Add/correct jli_base register.
 728         * arc-tbl.h (jli_s): Likewise.
 729
 730 2017-07-18  Nick Clifton  <nickc@redhat.com>
 731
 732         PR 21775
 733         * aarch64-opc.c: Fix spelling typos.
 734         * i386-dis.c: Likewise.
 735
 736 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 737
 738         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 739         max_addr_offset and octets variables to size_t.
 740
 741 2017-07-12  Alan Modra  <amodra@gmail.com>
 742
 743         * po/da.po: Update from translationproject.org/latest/opcodes/.
 744         * po/de.po: Likewise.
 745         * po/es.po: Likewise.
 746         * po/fi.po: Likewise.
 747         * po/fr.po: Likewise.
 748         * po/id.po: Likewise.
 749         * po/it.po: Likewise.
 750         * po/nl.po: Likewise.
 751         * po/pt_BR.po: Likewise.
 752         * po/ro.po: Likewise.
 753         * po/sv.po: Likewise.
 754         * po/tr.po: Likewise.
 755         * po/uk.po: Likewise.
 756         * po/vi.po: Likewise.
 757         * po/zh_CN.po: Likewise.
 758
 759 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 760             Alan Modra  <amodra@gmail.com>
 761
 762         * cgen.sh: Mark generated files read-only.
 763         * epiphany-asm.c: Regenerate.
 764         * epiphany-desc.c: Regenerate.
 765         * epiphany-desc.h: Regenerate.
 766         * epiphany-dis.c: Regenerate.
 767         * epiphany-ibld.c: Regenerate.
 768         * epiphany-opc.c: Regenerate.
 769         * epiphany-opc.h: Regenerate.
 770         * fr30-asm.c: Regenerate.
 771         * fr30-desc.c: Regenerate.
 772         * fr30-desc.h: Regenerate.
 773         * fr30-dis.c: Regenerate.
 774         * fr30-ibld.c: Regenerate.
 775         * fr30-opc.c: Regenerate.
 776         * fr30-opc.h: Regenerate.
 777         * frv-asm.c: Regenerate.
 778         * frv-desc.c: Regenerate.
 779         * frv-desc.h: Regenerate.
 780         * frv-dis.c: Regenerate.
 781         * frv-ibld.c: Regenerate.
 782         * frv-opc.c: Regenerate.
 783         * frv-opc.h: Regenerate.
 784         * ip2k-asm.c: Regenerate.
 785         * ip2k-desc.c: Regenerate.
 786         * ip2k-desc.h: Regenerate.
 787         * ip2k-dis.c: Regenerate.
 788         * ip2k-ibld.c: Regenerate.
 789         * ip2k-opc.c: Regenerate.
 790         * ip2k-opc.h: Regenerate.
 791         * iq2000-asm.c: Regenerate.
 792         * iq2000-desc.c: Regenerate.
 793         * iq2000-desc.h: Regenerate.
 794         * iq2000-dis.c: Regenerate.
 795         * iq2000-ibld.c: Regenerate.
 796         * iq2000-opc.c: Regenerate.
 797         * iq2000-opc.h: Regenerate.
 798         * lm32-asm.c: Regenerate.
 799         * lm32-desc.c: Regenerate.
 800         * lm32-desc.h: Regenerate.
 801         * lm32-dis.c: Regenerate.
 802         * lm32-ibld.c: Regenerate.
 803         * lm32-opc.c: Regenerate.
 804         * lm32-opc.h: Regenerate.
 805         * lm32-opinst.c: Regenerate.
 806         * m32c-asm.c: Regenerate.
 807         * m32c-desc.c: Regenerate.
 808         * m32c-desc.h: Regenerate.
 809         * m32c-dis.c: Regenerate.
 810         * m32c-ibld.c: Regenerate.
 811         * m32c-opc.c: Regenerate.
 812         * m32c-opc.h: Regenerate.
 813         * m32r-asm.c: Regenerate.
 814         * m32r-desc.c: Regenerate.
 815         * m32r-desc.h: Regenerate.
 816         * m32r-dis.c: Regenerate.
 817         * m32r-ibld.c: Regenerate.
 818         * m32r-opc.c: Regenerate.
 819         * m32r-opc.h: Regenerate.
 820         * m32r-opinst.c: Regenerate.
 821         * mep-asm.c: Regenerate.
 822         * mep-desc.c: Regenerate.
 823         * mep-desc.h: Regenerate.
 824         * mep-dis.c: Regenerate.
 825         * mep-ibld.c: Regenerate.
 826         * mep-opc.c: Regenerate.
 827         * mep-opc.h: Regenerate.
 828         * mt-asm.c: Regenerate.
 829         * mt-desc.c: Regenerate.
 830         * mt-desc.h: Regenerate.
 831         * mt-dis.c: Regenerate.
 832         * mt-ibld.c: Regenerate.
 833         * mt-opc.c: Regenerate.
 834         * mt-opc.h: Regenerate.
 835         * or1k-asm.c: Regenerate.
 836         * or1k-desc.c: Regenerate.
 837         * or1k-desc.h: Regenerate.
 838         * or1k-dis.c: Regenerate.
 839         * or1k-ibld.c: Regenerate.
 840         * or1k-opc.c: Regenerate.
 841         * or1k-opc.h: Regenerate.
 842         * or1k-opinst.c: Regenerate.
 843         * xc16x-asm.c: Regenerate.
 844         * xc16x-desc.c: Regenerate.
 845         * xc16x-desc.h: Regenerate.
 846         * xc16x-dis.c: Regenerate.
 847         * xc16x-ibld.c: Regenerate.
 848         * xc16x-opc.c: Regenerate.
 849         * xc16x-opc.h: Regenerate.
 850         * xstormy16-asm.c: Regenerate.
 851         * xstormy16-desc.c: Regenerate.
 852         * xstormy16-desc.h: Regenerate.
 853         * xstormy16-dis.c: Regenerate.
 854         * xstormy16-ibld.c: Regenerate.
 855         * xstormy16-opc.c: Regenerate.
 856         * xstormy16-opc.h: Regenerate.
 857
 858 2017-07-07  Alan Modra  <amodra@gmail.com>
 859
 860         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 861         * m32c-dis.c: Regenerate.
 862         * mep-dis.c: Regenerate.
 863
 864 2017-07-05  Borislav Petkov  <bp@suse.de>
 865
 866         * i386-dis.c: Enable ModRM.reg /6 aliases.
 867
 868 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 869
 870         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 871         with vmrs and vmsr.
 872
 873 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 874
 875         * configure: Regenerate.
 876
 877 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 878
 879         * po/opcodes.pot: Regenerate.
 880
 881 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 882
 883         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 884         entries to the MSA ASE instruction block.
 885
 886 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 887             Maciej W. Rozycki  <macro@imgtec.com>
 888
 889         * micromips-opc.c (XPA, XPAVZ): New macros.
 890         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 891         "mthgc0".
 892
 893 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 894             Maciej W. Rozycki  <macro@imgtec.com>
 895
 896         * micromips-opc.c (I36): New macro.
 897         (micromips_opcodes): Add "eretnc".
 898
 899 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 900             Andrew Bennett  <andrew.bennett@imgtec.com>
 901
 902         * mips-dis.c (mips_calculate_combination_ases): Handle the
 903         ASE_XPA_VIRT flag.
 904         (parse_mips_ase_option): New function.
 905         (parse_mips_dis_option): Factor out ASE option handling to the
 906         new function.  Call `mips_calculate_combination_ases'.
 907         * mips-opc.c (XPAVZ): New macro.
 908         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 909         "mfhgc0", "mthc0" and "mthgc0".
 910
 911 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 912
 913         * mips-dis.c (mips_calculate_combination_ases): New function.
 914         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 915         calculation to the new function.
 916         (set_default_mips_dis_options): Call the new function.
 917
 918 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 919
 920         * arc-dis.c (parse_disassembler_options): Use
 921         FOR_EACH_DISASSEMBLER_OPTION.
 922
 923 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 924
 925         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 926         disassembler option strings.
 927         (parse_cpu_option): Likewise.
 928
 929 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 930
 931         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 932         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 933         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 934         (aarch64_feature_dotprod, DOT_INSN): New.
 935         (udot, sdot): New.
 936         * aarch64-dis-2.c: Regenerated.
 937
 938 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 939
 940         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 941
 942 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 943             Matthew Fortune  <matthew.fortune@imgtec.com>
 944             Andrew Bennett  <andrew.bennett@imgtec.com>
 945
 946         * mips-formats.h (INT_BIAS): New macro.
 947         (INT_ADJ): Redefine in INT_BIAS terms.
 948         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 949         (mips_print_save_restore): New function.
 950         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 951         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 952         call.
 953         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 954         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 955         OP_SAVE_RESTORE_LIST handling, factored out from here.
 956         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 957         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 958         (mips_builtin_opcodes): Add "restore" and "save" entries.
 959         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 960         (IAMR2): New macro.
 961         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 962
 963 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 964
 965         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 966         alias; do not mark SLTI instruction as an alias.
 967
 968 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 969
 970         * i386-dis.c (RM_0FAE_REG_5): Removed.
 971         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 972         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 973         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 974         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 975         PREFIX_MOD_3_0F01_REG_5_RM_0.
 976         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 977         PREFIX_MOD_3_0FAE_REG_5.
 978         (mod_table): Update MOD_0FAE_REG_5.
 979         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 980         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 981         * i386-tbl.h: Regenerated.
 982
 983 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 984
 985         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 986         * i386-opc.tbl: Likewise.
 987         * i386-tbl.h: Regenerated.
 988
 989 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 990
 991         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 992         and "jmp{&|}".
 993         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 994         prefix.
 995
 996 2017-06-19  Nick Clifton  <nickc@redhat.com>
 997
 998         PR binutils/21614
 999         * score-dis.c (score_opcodes): Add sentinel.
1000
1001 2017-06-16  Alan Modra  <amodra@gmail.com>
1002
1003         * rx-decode.c: Regenerate.
1004
1005 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
1006
1007         PR binutils/21594
1008         * i386-dis.c (OP_E_register): Check valid bnd register.
1009         (OP_G): Likewise.
1010
1011 2017-06-15  Nick Clifton  <nickc@redhat.com>
1012
1013         PR binutils/21595
1014         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1015         range value.
1016
1017 2017-06-15  Nick Clifton  <nickc@redhat.com>
1018
1019         PR binutils/21588
1020         * rl78-decode.opc (OP_BUF_LEN): Define.
1021         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1022         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1023         array.
1024         * rl78-decode.c: Regenerate.
1025
1026 2017-06-15  Nick Clifton  <nickc@redhat.com>
1027
1028         PR binutils/21586
1029         * bfin-dis.c (gregs): Clip index to prevent overflow.
1030         (regs): Likewise.
1031         (regs_lo): Likewise.
1032         (regs_hi): Likewise.
1033
1034 2017-06-14  Nick Clifton  <nickc@redhat.com>
1035
1036         PR binutils/21576
1037         * score7-dis.c (score_opcodes): Add sentinel.
1038
1039 2017-06-14  Yao Qi  <yao.qi@linaro.org>
1040
1041         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1042         * arm-dis.c: Likewise.
1043         * ia64-dis.c: Likewise.
1044         * mips-dis.c: Likewise.
1045         * spu-dis.c: Likewise.
1046         * disassemble.h (print_insn_aarch64): New declaration, moved from
1047         include/dis-asm.h.
1048         (print_insn_big_arm, print_insn_big_mips): Likewise.
1049         (print_insn_i386, print_insn_ia64): Likewise.
1050         (print_insn_little_arm, print_insn_little_mips): Likewise.
1051
1052 2017-06-14  Nick Clifton  <nickc@redhat.com>
1053
1054         PR binutils/21587
1055         * rx-decode.opc: Include libiberty.h
1056         (GET_SCALE): New macro - validates access to SCALE array.
1057         (GET_PSCALE): New macro - validates access to PSCALE array.
1058         (DIs, SIs, S2Is, rx_disp): Use new macros.
1059         * rx-decode.c: Regenerate.
1060
1061 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1062
1063         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1064
1065 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
1066
1067         * arc-dis.c (enforced_isa_mask): Declare.
1068         (cpu_types): Likewise.
1069         (parse_cpu_option): New function.
1070         (parse_disassembler_options): Use it.
1071         (print_insn_arc): Use enforced_isa_mask.
1072         (print_arc_disassembler_options): Document new options.
1073
1074 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1075
1076         * alpha-dis.c: Include disassemble.h, don't include
1077         dis-asm.h.
1078         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1079         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1080         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1081         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1082         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1083         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1084         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1085         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1086         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1087         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1088         * moxie-dis.c, msp430-dis.c, mt-dis.c:
1089         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1090         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1091         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1092         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1093         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1094         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1095         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1096         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1097         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1098         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1099         * z80-dis.c, z8k-dis.c: Likewise.
1100         * disassemble.h: New file.
1101
1102 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1103
1104         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1105         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1106
1107 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1108
1109         * disassemble.c (disassembler): Add arguments a, big and mach.
1110         Use them.
1111
1112 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
1113
1114         * i386-dis.c (NOTRACK_Fixup): New.
1115         (NOTRACK): Likewise.
1116         (NOTRACK_PREFIX): Likewise.
1117         (last_active_prefix): Likewise.
1118         (reg_table): Use NOTRACK on indirect call and jmp.
1119         (ckprefix): Set last_active_prefix.
1120         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1121         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1122         * i386-opc.h (NoTrackPrefixOk): New.
1123         (i386_opcode_modifier): Add notrackprefixok.
1124         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1125         Add notrack.
1126         * i386-tbl.h: Regenerated.
1127
1128 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1129
1130         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1131         (X_IMM2): Define.
1132         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1133         bfd_mach_sparc_v9m8.
1134         (print_insn_sparc): Handle new operand types.
1135         * sparc-opc.c (MASK_M8): Define.
1136         (v6): Add MASK_M8.
1137         (v6notlet): Likewise.
1138         (v7): Likewise.
1139         (v8): Likewise.
1140         (v9): Likewise.
1141         (v9a): Likewise.
1142         (v9b): Likewise.
1143         (v9c): Likewise.
1144         (v9d): Likewise.
1145         (v9e): Likewise.
1146         (v9v): Likewise.
1147         (v9m): Likewise.
1148         (v9andleon): Likewise.
1149         (m8): Define.
1150         (HWS_VM8): Define.
1151         (HWS2_VM8): Likewise.
1152         (sparc_opcode_archs): Add entry for "m8".
1153         (sparc_opcodes): Add OSA2017 and M8 instructions
1154         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1155         fpx{ll,ra,rl}64x,
1156         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1157         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1158         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1159         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1160         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1161         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1162         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1163         ASI_CORE_SELECT_COMMIT_NHT.
1164
1165 2017-05-18  Alan Modra  <amodra@gmail.com>
1166
1167         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1168         * aarch64-dis.c: Likewise.
1169         * aarch64-gen.c: Likewise.
1170         * aarch64-opc.c: Likewise.
1171
1172 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1173             Matthew Fortune  <matthew.fortune@imgtec.com>
1174
1175         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1176         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1177         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1178         (print_insn_arg) <OP_REG28>: Add handler.
1179         (validate_insn_args) <OP_REG28>: Handle.
1180         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1181         32-bit encoding and 9-bit immediates.
1182         (print_insn_mips16): Handle MIPS16 instructions that require
1183         32-bit encoding and MFC0/MTC0 operand decoding.
1184         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1185         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1186         (RD_C0, WR_C0, E2, E2MT): New macros.
1187         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1188         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1189         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1190         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1191         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1192         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1193         instructions, "swl", "swr", "sync" and its "sync_acquire",
1194         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1195         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1196         regular/extended entries for original MIPS16 ISA revision
1197         instructions whose extended forms are subdecoded in the MIPS16e2
1198         ISA revision: "li", "sll" and "srl".
1199
1200 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1201
1202         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1203         reference in CP0 move operand decoding.
1204
1205 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1206
1207         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1208         type to hexadecimal.
1209         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1210
1211 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1212
1213         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1214         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1215         "sync_rmb" and "sync_wmb" as aliases.
1216         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1217         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1218
1219 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1220
1221         * arc-dis.c (parse_option): Update quarkse_em option..
1222         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1223         QUARKSE1.
1224         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1225
1226 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1227
1228         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1229
1230 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1231
1232         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1233         register.
1234
1235 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1236
1237         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1238         and branches and not synthetic data instructions.
1239
1240 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1241
1242         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1243
1244 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1245
1246         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1247         * arc-opc.c (insert_r13el): New function.
1248         (R13_EL): Define.
1249         * arc-tbl.h: Add new enter/leave variants.
1250
1251 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1252
1253         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1254
1255 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1256
1257         * mips-dis.c (print_mips_disassembler_options): Add
1258         `no-aliases'.
1259
1260 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1261
1262         * mips16-opc.c (AL): New macro.
1263         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1264         of "ld" and "lw" as aliases.
1265
1266 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1267
1268         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1269         arguments.
1270
1271 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1272             Alan Modra  <amodra@gmail.com>
1273
1274         * ppc-opc.c (ELEV): Define.
1275         (vle_opcodes): Add se_rfgi and e_sc.
1276         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1277         for E200Z4.
1278
1279 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1280
1281         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1282
1283 2017-04-21  Nick Clifton  <nickc@redhat.com>
1284
1285         PR binutils/21380
1286         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1287         LD3R and LD4R.
1288
1289 2017-04-13  Alan Modra  <amodra@gmail.com>
1290
1291         * epiphany-desc.c: Regenerate.
1292         * fr30-desc.c: Regenerate.
1293         * frv-desc.c: Regenerate.
1294         * ip2k-desc.c: Regenerate.
1295         * iq2000-desc.c: Regenerate.
1296         * lm32-desc.c: Regenerate.
1297         * m32c-desc.c: Regenerate.
1298         * m32r-desc.c: Regenerate.
1299         * mep-desc.c: Regenerate.
1300         * mt-desc.c: Regenerate.
1301         * or1k-desc.c: Regenerate.
1302         * xc16x-desc.c: Regenerate.
1303         * xstormy16-desc.c: Regenerate.
1304
1305 2017-04-11  Alan Modra  <amodra@gmail.com>
1306
1307         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1308         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1309         PPC_OPCODE_TMR for e6500.
1310         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1311         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1312         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1313         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1314         (PPCHTM): Define as PPC_OPCODE_POWER8.
1315         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1316
1317 2017-04-10  Alan Modra  <amodra@gmail.com>
1318
1319         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1320         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1321         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1322         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1323
1324 2017-04-09  Pip Cet  <pipcet@gmail.com>
1325
1326         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1327         appropriate floating-point precision directly.
1328
1329 2017-04-07  Alan Modra  <amodra@gmail.com>
1330
1331         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1332         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1333         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1334         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1335         vector instructions with E6500 not PPCVEC2.
1336
1337 2017-04-06  Pip Cet  <pipcet@gmail.com>
1338
1339         * Makefile.am: Add wasm32-dis.c.
1340         * configure.ac: Add wasm32-dis.c to wasm32 target.
1341         * disassemble.c: Add wasm32 disassembler code.
1342         * wasm32-dis.c: New file.
1343         * Makefile.in: Regenerate.
1344         * configure: Regenerate.
1345         * po/POTFILES.in: Regenerate.
1346         * po/opcodes.pot: Regenerate.
1347
1348 2017-04-05  Pedro Alves  <palves@redhat.com>
1349
1350         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1351         * arm-dis.c (parse_arm_disassembler_options): Constify.
1352         * ppc-dis.c (powerpc_init_dialect): Constify local.
1353         * vax-dis.c (parse_disassembler_options): Constify.
1354
1355 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1356
1357         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1358         RISCV_GP_SYMBOL.
1359
1360 2017-03-30  Pip Cet  <pipcet@gmail.com>
1361
1362         * configure.ac: Add (empty) bfd_wasm32_arch target.
1363         * configure: Regenerate
1364         * po/opcodes.pot: Regenerate.
1365
1366 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1367
1368         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1369         OSA2015.
1370         * opcodes/sparc-opc.c (asi_table): New ASIs.
1371
1372 2017-03-29  Alan Modra  <amodra@gmail.com>
1373
1374         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1375         "raw" option.
1376         (lookup_powerpc): Don't special case -1 dialect.  Handle
1377         PPC_OPCODE_RAW.
1378         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1379         lookup_powerpc call, pass it on second.
1380
1381 2017-03-27  Alan Modra  <amodra@gmail.com>
1382
1383         PR 21303
1384         * ppc-dis.c (struct ppc_mopt): Comment.
1385         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1386
1387 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1388
1389         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1390         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1391         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1392         (insert_nps_misc_imm_offset): New function.
1393         (extract_nps_misc imm_offset): New function.
1394         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1395         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1396
1397 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1398
1399         * s390-mkopc.c (main): Remove vx2 check.
1400         * s390-opc.txt: Remove vx2 instruction flags.
1401
1402 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1403
1404         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1405         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1406         (insert_nps_imm_offset): New function.
1407         (extract_nps_imm_offset): New function.
1408         (insert_nps_imm_entry): New function.
1409         (extract_nps_imm_entry): New function.
1410
1411 2017-03-17  Alan Modra  <amodra@gmail.com>
1412
1413         PR 21248
1414         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1415         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1416         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1417
1418 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1419
1420         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1421         <c.andi>: Likewise.
1422         <c.addiw> Likewise.
1423
1424 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1425
1426         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1427
1428 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1429
1430         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1431         <srl> Likewise.
1432         <srai> Likewise.
1433         <sra> Likewise.
1434
1435 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1436
1437         * i386-gen.c (opcode_modifiers): Replace S with Load.
1438         * i386-opc.h (S): Removed.
1439         (Load): New.
1440         (i386_opcode_modifier): Replace s with load.
1441         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1442         and {evex}.  Replace S with Load.
1443         * i386-tbl.h: Regenerated.
1444
1445 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1446
1447         * i386-opc.tbl: Use CpuCET on rdsspq.
1448         * i386-tbl.h: Regenerated.
1449
1450 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1451
1452         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1453         <vsx>: Do not use PPC_OPCODE_VSX3;
1454
1455 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1456
1457         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1458
1459 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1460
1461         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1462         (MOD_0F1E_PREFIX_1): Likewise.
1463         (MOD_0F38F5_PREFIX_2): Likewise.
1464         (MOD_0F38F6_PREFIX_0): Likewise.
1465         (RM_0F1E_MOD_3_REG_7): Likewise.
1466         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1467         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1468         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1469         (PREFIX_0F1E): Likewise.
1470         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1471         (PREFIX_0F38F5): Likewise.
1472         (dis386_twobyte): Use PREFIX_0F1E.
1473         (reg_table): Add REG_0F1E_MOD_3.
1474         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1475         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1476         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1477         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1478         (three_byte_table): Use PREFIX_0F38F5.
1479         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1480         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1481         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1482         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1483         PREFIX_MOD_3_0F01_REG_5_RM_2.
1484         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1485         (cpu_flags): Add CpuCET.
1486         * i386-opc.h (CpuCET): New enum.
1487         (CpuUnused): Commented out.
1488         (i386_cpu_flags): Add cpucet.
1489         * i386-opc.tbl: Add Intel CET instructions.
1490         * i386-init.h: Regenerated.
1491         * i386-tbl.h: Likewise.
1492
1493 2017-03-06  Alan Modra  <amodra@gmail.com>
1494
1495         PR 21124
1496         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1497         (extract_raq, extract_ras, extract_rbx): New functions.
1498         (powerpc_operands): Use opposite corresponding insert function.
1499         (Q_MASK): Define.
1500         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1501         register restriction.
1502
1503 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1504
1505         * disassemble.c Include "safe-ctype.h".
1506         (disassemble_init_for_target): Handle s390 init.
1507         (remove_whitespace_and_extra_commas): New function.
1508         (disassembler_options_cmp): Likewise.
1509         * arm-dis.c: Include "libiberty.h".
1510         (NUM_ELEM): Delete.
1511         (regnames): Use long disassembler style names.
1512         Add force-thumb and no-force-thumb options.
1513         (NUM_ARM_REGNAMES): Rename from this...
1514         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1515         (get_arm_regname_num_options): Delete.
1516         (set_arm_regname_option): Likewise.
1517         (get_arm_regnames): Likewise.
1518         (parse_disassembler_options): Likewise.
1519         (parse_arm_disassembler_option): Rename from this...
1520         (parse_arm_disassembler_options): ...to this.  Make static.
1521         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1522         (print_insn): Use parse_arm_disassembler_options.
1523         (disassembler_options_arm): New function.
1524         (print_arm_disassembler_options): Handle updated regnames.
1525         * ppc-dis.c: Include "libiberty.h".
1526         (ppc_opts): Add "32" and "64" entries.
1527         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1528         (powerpc_init_dialect): Add break to switch statement.
1529         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1530         (disassembler_options_powerpc): New function.
1531         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1532         Remove printing of "32" and "64".
1533         * s390-dis.c: Include "libiberty.h".
1534         (init_flag): Remove unneeded variable.
1535         (struct s390_options_t): New structure type.
1536         (options): New structure.
1537         (init_disasm): Rename from this...
1538         (disassemble_init_s390): ...to this.  Add initializations for
1539         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1540         (print_insn_s390): Delete call to init_disasm.
1541         (disassembler_options_s390): New function.
1542         (print_s390_disassembler_options): Print using information from
1543         struct 'options'.
1544         * po/opcodes.pot: Regenerate.
1545
1546 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1547
1548         * i386-dis.c (PCMPESTR_Fixup): New.
1549         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1550         (prefix_table): Use PCMPESTR_Fixup.
1551         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1552         PCMPESTR_Fixup.
1553         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1554         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1555         Split 64-bit and non-64-bit variants.
1556         * opcodes/i386-tbl.h: Re-generate.
1557
1558 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1559
1560         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1561         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1562         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1563         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1564         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1565         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1566         (OP_SVE_V_HSD): New macros.
1567         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1568         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1569         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1570         (aarch64_opcode_table): Add new SVE instructions.
1571         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1572         for rotation operands.  Add new SVE operands.
1573         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1574         (ins_sve_quad_index): Likewise.
1575         (ins_imm_rotate): Split into...
1576         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1577         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1578         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1579         functions.
1580         (aarch64_ins_sve_addr_ri_s4): New function.
1581         (aarch64_ins_sve_quad_index): Likewise.
1582         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1583         * aarch64-asm-2.c: Regenerate.
1584         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1585         (ext_sve_quad_index): Likewise.
1586         (ext_imm_rotate): Split into...
1587         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1588         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1589         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1590         functions.
1591         (aarch64_ext_sve_addr_ri_s4): New function.
1592         (aarch64_ext_sve_quad_index): Likewise.
1593         (aarch64_ext_sve_index): Allow quad indices.
1594         (do_misc_decoding): Likewise.
1595         * aarch64-dis-2.c: Regenerate.
1596         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1597         aarch64_field_kinds.
1598         (OPD_F_OD_MASK): Widen by one bit.
1599         (OPD_F_NO_ZR): Bump accordingly.
1600         (get_operand_field_width): New function.
1601         * aarch64-opc.c (fields): Add new SVE fields.
1602         (operand_general_constraint_met_p): Handle new SVE operands.
1603         (aarch64_print_operand): Likewise.
1604         * aarch64-opc-2.c: Regenerate.
1605
1606 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1607
1608         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1609         (aarch64_feature_compnum): ...this.
1610         (SIMD_V8_3): Replace with...
1611         (COMPNUM): ...this.
1612         (CNUM_INSN): New macro.
1613         (aarch64_opcode_table): Use it for the complex number instructions.
1614
1615 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1616
1617         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1618
1619 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1620
1621         Add support for associating SPARC ASIs with an architecture level.
1622         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1623         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1624         decoding of SPARC ASIs.
1625
1626 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1627
1628         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1629         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1630
1631 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1632
1633         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1634         1 (instead of to itself). Correct typo.
1635
1636 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1637
1638         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1639         pseudoinstructions.
1640
1641 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1642
1643         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1644         (aarch64_sys_reg_supported_p): Handle them.
1645
1646 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1647
1648         * arc-opc.c (UIMM6_20R): Define.
1649         (SIMM12_20): Use above.
1650         (SIMM12_20R): Define.
1651         (SIMM3_5_S): Use above.
1652         (UIMM7_A32_11R_S): Define.
1653         (UIMM7_9_S): Use above.
1654         (UIMM3_13R_S): Define.
1655         (SIMM11_A32_7_S): Use above.
1656         (SIMM9_8R): Define.
1657         (UIMM10_A32_8_S): Use above.
1658         (UIMM8_8R_S): Define.
1659         (W6): Use above.
1660         (arc_relax_opcodes): Use all above defines.
1661
1662 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1663
1664         * arc-regs.h: Distinguish some of the registers different on
1665         ARC700 and HS38 cpus.
1666
1667 2017-02-14  Alan Modra  <amodra@gmail.com>
1668
1669         PR 21118
1670         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1671         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1672
1673 2017-02-11  Stafford Horne  <shorne@gmail.com>
1674             Alan Modra  <amodra@gmail.com>
1675
1676         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1677         Use insn_bytes_value and insn_int_value directly instead.  Don't
1678         free allocated memory until function exit.
1679
1680 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1681
1682         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1683
1684 2017-02-03  Nick Clifton  <nickc@redhat.com>
1685
1686         PR 21096
1687         * aarch64-opc.c (print_register_list): Ensure that the register
1688         list index will fir into the tb buffer.
1689         (print_register_offset_address): Likewise.
1690         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1691
1692 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1693
1694         PR 21056
1695         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1696         instructions when the previous fetch packet ends with a 32-bit
1697         instruction.
1698
1699 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1700
1701         * pru-opc.c: Remove vague reference to a future GDB port.
1702
1703 2017-01-20  Nick Clifton  <nickc@redhat.com>
1704
1705         * po/ga.po: Updated Irish translation.
1706
1707 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1708
1709         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1710
1711 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1712
1713         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1714         if FETCH_DATA returns 0.
1715         (m68k_scan_mask): Likewise.
1716         (print_insn_m68k): Update code to handle -1 return value.
1717
1718 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1719
1720         * m68k-dis.c (enum print_insn_arg_error): New.
1721         (NEXTBYTE): Replace -3 with
1722         PRINT_INSN_ARG_MEMORY_ERROR.
1723         (NEXTULONG): Likewise.
1724         (NEXTSINGLE): Likewise.
1725         (NEXTDOUBLE): Likewise.
1726         (NEXTDOUBLE): Likewise.
1727         (NEXTPACKED): Likewise.
1728         (FETCH_ARG): Likewise.
1729         (FETCH_DATA): Update comments.
1730         (print_insn_arg): Update comments. Replace magic numbers with
1731         enum.
1732         (match_insn_m68k): Likewise.
1733
1734 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1735
1736         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1737         * i386-dis-evex.h (evex_table): Updated.
1738         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1739         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1740         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1741         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1742         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1743         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1744         * i386-init.h: Regenerate.
1745         * i386-tbl.h: Ditto.
1746
1747 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1748
1749         * msp430-dis.c (msp430_singleoperand): Return -1 if
1750         msp430dis_opcode_signed returns false.
1751         (msp430_doubleoperand): Likewise.
1752         (msp430_branchinstr): Return -1 if
1753         msp430dis_opcode_unsigned returns false.
1754         (msp430x_calla_instr): Likewise.
1755         (print_insn_msp430): Likewise.
1756
1757 2017-01-05  Nick Clifton  <nickc@redhat.com>
1758
1759         PR 20946
1760         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1761         could not be matched.
1762         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1763         NULL.
1764
1765 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1766
1767         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1768         (aarch64_opcode_table): Use RCPC_INSN.
1769
1770 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1771
1772         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1773         extension.
1774         * riscv-opcodes/all-opcodes: Likewise.
1775
1776 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1777
1778         * riscv-dis.c (print_insn_args): Add fall through comment.
1779
1780 2017-01-03  Nick Clifton  <nickc@redhat.com>
1781
1782         * po/sr.po: New Serbian translation.
1783         * configure.ac (ALL_LINGUAS): Add sr.
1784         * configure: Regenerate.
1785
1786 2017-01-02  Alan Modra  <amodra@gmail.com>
1787
1788         * epiphany-desc.h: Regenerate.
1789         * epiphany-opc.h: Regenerate.
1790         * fr30-desc.h: Regenerate.
1791         * fr30-opc.h: Regenerate.
1792         * frv-desc.h: Regenerate.
1793         * frv-opc.h: Regenerate.
1794         * ip2k-desc.h: Regenerate.
1795         * ip2k-opc.h: Regenerate.
1796         * iq2000-desc.h: Regenerate.
1797         * iq2000-opc.h: Regenerate.
1798         * lm32-desc.h: Regenerate.
1799         * lm32-opc.h: Regenerate.
1800         * m32c-desc.h: Regenerate.
1801         * m32c-opc.h: Regenerate.
1802         * m32r-desc.h: Regenerate.
1803         * m32r-opc.h: Regenerate.
1804         * mep-desc.h: Regenerate.
1805         * mep-opc.h: Regenerate.
1806         * mt-desc.h: Regenerate.
1807         * mt-opc.h: Regenerate.
1808         * or1k-desc.h: Regenerate.
1809         * or1k-opc.h: Regenerate.
1810         * xc16x-desc.h: Regenerate.
1811         * xc16x-opc.h: Regenerate.
1812         * xstormy16-desc.h: Regenerate.
1813         * xstormy16-opc.h: Regenerate.
1814
1815 2017-01-02  Alan Modra  <amodra@gmail.com>
1816
1817         Update year range in copyright notice of all files.
1818
1819 For older changes see ChangeLog-2016
1820 \f
1821 Copyright (C) 2017 Free Software Foundation, Inc.
1822
1823 Copying and distribution of this file, with or without modification,
1824 are permitted in any medium without royalty provided the copyright
1825 notice and this notice are preserved.
1826
1827 Local Variables:
1828 mode: change-log
1829 left-margin: 8
1830 fill-column: 74
1831 version-control: never
1832 End: