opcodes/ChangeLog

   1 2019-12-04  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
   4         forms.
   5         (xbegin): Drop DefaultSize.
   6         * i386-tbl.h: Re-generate.
   7
   8 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
   9
  10         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
  11         Change the coproc CRC conditions to use the extension
  12         feature set, second word, base on ARM_EXT2_CRC.
  13
  14 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  15
  16         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
  17         * i386-tbl.h: Re-generate.
  18
  19 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  20
  21         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
  22         JumpInterSegment, and JumpAbsolute entries.
  23         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
  24         JUMP_ABSOLUTE): Define.
  25         (struct i386_opcode_modifier): Extend jump field to 3 bits.
  26         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
  27         fields.
  28         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
  29         JumpInterSegment): Define.
  30         * i386-tbl.h: Re-generate.
  31
  32 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-gen.c (operand_type_init): Remove
  35         OPERAND_TYPE_JUMPABSOLUTE entry.
  36         (opcode_modifiers): Add JumpAbsolute entry.
  37         (operand_types): Remove JumpAbsolute entry.
  38         * i386-opc.h (JumpAbsolute): Move between enums.
  39         (struct i386_opcode_modifier): Add jumpabsolute field.
  40         (union i386_operand_type): Remove jumpabsolute field.
  41         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
  42         * i386-init.h, i386-tbl.h: Re-generate.
  43
  44 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  45
  46         * i386-gen.c (opcode_modifiers): Add AnySize entry.
  47         (operand_types): Remove AnySize entry.
  48         * i386-opc.h (AnySize): Move between enums.
  49         (struct i386_opcode_modifier): Add anysize field.
  50         (OTUnused): Un-comment.
  51         (union i386_operand_type): Remove anysize field.
  52         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
  53         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
  54         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
  55         AnySize.
  56         * i386-tbl.h: Re-generate.
  57
  58 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
  59
  60         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
  61         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
  62         use the floating point register (FPR).
  63
  64 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
  65
  66         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
  67         cmode 1101.
  68         (is_mve_encoding_conflict): Update cmode conflict checks for
  69         MVE_VMVN_IMM.
  70
  71 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
  74         entry.
  75         (operand_types): Remove EsSeg entry.
  76         (main): Replace stale use of OTMax.
  77         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
  78         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
  79         (EsSeg): Delete.
  80         (OTUnused): Comment out.
  81         (union i386_operand_type): Remove esseg field.
  82         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
  83         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
  84         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
  85         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
  86         * i386-init.h, i386-tbl.h: Re-generate.
  87
  88 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  89
  90         * i386-gen.c (operand_instances): Add RegB entry.
  91         * i386-opc.h (enum operand_instance): Add RegB.
  92         * i386-opc.tbl (RegC, RegD, RegB): Define.
  93         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
  94         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
  95         monitorx, mwaitx): Drop ImmExt and convert encodings
  96         accordingly.
  97         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
  98         (edx, rdx): Add Instance=RegD.
  99         (ebx, rbx): Add Instance=RegB.
 100         * i386-tbl.h: Re-generate.
 101
 102 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-gen.c (operand_type_init): Adjust
 105         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 106         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 107         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 108         (operand_instances): New.
 109         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 110         (output_operand_type): New parameter "instance". Process it.
 111         (process_i386_operand_type): New local variable "instance".
 112         (main): Adjust static assertions.
 113         * i386-opc.h (INSTANCE_WIDTH): Define.
 114         (enum operand_instance): New.
 115         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 116         (union i386_operand_type): Replace acc, inoutportreg, and
 117         shiftcount by instance.
 118         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 119         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 120         Add Instance=.
 121         * i386-init.h, i386-tbl.h: Re-generate.
 122
 123 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 124
 125         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 126         smaxp/sminp entries' "tied_operand" field to 2.
 127
 128 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 129
 130         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 131         "index" local variable by that of the already existing "num".
 132
 133 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 134
 135         PR gas/25167
 136         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 137         * i386-tbl.h: Regenerated.
 138
 139 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 140
 141         * i386-gen.c (operand_type_init): Add Class= to
 142         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 143         OPERAND_TYPE_REGBND entry.
 144         (operand_classes): Add RegMask and RegBND entries.
 145         (operand_types): Drop RegMask and RegBND entry.
 146         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 147         (RegMask, RegBND): Delete.
 148         (union i386_operand_type): Remove regmask and regbnd fields.
 149         * i386-opc.tbl (RegMask, RegBND): Define.
 150         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 151         Class=RegBND.
 152         * i386-init.h, i386-tbl.h: Re-generate.
 153
 154 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-gen.c (operand_type_init): Add Class= to
 157         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 158         OPERAND_TYPE_REGZMM entries.
 159         (operand_classes): Add RegMMX and RegSIMD entries.
 160         (operand_types): Drop RegMMX and RegSIMD entries.
 161         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 162         (RegMMX, RegSIMD): Delete.
 163         (union i386_operand_type): Remove regmmx and regsimd fields.
 164         * i386-opc.tbl (RegMMX): Define.
 165         (RegXMM, RegYMM, RegZMM): Add Class=.
 166         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 167         Class=RegSIMD.
 168         * i386-init.h, i386-tbl.h: Re-generate.
 169
 170 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 171
 172         * i386-gen.c (operand_type_init): Add Class= to
 173         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 174         entries.
 175         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 176         (operand_types): Drop Control, Debug, and Test entries.
 177         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 178         (Control, Debug, Test): Delete.
 179         (union i386_operand_type): Remove control, debug, and test
 180         fields.
 181         * i386-opc.tbl (Control, Debug, Test): Define.
 182         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 183         Class=RegDR, and Test by Class=RegTR.
 184         * i386-init.h, i386-tbl.h: Re-generate.
 185
 186 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-gen.c (operand_type_init): Add Class= to
 189         OPERAND_TYPE_SREG entry.
 190         (operand_classes): Add SReg entry.
 191         (operand_types): Drop SReg entry.
 192         * i386-opc.h (enum operand_class): Add SReg.
 193         (SReg): Delete.
 194         (union i386_operand_type): Remove sreg field.
 195         * i386-opc.tbl (SReg): Define.
 196         * i386-reg.tbl: Replace SReg by Class=SReg.
 197         * i386-init.h, i386-tbl.h: Re-generate.
 198
 199 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-gen.c (operand_type_init): Add Class=. New
 202         OPERAND_TYPE_ANYIMM entry.
 203         (operand_classes): New.
 204         (operand_types): Drop Reg entry.
 205         (output_operand_type): New parameter "class". Process it.
 206         (process_i386_operand_type): New local variable "class".
 207         (main): Adjust static assertions.
 208         * i386-opc.h (CLASS_WIDTH): Define.
 209         (enum operand_class): New.
 210         (Reg): Replace by Class. Adjust comment.
 211         (union i386_operand_type): Replace reg by class.
 212         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 213         Class=.
 214         * i386-reg.tbl: Replace Reg by Class=Reg.
 215         * i386-init.h: Re-generate.
 216
 217 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 218
 219         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 220         (aarch64_opcode_table): Add data gathering hint mnemonic.
 221         * opcodes/aarch64-dis-2.c: Account for new instruction.
 222
 223 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 224
 225         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 226
 227
 228 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 229
 230         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 231         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 232         aarch64_feature_f64mm): New feature sets.
 233         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 234         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 235         instructions.
 236         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 237         macros.
 238         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 239         (OP_SVE_QQQ): New qualifier.
 240         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 241         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 242         the movprfx constraint.
 243         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 244         (aarch64_opcode_table): Define new instructions smmla,
 245         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 246         uzip{1/2}, trn{1/2}.
 247         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 248         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 249         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 250         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 251         Account for new instructions.
 252         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 253         S4x32 operand.
 254         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 255
 256 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 257 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 258
 259         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 260         Armv8.6-A.
 261         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 262         (neon_opcodes): Add bfloat SIMD instructions.
 263         (print_insn_coprocessor): Add new control character %b to print
 264         condition code without checking cp_num.
 265         (print_insn_neon): Account for BFloat16 instructions that have no
 266         special top-byte handling.
 267
 268 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 269 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 270
 271         * arm-dis.c (print_insn_coprocessor,
 272         print_insn_generic_coprocessor): Create wrapper functions around
 273         the implementation of the print_insn_coprocessor control codes.
 274         (print_insn_coprocessor_1): Original print_insn_coprocessor
 275         function that now takes which array to look at as an argument.
 276         (print_insn_arm): Use both print_insn_coprocessor and
 277         print_insn_generic_coprocessor.
 278         (print_insn_thumb32): As above.
 279
 280 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 281 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 282
 283         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 284         in reglane special case.
 285         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 286         aarch64_find_next_opcode): Account for new instructions.
 287         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 288         in reglane special case.
 289         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 290         new AARCH64_OPND_QLF_S_2H qualifier.
 291         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 292         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 293         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 294         sets.
 295         (BFLOAT_SVE, BFLOAT): New feature set macros.
 296         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 297         instructions.
 298         (aarch64_opcode_table): Define new instructions bfdot,
 299         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 300         bfcvtn2, bfcvt.
 301
 302 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 303 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 304
 305         * aarch64-tbl.h (ARMV8_6): New macro.
 306
 307 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-dis.c (prefix_table): Add mcommit.
 310         (rm_table): Add rdpru.
 311         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 312         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 313         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 314         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 315         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 316         * i386-opc.tbl (mcommit, rdpru): New.
 317         * i386-init.h, i386-tbl.h: Re-generate.
 318
 319 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 322         "names32" instead.
 323         (OP_Monitor): Drop local variable "op1_names", re-purpose
 324         "names" for it instead, and replace former "names" uses by
 325         "names32" ones.
 326
 327 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 328
 329         PR/gas 25167
 330         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 331         operand-less forms.
 332         * opcodes/i386-tbl.h: Re-generate.
 333
 334 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-dis.c (OP_Mwaitx): Delete.
 337         (prefix_table): Use OP_Mwait for mwaitx entry.
 338         (OP_Mwait): Also handle mwaitx.
 339
 340 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 341
 342         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 343         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 344         (prefix_table): Add respective entries.
 345         (rm_table): Link to those entries.
 346
 347 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 350         (REG_0F1C_P_0_MOD_0): ... this.
 351         (REG_0F1E_MOD_3): Rename to ...
 352         (REG_0F1E_P_1_MOD_3): ... this.
 353         (RM_0F01_REG_5): Rename to ...
 354         (RM_0F01_REG_5_MOD_3): ... this.
 355         (RM_0F01_REG_7): Rename to ...
 356         (RM_0F01_REG_7_MOD_3): ... this.
 357         (RM_0F1E_MOD_3_REG_7): Rename to ...
 358         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 359         (RM_0FAE_REG_6): Rename to ...
 360         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 361         (RM_0FAE_REG_7): Rename to ...
 362         (RM_0FAE_REG_7_MOD_3): ... this.
 363         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 364         (PREFIX_0F01_REG_5_MOD_0): ... this.
 365         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 366         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 367         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 368         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 369         (PREFIX_0FAE_REG_0): Rename to ...
 370         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 371         (PREFIX_0FAE_REG_1): Rename to ...
 372         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 373         (PREFIX_0FAE_REG_2): Rename to ...
 374         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 375         (PREFIX_0FAE_REG_3): Rename to ...
 376         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 377         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 378         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 379         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 380         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 381         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 382         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 383         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 384         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 385         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 386         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 387         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 388         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 389         (PREFIX_0FAE_REG_7): Rename to ...
 390         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 391         (PREFIX_MOD_0_0FC3): Rename to ...
 392         (PREFIX_0FC3_MOD_0): ... this.
 393         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 394         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 395         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 396         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 397         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 398         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 399         (reg_table, prefix_table, mod_table, rm_table): Adjust
 400         accordingly.
 401
 402 2019-11-04  Nick Clifton  <nickc@redhat.com>
 403
 404         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 405         of a v850 system register.  Move the v850_sreg_names array into
 406         this function.
 407         (get_v850_reg_name): Likewise for ordinary register names.
 408         (get_v850_vreg_name): Likewise for vector register names.
 409         (get_v850_cc_name): Likewise for condition codes.
 410         * get_v850_float_cc_name): Likewise for floating point condition
 411         codes.
 412         (get_v850_cacheop_name): Likewise for cache-ops.
 413         (get_v850_prefop_name): Likewise for pref-ops.
 414         (disassemble): Use the new accessor functions.
 415
 416 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 417
 418         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 419         immediate for the writeback form of ldraa/ldrab if it is 0.
 420         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 421         * aarch64-opc-2.c: Regenerated.
 422
 423 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 424
 425         * i386-gen.c (operand_type_shorthands): Delete.
 426         (operand_type_init): Expand previous shorthands.
 427         (set_bitfield_from_shorthand): Rename back to ...
 428         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 429         of operand_type_init[].
 430         (set_bitfield): Adjust call to the above function.
 431         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 432         RegXMM, RegYMM, RegZMM): Define.
 433         * i386-reg.tbl: Expand prior shorthands.
 434
 435 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 436
 437         * i386-gen.c (output_i386_opcode): Change order of fields
 438         emitted to output.
 439         * i386-opc.h (struct insn_template): Move operands field.
 440         Convert extension_opcode field to unsigned short.
 441         * i386-tbl.h: Re-generate.
 442
 443 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 444
 445         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 446         of W.
 447         * i386-opc.h (W): Extend comment.
 448         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 449         general purpose variants not allowing for byte operands.
 450         * i386-tbl.h: Re-generate.
 451
 452 2019-10-29  Nick Clifton  <nickc@redhat.com>
 453
 454         * tic30-dis.c (print_branch): Correct size of operand array.
 455
 456 2019-10-29  Nick Clifton  <nickc@redhat.com>
 457
 458         * d30v-dis.c (print_insn): Check that operand index is valid
 459         before attempting to access the operands array.
 460
 461 2019-10-29  Nick Clifton  <nickc@redhat.com>
 462
 463         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 464         locating the bit to be tested.
 465
 466 2019-10-29  Nick Clifton  <nickc@redhat.com>
 467
 468         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 469         values.
 470         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 471         (print_insn_s12z):  Check for illegal size values.
 472
 473 2019-10-28  Nick Clifton  <nickc@redhat.com>
 474
 475         * csky-dis.c (csky_chars_to_number): Check for a negative
 476         count. Use an unsigned integer to construct the return value.
 477
 478 2019-10-28  Nick Clifton  <nickc@redhat.com>
 479
 480         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 481         operand buffer.  Set value to 15 not 13.
 482         (get_register_operand): Use OPERAND_BUFFER_LEN.
 483         (get_indirect_operand): Likewise.
 484         (print_two_operand): Likewise.
 485         (print_three_operand): Likewise.
 486         (print_oar_insn): Likewise.
 487
 488 2019-10-28  Nick Clifton  <nickc@redhat.com>
 489
 490         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 491         (bit_extract_simple): Likewise.
 492         (bit_copy): Likewise.
 493         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 494         index_offset array are not accessed.
 495
 496 2019-10-28  Nick Clifton  <nickc@redhat.com>
 497
 498         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 499         operand.
 500
 501 2019-10-25  Nick Clifton  <nickc@redhat.com>
 502
 503         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 504         access to opcodes.op array element.
 505
 506 2019-10-23  Nick Clifton  <nickc@redhat.com>
 507
 508         * rx-dis.c (get_register_name): Fix spelling typo in error
 509         message.
 510         (get_condition_name, get_flag_name, get_double_register_name)
 511         (get_double_register_high_name, get_double_register_low_name)
 512         (get_double_control_register_name, get_double_condition_name)
 513         (get_opsize_name, get_size_name): Likewise.
 514
 515 2019-10-22  Nick Clifton  <nickc@redhat.com>
 516
 517         * rx-dis.c (get_size_name): New function.  Provides safe
 518         access to name array.
 519         (get_opsize_name): Likewise.
 520         (print_insn_rx): Use the accessor functions.
 521
 522 2019-10-16  Nick Clifton  <nickc@redhat.com>
 523
 524         * rx-dis.c (get_register_name): New function.  Provides safe
 525         access to name array.
 526         (get_condition_name, get_flag_name, get_double_register_name)
 527         (get_double_register_high_name, get_double_register_low_name)
 528         (get_double_control_register_name, get_double_condition_name):
 529         Likewise.
 530         (print_insn_rx): Use the accessor functions.
 531
 532 2019-10-09  Nick Clifton  <nickc@redhat.com>
 533
 534         PR 25041
 535         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 536         instructions.
 537
 538 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 539
 540         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 541         (cmpsd): Likewise. Move EsSeg to other operand.
 542         * opcodes/i386-tbl.h: Re-generate.
 543
 544 2019-09-23  Alan Modra  <amodra@gmail.com>
 545
 546         * m68k-dis.c: Include cpu-m68k.h
 547
 548 2019-09-23  Alan Modra  <amodra@gmail.com>
 549
 550         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 551         "elf/mips.h" earlier.
 552
 553 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 554
 555         PR gas/25012
 556         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 557         with SReg operand.
 558         * i386-tbl.h: Re-generate.
 559
 560 2019-09-18  Alan Modra  <amodra@gmail.com>
 561
 562         * arc-ext.c: Update throughout for bfd section macro changes.
 563
 564 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 565
 566         * Makefile.in: Re-generate.
 567         * configure: Re-generate.
 568
 569 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 570
 571         * riscv-opc.c (riscv_opcodes): Change subset field
 572         to insn_class field for all instructions.
 573         (riscv_insn_types): Likewise.
 574
 575 2019-09-16  Phil Blundell  <pb@pbcl.net>
 576
 577         * configure: Regenerated.
 578
 579 2019-09-10  Miod Vallat  <miod@online.fr>
 580
 581         PR 24982
 582         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 583
 584 2019-09-09  Phil Blundell  <pb@pbcl.net>
 585
 586         binutils 2.33 branch created.
 587
 588 2019-09-03  Nick Clifton  <nickc@redhat.com>
 589
 590         PR 24961
 591         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 592         greater than zero before indexing via (bufcnt -1).
 593
 594 2019-09-03  Nick Clifton  <nickc@redhat.com>
 595
 596         PR 24958
 597         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 598         (MAX_SPEC_REG_NAME_LEN): Define.
 599         (struct mmix_dis_info): Use defined constants for array lengths.
 600         (get_reg_name): New function.
 601         (get_sprec_reg_name): New function.
 602         (print_insn_mmix): Use new functions.
 603
 604 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 605
 606         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 607         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 608         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 609
 610 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 611
 612         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 613         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 614         (aarch64_sys_reg_supported_p): Update checks for the above.
 615
 616 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 617
 618         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 619         cases MVE_SQRSHRL and MVE_UQRSHLL.
 620         (print_insn_mve): Add case for specifier 'k' to check
 621         specific bit of the instruction.
 622
 623 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 624
 625         PR 24854
 626         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 627         encountering an unknown machine type.
 628         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 629         cases return -1 rather than calling abort.
 630
 631 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 632
 633         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 634         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 635         IgnoreSize.
 636         * i386-tbl.h: Re-generate.
 637
 638 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 639
 640         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 641         instructions.
 642
 643 2019-07-30  Mel Chen <mel.chen@sifive.com>
 644
 645         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 646         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 647
 648         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 649         fscsr.
 650
 651 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 652
 653         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 654         and MPY class instructions.
 655         (parse_option): Add nps400 option.
 656         (print_arc_disassembler_options): Add nps400 info.
 657
 658 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 659
 660         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 661         (bspop): Likewise.
 662         (modapp): Likewise.
 663         * arc-opc.c (RAD_CHK): Add.
 664         * arc-tbl.h: Regenerate.
 665
 666 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 667
 668         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 669         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 670
 671 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 672
 673         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 674         instructions as UNPREDICTABLE.
 675
 676 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 677
 678         * bpf-desc.c: Regenerated.
 679
 680 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-gen.c (static_assert): Define.
 683         (main): Use it.
 684         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 685         (Opcode_Modifier_Num): ... this.
 686         (Mem): Delete.
 687
 688 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 689
 690         * i386-gen.c (operand_types): Move RegMem ...
 691         (opcode_modifiers): ... here.
 692         * i386-opc.h (RegMem): Move to opcode modifer enum.
 693         (union i386_operand_type): Move regmem field ...
 694         (struct i386_opcode_modifier): ... here.
 695         * i386-opc.tbl (RegMem): Define.
 696         (mov, movq): Move RegMem on segment, control, debug, and test
 697         register flavors.
 698         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 699         to non-SSE2AVX flavor.
 700         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 701         Move RegMem on register only flavors. Drop IgnoreSize from
 702         legacy encoding flavors.
 703         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 704         flavors.
 705         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 706         register only flavors.
 707         (vmovd): Move RegMem and drop IgnoreSize on register only
 708         flavor. Change opcode and operand order to store form.
 709         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 710
 711 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 712
 713         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 714         entries.
 715         * i386-opc.h (SReg2, SReg3): Replace by ...
 716         (SReg): ... this.
 717         (union i386_operand_type): Replace sreg fields.
 718         * i386-opc.tbl (mov, ): Use SReg.
 719         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 720         register flavors.
 721         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 722         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 723
 724 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 725
 726         * bpf-desc.c: Regenerate.
 727         * bpf-opc.c: Likewise.
 728         * bpf-opc.h: Likewise.
 729
 730 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 731
 732         * bpf-desc.c: Regenerate.
 733         * bpf-opc.c: Likewise.
 734
 735 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 736
 737         * arm-dis.c (print_insn_coprocessor): Rename index to
 738         index_operand.
 739
 740 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 741
 742         * riscv-opc.c (riscv_insn_types): Add r4 type.
 743
 744         * riscv-opc.c (riscv_insn_types): Add b and j type.
 745
 746         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 747         format for sb type and correct s type.
 748
 749 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 750
 751         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 752         SVE FMOV alias of FCPY.
 753
 754 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 755
 756         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 757         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 758
 759 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 760
 761         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 762         registers in an instruction prefixed by MOVPRFX.
 763
 764 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 765
 766         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 767         sve_size_13 icode to account for variant behaviour of
 768         pmull{t,b}.
 769         * aarch64-dis-2.c: Regenerate.
 770         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 771         sve_size_13 icode to account for variant behaviour of
 772         pmull{t,b}.
 773         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 774         (OP_SVE_VVV_Q_D): Add new qualifier.
 775         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 776         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 777         AES and those not.
 778
 779 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 780
 781         * opcodes/i386-gen.c (operand_type_init): Remove
 782         OPERAND_TYPE_VEC_IMM4 entry.
 783         (operand_types): Remove Vec_Imm4.
 784         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 785         (union i386_operand_type): Remove vec_imm4.
 786         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 787         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 788
 789 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 790
 791         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 792         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 793         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 794         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 795         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 796         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 797         * i386-tbl.h: Re-generate.
 798
 799 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 802         register operands.
 803         * i386-tbl.h: Re-generate.
 804
 805 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-opc.tbl (C): New.
 808         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 809         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 810         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 811         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 812         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 813         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 814         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 815         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 816         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 817         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 818         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 819         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 820         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 821         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 822         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 823         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 824         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 825         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 826         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 827         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 828         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 829         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 830         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 831         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 832         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 833         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 834         flavors.
 835         * i386-tbl.h: Re-generate.
 836
 837 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 838
 839         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 840         register operands.
 841         * i386-tbl.h: Re-generate.
 842
 843 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 844
 845         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 846         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 847         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 848         * i386-tbl.h: Re-generate.
 849
 850 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 853         Disp8MemShift from register only templates.
 854         * i386-tbl.h: Re-generate.
 855
 856 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 857
 858         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 859         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 860         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 861         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 862         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 863         EVEX_W_0F11_P_3_M_1): Delete.
 864         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 865         EVEX_W_0F11_P_3): New.
 866         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 867         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 868         MOD_EVEX_0F11_PREFIX_3 table entries.
 869         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 870         PREFIX_EVEX_0F11 table entries.
 871         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 872         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 873         EVEX_W_0F11_P_3_M_{0,1} table entries.
 874
 875 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 876
 877         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 878         Delete.
 879
 880 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 881
 882         PR binutils/24719
 883         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 884         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 885         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 886         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 887         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 888         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 889         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 890         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 891         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 892         PREFIX_EVEX_0F38C6_REG_6 entries.
 893         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 894         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 895         EVEX_W_0F38C7_R_6_P_2 entries.
 896         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 897         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 898         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 899         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 900         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 901         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 902         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 903
 904 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 905
 906         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 907         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 908         VEX_LEN_0F2D_P_3): Delete.
 909         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 910         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 911         (prefix_table): ... here.
 912
 913 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 914
 915         * i386-dis.c (Iq): Delete.
 916         (Id): New.
 917         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 918         TBM insns.
 919         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 920         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 921         (OP_E_memory): Also honor needindex when deciding whether an
 922         address size prefix needs printing.
 923         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 924
 925 2019-06-26  Jim Wilson  <jimw@sifive.com>
 926
 927         PR binutils/24739
 928         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 929         Set info->display_endian to info->endian_code.
 930
 931 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 932
 933         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 934         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 935         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 936         OPERAND_TYPE_ACC64 entries.
 937         * i386-init.h: Re-generate.
 938
 939 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 940
 941         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 942         Delete.
 943         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 944         of dqa_mode.
 945         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 946         entries here.
 947         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 948         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 949
 950 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 951
 952         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 953         variables.
 954
 955 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 956
 957         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 958         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 959         movnti.
 960         * i386-opc.tbl (movnti): Add IgnoreSize.
 961         * i386-tbl.h: Re-generate.
 962
 963 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 964
 965         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 966         * i386-tbl.h: Re-generate.
 967
 968 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 969
 970         * i386-dis-evex.h: Break into ...
 971         * i386-dis-evex-len.h: New file.
 972         * i386-dis-evex-mod.h: Likewise.
 973         * i386-dis-evex-prefix.h: Likewise.
 974         * i386-dis-evex-reg.h: Likewise.
 975         * i386-dis-evex-w.h: Likewise.
 976         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 977         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 978         i386-dis-evex-mod.h.
 979
 980 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 981
 982         PR binutils/24700
 983         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 984         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 985         EVEX_W_0F385B_P_2.
 986         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 987         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 988         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 989         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 990         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 991         EVEX_LEN_0F385B_P_2_W_1.
 992         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 993         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 994         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 995         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 996         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 997         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 998         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 999         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1000         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1001         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1002
1003 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1004
1005         PR binutils/24691
1006         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1007         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1008         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1009         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1010         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1011         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1012         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1013         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1014         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1015         EVEX_LEN_0F3A43_P_2_W_1.
1016         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1017         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1018         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1019         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1020         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1021         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1022         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1023         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1024         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1025         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1026         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1027         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1028
1029 2019-06-14  Nick Clifton  <nickc@redhat.com>
1030
1031         * po/fr.po; Updated French translation.
1032
1033 2019-06-13  Stafford Horne  <shorne@gmail.com>
1034
1035         * or1k-asm.c: Regenerated.
1036         * or1k-desc.c: Regenerated.
1037         * or1k-desc.h: Regenerated.
1038         * or1k-dis.c: Regenerated.
1039         * or1k-ibld.c: Regenerated.
1040         * or1k-opc.c: Regenerated.
1041         * or1k-opc.h: Regenerated.
1042         * or1k-opinst.c: Regenerated.
1043
1044 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1045
1046         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1047
1048 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1049
1050         PR binutils/24633
1051         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1052         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1053         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1054         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1055         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1056         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1057         EVEX_LEN_0F3A1B_P_2_W_1.
1058         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1059         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1060         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1061         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1062         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1063         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1064         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1065         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1066
1067 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1068
1069         PR binutils/24626
1070         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1071         EVEX.vvvv when disassembling VEX and EVEX instructions.
1072         (OP_VEX): Set vex.register_specifier to 0 after readding
1073         vex.register_specifier.
1074         (OP_Vex_2src_1): Likewise.
1075         (OP_Vex_2src_2): Likewise.
1076         (OP_LWP_E): Likewise.
1077         (OP_EX_Vex): Don't check vex.register_specifier.
1078         (OP_XMM_Vex): Likewise.
1079
1080 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1081             Lili Cui  <lili.cui@intel.com>
1082
1083         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1084         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1085         instructions.
1086         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1087         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1088         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1089         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1090         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1091         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1092         * i386-init.h: Regenerated.
1093         * i386-tbl.h: Likewise.
1094
1095 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1096             Lili Cui  <lili.cui@intel.com>
1097
1098         * doc/c-i386.texi: Document enqcmd.
1099         * testsuite/gas/i386/enqcmd-intel.d: New file.
1100         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1101         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1102         * testsuite/gas/i386/enqcmd.d: Likewise.
1103         * testsuite/gas/i386/enqcmd.s: Likewise.
1104         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1105         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1106         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1107         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1108         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1109         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1110         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1111         and x86-64-enqcmd.
1112
1113 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1114
1115         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1116
1117 2019-06-03  Alan Modra  <amodra@gmail.com>
1118
1119         * ppc-dis.c (prefix_opcd_indices): Correct size.
1120
1121 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1122
1123         PR gas/24625
1124         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1125         Disp8ShiftVL.
1126         * i386-tbl.h: Regenerated.
1127
1128 2019-05-24  Alan Modra  <amodra@gmail.com>
1129
1130         * po/POTFILES.in: Regenerate.
1131
1132 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1133             Alan Modra  <amodra@gmail.com>
1134
1135         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1136         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1137         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1138         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1139         XTOP>): Define and add entries.
1140         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1141         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1142         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1143         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1144
1145 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1146             Alan Modra  <amodra@gmail.com>
1147
1148         * ppc-dis.c (ppc_opts): Add "future" entry.
1149         (PREFIX_OPCD_SEGS): Define.
1150         (prefix_opcd_indices): New array.
1151         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1152         (lookup_prefix): New function.
1153         (print_insn_powerpc): Handle 64-bit prefix instructions.
1154         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1155         (PMRR, POWERXX): Define.
1156         (prefix_opcodes): New instruction table.
1157         (prefix_num_opcodes): New constant.
1158
1159 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1160
1161         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1162         * configure: Regenerated.
1163         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1164         and cpu/bpf.opc.
1165         (HFILES): Add bpf-desc.h and bpf-opc.h.
1166         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1167         bpf-ibld.c and bpf-opc.c.
1168         (BPF_DEPS): Define.
1169         * Makefile.in: Regenerated.
1170         * disassemble.c (ARCH_bpf): Define.
1171         (disassembler): Add case for bfd_arch_bpf.
1172         (disassemble_init_for_target): Likewise.
1173         (enum epbf_isa_attr): Define.
1174         * disassemble.h: extern print_insn_bpf.
1175         * bpf-asm.c: Generated.
1176         * bpf-opc.h: Likewise.
1177         * bpf-opc.c: Likewise.
1178         * bpf-ibld.c: Likewise.
1179         * bpf-dis.c: Likewise.
1180         * bpf-desc.h: Likewise.
1181         * bpf-desc.c: Likewise.
1182
1183 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1184
1185         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1186         and VMSR with the new operands.
1187
1188 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1189
1190         * arm-dis.c (enum mve_instructions): New enum
1191         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1192         and cneg.
1193         (mve_opcodes): New instructions as above.
1194         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1195         csneg and csel.
1196         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1197
1198 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1199
1200         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1201         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1202         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1203         uqshl, urshrl and urshr.
1204         (is_mve_okay_in_it): Add new instructions to TRUE list.
1205         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1206         (print_insn_mve): Updated to accept new %j,
1207         %<bitfield>m and %<bitfield>n patterns.
1208
1209 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1210
1211         * mips-opc.c (mips_builtin_opcodes): Change source register
1212         constraint for DAUI.
1213
1214 2019-05-20  Nick Clifton  <nickc@redhat.com>
1215
1216         * po/fr.po: Updated French translation.
1217
1218 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1219             Michael Collison <michael.collison@arm.com>
1220
1221         * arm-dis.c (thumb32_opcodes): Add new instructions.
1222         (enum mve_instructions): Likewise.
1223         (enum mve_undefined): Add new reasons.
1224         (is_mve_encoding_conflict): Handle new instructions.
1225         (is_mve_undefined): Likewise.
1226         (is_mve_unpredictable): Likewise.
1227         (print_mve_undefined): Likewise.
1228         (print_mve_size): Likewise.
1229
1230 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1231             Michael Collison <michael.collison@arm.com>
1232
1233         * arm-dis.c (thumb32_opcodes): Add new instructions.
1234         (enum mve_instructions): Likewise.
1235         (is_mve_encoding_conflict): Handle new instructions.
1236         (is_mve_undefined): Likewise.
1237         (is_mve_unpredictable): Likewise.
1238         (print_mve_size): Likewise.
1239
1240 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1241             Michael Collison <michael.collison@arm.com>
1242
1243         * arm-dis.c (thumb32_opcodes): Add new instructions.
1244         (enum mve_instructions): Likewise.
1245         (is_mve_encoding_conflict): Likewise.
1246         (is_mve_unpredictable): Likewise.
1247         (print_mve_size): Likewise.
1248
1249 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1250             Michael Collison <michael.collison@arm.com>
1251
1252         * arm-dis.c (thumb32_opcodes): Add new instructions.
1253         (enum mve_instructions): Likewise.
1254         (is_mve_encoding_conflict): Handle new instructions.
1255         (is_mve_undefined): Likewise.
1256         (is_mve_unpredictable): Likewise.
1257         (print_mve_size): Likewise.
1258
1259 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1260             Michael Collison <michael.collison@arm.com>
1261
1262         * arm-dis.c (thumb32_opcodes): Add new instructions.
1263         (enum mve_instructions): Likewise.
1264         (is_mve_encoding_conflict): Handle new instructions.
1265         (is_mve_undefined): Likewise.
1266         (is_mve_unpredictable): Likewise.
1267         (print_mve_size): Likewise.
1268         (print_insn_mve): Likewise.
1269
1270 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1271             Michael Collison <michael.collison@arm.com>
1272
1273         * arm-dis.c (thumb32_opcodes): Add new instructions.
1274         (print_insn_thumb32): Handle new instructions.
1275
1276 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1277             Michael Collison <michael.collison@arm.com>
1278
1279         * arm-dis.c (enum mve_instructions): Add new instructions.
1280         (enum mve_undefined): Add new reasons.
1281         (is_mve_encoding_conflict): Handle new instructions.
1282         (is_mve_undefined): Likewise.
1283         (is_mve_unpredictable): Likewise.
1284         (print_mve_undefined): Likewise.
1285         (print_mve_size): Likewise.
1286         (print_mve_shift_n): Likewise.
1287         (print_insn_mve): Likewise.
1288
1289 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1290             Michael Collison <michael.collison@arm.com>
1291
1292         * arm-dis.c (enum mve_instructions): Add new instructions.
1293         (is_mve_encoding_conflict): Handle new instructions.
1294         (is_mve_unpredictable): Likewise.
1295         (print_mve_rotate): Likewise.
1296         (print_mve_size): Likewise.
1297         (print_insn_mve): Likewise.
1298
1299 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1300             Michael Collison <michael.collison@arm.com>
1301
1302         * arm-dis.c (enum mve_instructions): Add new instructions.
1303         (is_mve_encoding_conflict): Handle new instructions.
1304         (is_mve_unpredictable): Likewise.
1305         (print_mve_size): Likewise.
1306         (print_insn_mve): Likewise.
1307
1308 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1309             Michael Collison <michael.collison@arm.com>
1310
1311         * arm-dis.c (enum mve_instructions): Add new instructions.
1312         (enum mve_undefined): Add new reasons.
1313         (is_mve_encoding_conflict): Handle new instructions.
1314         (is_mve_undefined): Likewise.
1315         (is_mve_unpredictable): Likewise.
1316         (print_mve_undefined): Likewise.
1317         (print_mve_size): Likewise.
1318         (print_insn_mve): Likewise.
1319
1320 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1321             Michael Collison <michael.collison@arm.com>
1322
1323         * arm-dis.c (enum mve_instructions): Add new instructions.
1324         (is_mve_encoding_conflict): Handle new instructions.
1325         (is_mve_undefined): Likewise.
1326         (is_mve_unpredictable): Likewise.
1327         (print_mve_size): Likewise.
1328         (print_insn_mve): Likewise.
1329
1330 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1331             Michael Collison <michael.collison@arm.com>
1332
1333         * arm-dis.c (enum mve_instructions): Add new instructions.
1334         (enum mve_unpredictable): Add new reasons.
1335         (enum mve_undefined): Likewise.
1336         (is_mve_okay_in_it): Handle new isntructions.
1337         (is_mve_encoding_conflict): Likewise.
1338         (is_mve_undefined): Likewise.
1339         (is_mve_unpredictable): Likewise.
1340         (print_mve_vmov_index): Likewise.
1341         (print_simd_imm8): Likewise.
1342         (print_mve_undefined): Likewise.
1343         (print_mve_unpredictable): Likewise.
1344         (print_mve_size): Likewise.
1345         (print_insn_mve): Likewise.
1346
1347 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1348             Michael Collison <michael.collison@arm.com>
1349
1350         * arm-dis.c (enum mve_instructions): Add new instructions.
1351         (enum mve_unpredictable): Add new reasons.
1352         (enum mve_undefined): Likewise.
1353         (is_mve_encoding_conflict): Handle new instructions.
1354         (is_mve_undefined): Likewise.
1355         (is_mve_unpredictable): Likewise.
1356         (print_mve_undefined): Likewise.
1357         (print_mve_unpredictable): Likewise.
1358         (print_mve_rounding_mode): Likewise.
1359         (print_mve_vcvt_size): Likewise.
1360         (print_mve_size): Likewise.
1361         (print_insn_mve): Likewise.
1362
1363 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1364             Michael Collison <michael.collison@arm.com>
1365
1366         * arm-dis.c (enum mve_instructions): Add new instructions.
1367         (enum mve_unpredictable): Add new reasons.
1368         (enum mve_undefined): Likewise.
1369         (is_mve_undefined): Handle new instructions.
1370         (is_mve_unpredictable): Likewise.
1371         (print_mve_undefined): Likewise.
1372         (print_mve_unpredictable): Likewise.
1373         (print_mve_size): Likewise.
1374         (print_insn_mve): Likewise.
1375
1376 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1377             Michael Collison <michael.collison@arm.com>
1378
1379         * arm-dis.c (enum mve_instructions): Add new instructions.
1380         (enum mve_undefined): Add new reasons.
1381         (insns): Add new instructions.
1382         (is_mve_encoding_conflict):
1383         (print_mve_vld_str_addr): New print function.
1384         (is_mve_undefined): Handle new instructions.
1385         (is_mve_unpredictable): Likewise.
1386         (print_mve_undefined): Likewise.
1387         (print_mve_size): Likewise.
1388         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1389         (print_insn_mve):  Handle new operands.
1390
1391 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1392             Michael Collison <michael.collison@arm.com>
1393
1394         * arm-dis.c (enum mve_instructions): Add new instructions.
1395         (enum mve_unpredictable): Add new reasons.
1396         (is_mve_encoding_conflict): Handle new instructions.
1397         (is_mve_unpredictable): Likewise.
1398         (mve_opcodes): Add new instructions.
1399         (print_mve_unpredictable): Handle new reasons.
1400         (print_mve_register_blocks): New print function.
1401         (print_mve_size): Handle new instructions.
1402         (print_insn_mve): Likewise.
1403
1404 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1405             Michael Collison <michael.collison@arm.com>
1406
1407         * arm-dis.c (enum mve_instructions): Add new instructions.
1408         (enum mve_unpredictable): Add new reasons.
1409         (enum mve_undefined): Likewise.
1410         (is_mve_encoding_conflict): Handle new instructions.
1411         (is_mve_undefined): Likewise.
1412         (is_mve_unpredictable): Likewise.
1413         (coprocessor_opcodes): Move NEON VDUP from here...
1414         (neon_opcodes): ... to here.
1415         (mve_opcodes): Add new instructions.
1416         (print_mve_undefined):  Handle new reasons.
1417         (print_mve_unpredictable): Likewise.
1418         (print_mve_size): Handle new instructions.
1419         (print_insn_neon): Handle vdup.
1420         (print_insn_mve): Handle new operands.
1421
1422 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1423             Michael Collison <michael.collison@arm.com>
1424
1425         * arm-dis.c (enum mve_instructions): Add new instructions.
1426         (enum mve_unpredictable): Add new values.
1427         (mve_opcodes): Add new instructions.
1428         (vec_condnames): New array with vector conditions.
1429         (mve_predicatenames): New array with predicate suffixes.
1430         (mve_vec_sizename): New array with vector sizes.
1431         (enum vpt_pred_state): New enum with vector predication states.
1432         (struct vpt_block): New struct type for vpt blocks.
1433         (vpt_block_state): Global struct to keep track of state.
1434         (mve_extract_pred_mask): New helper function.
1435         (num_instructions_vpt_block): Likewise.
1436         (mark_outside_vpt_block): Likewise.
1437         (mark_inside_vpt_block): Likewise.
1438         (invert_next_predicate_state): Likewise.
1439         (update_next_predicate_state): Likewise.
1440         (update_vpt_block_state): Likewise.
1441         (is_vpt_instruction): Likewise.
1442         (is_mve_encoding_conflict): Add entries for new instructions.
1443         (is_mve_unpredictable): Likewise.
1444         (print_mve_unpredictable): Handle new cases.
1445         (print_instruction_predicate): Likewise.
1446         (print_mve_size): New function.
1447         (print_vec_condition): New function.
1448         (print_insn_mve): Handle vpt blocks and new print operands.
1449
1450 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1451
1452         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1453         8, 14 and 15 for Armv8.1-M Mainline.
1454
1455 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1456             Michael Collison <michael.collison@arm.com>
1457
1458         * arm-dis.c (enum mve_instructions): New enum.
1459         (enum mve_unpredictable): Likewise.
1460         (enum mve_undefined): Likewise.
1461         (struct mopcode32): New struct.
1462         (is_mve_okay_in_it): New function.
1463         (is_mve_architecture): Likewise.
1464         (arm_decode_field): Likewise.
1465         (arm_decode_field_multiple): Likewise.
1466         (is_mve_encoding_conflict): Likewise.
1467         (is_mve_undefined): Likewise.
1468         (is_mve_unpredictable): Likewise.
1469         (print_mve_undefined): Likewise.
1470         (print_mve_unpredictable): Likewise.
1471         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1472         (print_insn_mve): New function.
1473         (print_insn_thumb32): Handle MVE architecture.
1474         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1475
1476 2019-05-10  Nick Clifton  <nickc@redhat.com>
1477
1478         PR 24538
1479         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1480         end of the table prematurely.
1481
1482 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1483
1484         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1485         macros for R6.
1486
1487 2019-05-11  Alan Modra  <amodra@gmail.com>
1488
1489         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1490         when -Mraw is in effect.
1491
1492 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1493
1494         * aarch64-dis-2.c: Regenerate.
1495         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1496         (OP_SVE_BBB): New variant set.
1497         (OP_SVE_DDDD): New variant set.
1498         (OP_SVE_HHH): New variant set.
1499         (OP_SVE_HHHU): New variant set.
1500         (OP_SVE_SSS): New variant set.
1501         (OP_SVE_SSSU): New variant set.
1502         (OP_SVE_SHH): New variant set.
1503         (OP_SVE_SBBU): New variant set.
1504         (OP_SVE_DSS): New variant set.
1505         (OP_SVE_DHHU): New variant set.
1506         (OP_SVE_VMV_HSD_BHS): New variant set.
1507         (OP_SVE_VVU_HSD_BHS): New variant set.
1508         (OP_SVE_VVVU_SD_BH): New variant set.
1509         (OP_SVE_VVVU_BHSD): New variant set.
1510         (OP_SVE_VVV_QHD_DBS): New variant set.
1511         (OP_SVE_VVV_HSD_BHS): New variant set.
1512         (OP_SVE_VVV_HSD_BHS2): New variant set.
1513         (OP_SVE_VVV_BHS_HSD): New variant set.
1514         (OP_SVE_VV_BHS_HSD): New variant set.
1515         (OP_SVE_VVV_SD): New variant set.
1516         (OP_SVE_VVU_BHS_HSD): New variant set.
1517         (OP_SVE_VZVV_SD): New variant set.
1518         (OP_SVE_VZVV_BH): New variant set.
1519         (OP_SVE_VZV_SD): New variant set.
1520         (aarch64_opcode_table): Add sve2 instructions.
1521
1522 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1523
1524         * aarch64-asm-2.c: Regenerated.
1525         * aarch64-dis-2.c: Regenerated.
1526         * aarch64-opc-2.c: Regenerated.
1527         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1528         for SVE_SHLIMM_UNPRED_22.
1529         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1530         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1531         operand.
1532
1533 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1534
1535         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1536         sve_size_tsz_bhs iclass encode.
1537         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1538         sve_size_tsz_bhs iclass decode.
1539
1540 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1541
1542         * aarch64-asm-2.c: Regenerated.
1543         * aarch64-dis-2.c: Regenerated.
1544         * aarch64-opc-2.c: Regenerated.
1545         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1546         for SVE_Zm4_11_INDEX.
1547         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1548         (fields): Handle SVE_i2h field.
1549         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1550         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1551
1552 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1553
1554         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1555         sve_shift_tsz_bhsd iclass encode.
1556         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1557         sve_shift_tsz_bhsd iclass decode.
1558
1559 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1560
1561         * aarch64-asm-2.c: Regenerated.
1562         * aarch64-dis-2.c: Regenerated.
1563         * aarch64-opc-2.c: Regenerated.
1564         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1565         (aarch64_encode_variant_using_iclass): Handle
1566         sve_shift_tsz_hsd iclass encode.
1567         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1568         sve_shift_tsz_hsd iclass decode.
1569         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1570         for SVE_SHRIMM_UNPRED_22.
1571         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1572         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1573         operand.
1574
1575 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1576
1577         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1578         sve_size_013 iclass encode.
1579         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1580         sve_size_013 iclass decode.
1581
1582 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1583
1584         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1585         sve_size_bh iclass encode.
1586         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1587         sve_size_bh iclass decode.
1588
1589 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1590
1591         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1592         sve_size_sd2 iclass encode.
1593         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1594         sve_size_sd2 iclass decode.
1595         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1596         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1597
1598 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1599
1600         * aarch64-asm-2.c: Regenerated.
1601         * aarch64-dis-2.c: Regenerated.
1602         * aarch64-opc-2.c: Regenerated.
1603         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1604         for SVE_ADDR_ZX.
1605         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1606         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1607
1608 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1609
1610         * aarch64-asm-2.c: Regenerated.
1611         * aarch64-dis-2.c: Regenerated.
1612         * aarch64-opc-2.c: Regenerated.
1613         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1614         for SVE_Zm3_11_INDEX.
1615         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1616         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1617         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1618         fields.
1619         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1620
1621 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1622
1623         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1624         sve_size_hsd2 iclass encode.
1625         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1626         sve_size_hsd2 iclass decode.
1627         * aarch64-opc.c (fields): Handle SVE_size field.
1628         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1629
1630 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1631
1632         * aarch64-asm-2.c: Regenerated.
1633         * aarch64-dis-2.c: Regenerated.
1634         * aarch64-opc-2.c: Regenerated.
1635         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1636         for SVE_IMM_ROT3.
1637         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1638         (fields): Handle SVE_rot3 field.
1639         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1640         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1641
1642 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1643
1644         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1645         instructions.
1646
1647 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1648
1649         * aarch64-tbl.h
1650         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1651         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1652         aarch64_feature_sve2bitperm): New feature sets.
1653         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1654         for feature set addresses.
1655         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1656         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1657
1658 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1659             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1660
1661         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1662         argument and set ASE_EVA_R6 appropriately.
1663         (set_default_mips_dis_options): Pass ISA to above.
1664         (parse_mips_dis_option): Likewise.
1665         * mips-opc.c (EVAR6): New macro.
1666         (mips_builtin_opcodes): Add llwpe, scwpe.
1667
1668 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1669
1670         * aarch64-asm-2.c: Regenerated.
1671         * aarch64-dis-2.c: Regenerated.
1672         * aarch64-opc-2.c: Regenerated.
1673         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1674         AARCH64_OPND_TME_UIMM16.
1675         (aarch64_print_operand): Likewise.
1676         * aarch64-tbl.h (QL_IMM_NIL): New.
1677         (TME): New.
1678         (_TME_INSN): New.
1679         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1680
1681 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1682
1683         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1684
1685 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1686             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1687
1688         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1689
1690 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1691
1692         * s12z-opc.h: Add extern "C" bracketing to help
1693         users who wish to use this interface in c++ code.
1694
1695 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1696
1697         * s12z-opc.c (bm_decode): Handle bit map operations with the
1698         "reserved0" mode.
1699
1700 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1701
1702         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1703         specifier.  Add entries for VLDR and VSTR of system registers.
1704         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1705         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1706         of %J and %K format specifier.
1707
1708 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1709
1710         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1711         Add new entries for VSCCLRM instruction.
1712         (print_insn_coprocessor): Handle new %C format control code.
1713
1714 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1715
1716         * arm-dis.c (enum isa): New enum.
1717         (struct sopcode32): New structure.
1718         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1719         set isa field of all current entries to ANY.
1720         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1721         Only match an entry if its isa field allows the current mode.
1722
1723 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1724
1725         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1726         CLRM.
1727         (print_insn_thumb32): Add logic to print %n CLRM register list.
1728
1729 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1730
1731         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1732         and %Q patterns.
1733
1734 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1735
1736         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1737         (print_insn_thumb32): Edit the switch case for %Z.
1738
1739 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1740
1741         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1742
1743 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1744
1745         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1746
1747 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1748
1749         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1750
1751 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1752
1753         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1754         Arm register with r13 and r15 unpredictable.
1755         (thumb32_opcodes): New instructions for bfx and bflx.
1756
1757 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1758
1759         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1760
1761 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1762
1763         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1764
1765 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1766
1767         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1768
1769 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1770
1771         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1772
1773 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1774
1775         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1776         "optr". ("operator" is a reserved word in c++).
1777
1778 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1779
1780         * aarch64-opc.c (aarch64_print_operand): Add case for
1781         AARCH64_OPND_Rt_SP.
1782         (verify_constraints): Likewise.
1783         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1784         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1785         to accept Rt|SP as first operand.
1786         (AARCH64_OPERANDS): Add new Rt_SP.
1787         * aarch64-asm-2.c: Regenerated.
1788         * aarch64-dis-2.c: Regenerated.
1789         * aarch64-opc-2.c: Regenerated.
1790
1791 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1792
1793         * aarch64-asm-2.c: Regenerated.
1794         * aarch64-dis-2.c: Likewise.
1795         * aarch64-opc-2.c: Likewise.
1796         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1797
1798 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1799
1800         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1801
1802 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1803
1804         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1805         * i386-init.h: Regenerated.
1806
1807 2019-04-07  Alan Modra  <amodra@gmail.com>
1808
1809         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1810         op_separator to control printing of spaces, comma and parens
1811         rather than need_comma, need_paren and spaces vars.
1812
1813 2019-04-07  Alan Modra  <amodra@gmail.com>
1814
1815         PR 24421
1816         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1817         (print_insn_neon, print_insn_arm): Likewise.
1818
1819 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1820
1821         * i386-dis-evex.h (evex_table): Updated to support BF16
1822         instructions.
1823         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1824         and EVEX_W_0F3872_P_3.
1825         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1826         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1827         * i386-opc.h (enum): Add CpuAVX512_BF16.
1828         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1829         * i386-opc.tbl: Add AVX512 BF16 instructions.
1830         * i386-init.h: Regenerated.
1831         * i386-tbl.h: Likewise.
1832
1833 2019-04-05  Alan Modra  <amodra@gmail.com>
1834
1835         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1836         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1837         to favour printing of "-" branch hint when using the "y" bit.
1838         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1839
1840 2019-04-05  Alan Modra  <amodra@gmail.com>
1841
1842         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1843         opcode until first operand is output.
1844
1845 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1846
1847         PR gas/24349
1848         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1849         (valid_bo_post_v2): Add support for 'at' branch hints.
1850         (insert_bo): Only error on branch on ctr.
1851         (get_bo_hint_mask): New function.
1852         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1853         for inserting 'at' branch hints.
1854         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1855         for extracting 'at' branch hints.
1856         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1857         (BOE): Delete operand.
1858         (BOM, BOP): New operands.
1859         (RM): Update value.
1860         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1861         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1862         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1863         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1864         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1865         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1866         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1867         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1868         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1869         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1870         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1871         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1872         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1873         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1874         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1875         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1876         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1877         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1878         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1879         bttarl+>: New extended mnemonics.
1880
1881 2019-03-28  Alan Modra  <amodra@gmail.com>
1882
1883         PR 24390
1884         * ppc-opc.c (BTF): Define.
1885         (powerpc_opcodes): Use for mtfsb*.
1886         * ppc-dis.c (print_insn_powerpc): Print fields with both
1887         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1888
1889 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1890
1891         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1892         (mapping_symbol_for_insn): Implement new algorithm.
1893         (print_insn): Remove duplicate code.
1894
1895 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1896
1897         * aarch64-dis.c (print_insn_aarch64):
1898         Implement override.
1899
1900 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1901
1902         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1903         order.
1904
1905 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1906
1907         * aarch64-dis.c (last_stop_offset): New.
1908         (print_insn_aarch64): Use stop_offset.
1909
1910 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1911
1912         PR gas/24359
1913         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1914         CPU_ANY_AVX2_FLAGS.
1915         * i386-init.h: Regenerated.
1916
1917 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1918
1919         PR gas/24348
1920         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1921         vmovdqu16, vmovdqu32 and vmovdqu64.
1922         * i386-tbl.h: Regenerated.
1923
1924 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1925
1926         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1927         from vstrszb, vstrszh, and vstrszf.
1928
1929 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1930
1931         * s390-opc.txt: Add instruction descriptions.
1932
1933 2019-02-08  Jim Wilson  <jimw@sifive.com>
1934
1935         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1936         <bne>: Likewise.
1937
1938 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1939
1940         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1941
1942 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1943
1944         PR binutils/23212
1945         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1946         * aarch64-opc.c (verify_elem_sd): New.
1947         (fields): Add FLD_sz entr.
1948         * aarch64-tbl.h (_SIMD_INSN): New.
1949         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1950         fmulx scalar and vector by element isns.
1951
1952 2019-02-07  Nick Clifton  <nickc@redhat.com>
1953
1954         * po/sv.po: Updated Swedish translation.
1955
1956 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1957
1958         * s390-mkopc.c (main): Accept arch13 as cpu string.
1959         * s390-opc.c: Add new instruction formats and instruction opcode
1960         masks.
1961         * s390-opc.txt: Add new arch13 instructions.
1962
1963 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1964
1965         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1966         (aarch64_opcode): Change encoding for stg, stzg
1967         st2g and st2zg.
1968         * aarch64-asm-2.c: Regenerated.
1969         * aarch64-dis-2.c: Regenerated.
1970         * aarch64-opc-2.c: Regenerated.
1971
1972 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1973
1974         * aarch64-asm-2.c: Regenerated.
1975         * aarch64-dis-2.c: Likewise.
1976         * aarch64-opc-2.c: Likewise.
1977         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1978
1979 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1980             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1981
1982         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1983         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1984         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1985         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1986         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1987         case for ldstgv_indexed.
1988         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1989         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1990         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1991         * aarch64-asm-2.c: Regenerated.
1992         * aarch64-dis-2.c: Regenerated.
1993         * aarch64-opc-2.c: Regenerated.
1994
1995 2019-01-23  Nick Clifton  <nickc@redhat.com>
1996
1997         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1998
1999 2019-01-21  Nick Clifton  <nickc@redhat.com>
2000
2001         * po/de.po: Updated German translation.
2002         * po/uk.po: Updated Ukranian translation.
2003
2004 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2005         * mips-dis.c (mips_arch_choices): Fix typo in
2006         gs464, gs464e and gs264e descriptors.
2007
2008 2019-01-19  Nick Clifton  <nickc@redhat.com>
2009
2010         * configure: Regenerate.
2011         * po/opcodes.pot: Regenerate.
2012
2013 2018-06-24  Nick Clifton  <nickc@redhat.com>
2014
2015         2.32 branch created.
2016
2017 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2018
2019         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2020         if it is null.
2021         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2022         zero.
2023
2024 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2025
2026         * configure: Regenerate.
2027
2028 2019-01-07  Alan Modra  <amodra@gmail.com>
2029
2030         * configure: Regenerate.
2031         * po/POTFILES.in: Regenerate.
2032
2033 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2034
2035         * s12z-opc.c: New file.
2036         * s12z-opc.h: New file.
2037         * s12z-dis.c: Removed all code not directly related to display
2038         of instructions.  Used the interface provided by the new files
2039         instead.
2040         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2041         * Makefile.in: Regenerate.
2042         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2043         * configure: Regenerate.
2044
2045 2019-01-01  Alan Modra  <amodra@gmail.com>
2046
2047         Update year range in copyright notice of all files.
2048
2049 For older changes see ChangeLog-2018
2050 \f
2051 Copyright (C) 2019 Free Software Foundation, Inc.
2052
2053 Copying and distribution of this file, with or without modification,
2054 are permitted in any medium without royalty provided the copyright
2055 notice and this notice are preserved.
2056
2057 Local Variables:
2058 mode: change-log
2059 left-margin: 8
2060 fill-column: 74
2061 version-control: never
2062 End: