1 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
3 * arm-dis.c (print_insn_cde): Define 'V' parse character.
4 (cde_opcodes): Add VCX* instructions.
6 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
7 Matthew Malcomson <matthew.malcomson@arm.com>
9 * arm-dis.c (struct cdeopcode32): New.
10 (CDE_OPCODE): New macro.
11 (cde_opcodes): New disassembly table.
12 (regnames): New option to table.
13 (cde_coprocs): New global variable.
15 (print_insn_thumb32): Use print_insn_cde.
16 (parse_arm_disassembler_options): Parse coprocN args.
18 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
21 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
23 * i386-opc.h (AMD64): Removed.
27 (INTEL64ONLY): Likewise.
28 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
29 * i386-opc.tbl (Amd64): New.
31 (Intel64Only): Likewise.
32 Replace AMD64 with Amd64. Update sysenter/sysenter with
33 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
34 * i386-tbl.h: Regenerated.
36 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
39 * z80-dis.c: Add support for GBZ80 opcodes.
41 2020-02-04 Alan Modra <amodra@gmail.com>
43 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
45 2020-02-03 Alan Modra <amodra@gmail.com>
47 * m32c-ibld.c: Regenerate.
49 2020-02-01 Alan Modra <amodra@gmail.com>
51 * frv-ibld.c: Regenerate.
53 2020-01-31 Jan Beulich <jbeulich@suse.com>
55 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
56 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
57 (OP_E_memory): Replace xmm_mdq_mode case label by
58 vex_scalar_w_dq_mode one.
59 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
61 2020-01-31 Jan Beulich <jbeulich@suse.com>
63 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
64 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
65 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
66 (intel_operand_size): Drop vex_w_dq_mode case label.
68 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
70 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
71 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
73 2020-01-30 Alan Modra <amodra@gmail.com>
75 * m32c-ibld.c: Regenerate.
77 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
79 * bpf-opc.c: Regenerate.
81 2020-01-30 Jan Beulich <jbeulich@suse.com>
83 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
84 (dis386): Use them to replace C2/C3 table entries.
85 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
86 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
87 ones. Use Size64 instead of DefaultSize on Intel64 ones.
88 * i386-tbl.h: Re-generate.
90 2020-01-30 Jan Beulich <jbeulich@suse.com>
92 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
94 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
96 * i386-tbl.h: Re-generate.
98 2020-01-30 Alan Modra <amodra@gmail.com>
100 * tic4x-dis.c (tic4x_dp): Make unsigned.
102 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
103 Jan Beulich <jbeulich@suse.com>
106 * i386-dis.c (MOVSXD_Fixup): New function.
107 (movsxd_mode): New enum.
108 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
109 (intel_operand_size): Handle movsxd_mode.
110 (OP_E_register): Likewise.
112 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
113 register on movsxd. Add movsxd with 16-bit destination register
114 for AMD64 and Intel64 ISAs.
115 * i386-tbl.h: Regenerated.
117 2020-01-27 Tamar Christina <tamar.christina@arm.com>
120 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
121 * aarch64-asm-2.c: Regenerate
122 * aarch64-dis-2.c: Likewise.
123 * aarch64-opc-2.c: Likewise.
125 2020-01-21 Jan Beulich <jbeulich@suse.com>
127 * i386-opc.tbl (sysret): Drop DefaultSize.
128 * i386-tbl.h: Re-generate.
130 2020-01-21 Jan Beulich <jbeulich@suse.com>
132 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
134 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
135 * i386-tbl.h: Re-generate.
137 2020-01-20 Nick Clifton <nickc@redhat.com>
139 * po/de.po: Updated German translation.
140 * po/pt_BR.po: Updated Brazilian Portuguese translation.
141 * po/uk.po: Updated Ukranian translation.
143 2020-01-20 Alan Modra <amodra@gmail.com>
145 * hppa-dis.c (fput_const): Remove useless cast.
147 2020-01-20 Alan Modra <amodra@gmail.com>
149 * arm-dis.c (print_insn_arm): Wrap 'T' value.
151 2020-01-18 Nick Clifton <nickc@redhat.com>
153 * configure: Regenerate.
154 * po/opcodes.pot: Regenerate.
156 2020-01-18 Nick Clifton <nickc@redhat.com>
158 Binutils 2.34 branch created.
160 2020-01-17 Christian Biesinger <cbiesinger@google.com>
162 * opintl.h: Fix spelling error (seperate).
164 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
166 * i386-opc.tbl: Add {vex} pseudo prefix.
167 * i386-tbl.h: Regenerated.
169 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
172 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
173 (neon_opcodes): Likewise.
174 (select_arm_features): Make sure we enable MVE bits when selecting
175 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
178 2020-01-16 Jan Beulich <jbeulich@suse.com>
180 * i386-opc.tbl: Drop stale comment from XOP section.
182 2020-01-16 Jan Beulich <jbeulich@suse.com>
184 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
185 (extractps): Add VexWIG to SSE2AVX forms.
186 * i386-tbl.h: Re-generate.
188 2020-01-16 Jan Beulich <jbeulich@suse.com>
190 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
191 Size64 from and use VexW1 on SSE2AVX forms.
192 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
193 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
194 * i386-tbl.h: Re-generate.
196 2020-01-15 Alan Modra <amodra@gmail.com>
198 * tic4x-dis.c (tic4x_version): Make unsigned long.
199 (optab, optab_special, registernames): New file scope vars.
200 (tic4x_print_register): Set up registernames rather than
201 malloc'd registertable.
202 (tic4x_disassemble): Delete optable and optable_special. Use
203 optab and optab_special instead. Throw away old optab,
204 optab_special and registernames when info->mach changes.
206 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
209 * z80-dis.c (suffix): Use .db instruction to generate double
212 2020-01-14 Alan Modra <amodra@gmail.com>
214 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
215 values to unsigned before shifting.
217 2020-01-13 Thomas Troeger <tstroege@gmx.de>
219 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
221 (print_insn_thumb16, print_insn_thumb32): Likewise.
222 (print_insn): Initialize the insn info.
223 * i386-dis.c (print_insn): Initialize the insn info fields, and
226 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
228 * arc-opc.c (C_NE): Make it required.
230 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
232 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
233 reserved register name.
235 2020-01-13 Alan Modra <amodra@gmail.com>
237 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
238 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
240 2020-01-13 Alan Modra <amodra@gmail.com>
242 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
243 result of wasm_read_leb128 in a uint64_t and check that bits
244 are not lost when copying to other locals. Use uint32_t for
245 most locals. Use PRId64 when printing int64_t.
247 2020-01-13 Alan Modra <amodra@gmail.com>
249 * score-dis.c: Formatting.
250 * score7-dis.c: Formatting.
252 2020-01-13 Alan Modra <amodra@gmail.com>
254 * score-dis.c (print_insn_score48): Use unsigned variables for
255 unsigned values. Don't left shift negative values.
256 (print_insn_score32): Likewise.
257 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
259 2020-01-13 Alan Modra <amodra@gmail.com>
261 * tic4x-dis.c (tic4x_print_register): Remove dead code.
263 2020-01-13 Alan Modra <amodra@gmail.com>
265 * fr30-ibld.c: Regenerate.
267 2020-01-13 Alan Modra <amodra@gmail.com>
269 * xgate-dis.c (print_insn): Don't left shift signed value.
270 (ripBits): Formatting, use 1u.
272 2020-01-10 Alan Modra <amodra@gmail.com>
274 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
275 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
277 2020-01-10 Alan Modra <amodra@gmail.com>
279 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
280 and XRREG value earlier to avoid a shift with negative exponent.
281 * m10200-dis.c (disassemble): Similarly.
283 2020-01-09 Nick Clifton <nickc@redhat.com>
286 * z80-dis.c (ld_ii_ii): Use correct cast.
288 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
291 * z80-dis.c (ld_ii_ii): Use character constant when checking
294 2020-01-09 Jan Beulich <jbeulich@suse.com>
296 * i386-dis.c (SEP_Fixup): New.
298 (dis386_twobyte): Use it for sysenter/sysexit.
299 (enum x86_64_isa): Change amd64 enumerator to value 1.
300 (OP_J): Compare isa64 against intel64 instead of amd64.
301 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
303 * i386-tbl.h: Re-generate.
305 2020-01-08 Alan Modra <amodra@gmail.com>
307 * z8k-dis.c: Include libiberty.h
308 (instr_data_s): Make max_fetched unsigned.
309 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
310 Don't exceed byte_info bounds.
311 (output_instr): Make num_bytes unsigned.
312 (unpack_instr): Likewise for nibl_count and loop.
313 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
315 * z8k-opc.h: Regenerate.
317 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
319 * arc-tbl.h (llock): Use 'LLOCK' as class.
321 (scond): Use 'SCOND' as class.
323 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
326 2020-01-06 Alan Modra <amodra@gmail.com>
328 * m32c-ibld.c: Regenerate.
330 2020-01-06 Alan Modra <amodra@gmail.com>
333 * z80-dis.c (suffix): Don't use a local struct buffer copy.
334 Peek at next byte to prevent recursion on repeated prefix bytes.
335 Ensure uninitialised "mybuf" is not accessed.
336 (print_insn_z80): Don't zero n_fetch and n_used here,..
337 (print_insn_z80_buf): ..do it here instead.
339 2020-01-04 Alan Modra <amodra@gmail.com>
341 * m32r-ibld.c: Regenerate.
343 2020-01-04 Alan Modra <amodra@gmail.com>
345 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
347 2020-01-04 Alan Modra <amodra@gmail.com>
349 * crx-dis.c (match_opcode): Avoid shift left of signed value.
351 2020-01-04 Alan Modra <amodra@gmail.com>
353 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
355 2020-01-03 Jan Beulich <jbeulich@suse.com>
357 * aarch64-tbl.h (aarch64_opcode_table): Use
358 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
360 2020-01-03 Jan Beulich <jbeulich@suse.com>
362 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
363 forms of SUDOT and USDOT.
365 2020-01-03 Jan Beulich <jbeulich@suse.com>
367 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
369 * opcodes/aarch64-dis-2.c: Re-generate.
371 2020-01-03 Jan Beulich <jbeulich@suse.com>
373 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
375 * opcodes/aarch64-dis-2.c: Re-generate.
377 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
379 * z80-dis.c: Add support for eZ80 and Z80 instructions.
381 2020-01-01 Alan Modra <amodra@gmail.com>
383 Update year range in copyright notice of all files.
385 For older changes see ChangeLog-2019
387 Copyright (C) 2020 Free Software Foundation, Inc.
389 Copying and distribution of this file, with or without modification,
390 are permitted in any medium without royalty provided the copyright
391 notice and this notice are preserved.
397 version-control: never