opcodes/ChangeLog

   1 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/23642
   4         * i386-opc.h (VEXWIG): New.
   5         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
   6         * i386-tbl.h: Regenerated.
   7
   8 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
   9
  10         PR binutils/23655
  11         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
  12         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
  13         * i386-dis.c (EXxEVexR64): New.
  14         (evex_rounding_64_mode): Likewise.
  15         (OP_Rounding): Handle evex_rounding_64_mode.
  16
  17 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  18
  19         PR binutils/23655
  20         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
  21         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
  22         * i386-dis.c (Edqa): New.
  23         (dqa_mode): Likewise.
  24         (intel_operand_size): Handle dqa_mode as m_mode.
  25         (OP_E_register): Handle dqa_mode as dq_mode.
  26         (OP_E_memory): Set shift for dqa_mode based on address_mode.
  27
  28 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
  29
  30         * i386-dis.c (OP_E_memory): Reformat.
  31
  32 2018-09-14  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-opc.tbl (crc32): Fold byte and word forms.
  35         * i386-tbl.h: Re-generate.
  36
  37 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
  38
  39         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
  40         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
  41         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
  42         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
  43         * i386-tbl.h: Regenerated.
  44
  45 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
  48         meaningless.
  49         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
  50         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
  51         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
  52         * i386-tbl.h: Re-generate.
  53
  54 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
  57         AVX512_4VNNIW insns.
  58         * i386-tbl.h: Re-generate.
  59
  60 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
  63         meaningless.
  64         * i386-tbl.h: Re-generate.
  65
  66 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
  69         meaningless.
  70         * i386-tbl.h: Re-generate.
  71
  72 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
  75         meaningless.
  76         * i386-tbl.h: Re-generate.
  77
  78 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  79
  80         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
  81         meaningless.
  82         * i386-tbl.h: Re-generate.
  83
  84 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
  87         meaningless.
  88         * i386-tbl.h: Re-generate.
  89
  90 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
  93         * i386-tbl.h: Re-generate.
  94
  95 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
  98         * i386-tbl.h: Re-generate.
  99
 100 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 101
 102         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 103         meaningless.
 104         * i386-tbl.h: Re-generate.
 105
 106 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 107
 108         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 109         meaningless.
 110         * i386-tbl.h: Re-generate.
 111
 112 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 113
 114         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 115         * i386-tbl.h: Re-generate.
 116
 117 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 120         * i386-tbl.h: Re-generate.
 121
 122 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 123
 124         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 125         * i386-tbl.h: Re-generate.
 126
 127 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 130         meaningless.
 131         * i386-tbl.h: Re-generate.
 132
 133 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 136         meaningless.
 137         * i386-tbl.h: Re-generate.
 138
 139 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 140
 141         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 142         meaningless.
 143         * i386-tbl.h: Re-generate.
 144
 145 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 148         * i386-tbl.h: Re-generate.
 149
 150 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 153         * i386-tbl.h: Re-generate.
 154
 155 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 156
 157         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 158         * i386-tbl.h: Re-generate.
 159
 160 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 161
 162         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 163         (vpbroadcastw, rdpid): Drop NoRex64.
 164         * i386-tbl.h: Re-generate.
 165
 166 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 169         store templates, adding D.
 170         * i386-tbl.h: Re-generate.
 171
 172 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 173
 174         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 175         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 176         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 177         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 178         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 179         Fold load and store templates where possible, adding D. Drop
 180         IgnoreSize where it was pointlessly present. Drop redundant
 181         *word.
 182         * i386-tbl.h: Re-generate.
 183
 184 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 187         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 188         (intel_operand_size): Handle v_bndmk_mode.
 189         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 190
 191 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 192
 193         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 194
 195 2018-08-31  Kito Cheng  <kito@andestech.com>
 196
 197         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 198         compressed floating point instructions.
 199
 200 2018-08-30  Kito Cheng  <kito@andestech.com>
 201
 202         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 203         riscv_opcode.xlen_requirement.
 204         * riscv-opc.c (riscv_opcodes): Update for struct change.
 205
 206 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 207
 208         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 209         psr (PWRPSR) instruction.
 210
 211 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 212
 213         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 214
 215 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 216
 217         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 218
 219 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 220
 221         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 222         loongson3a as an alias of gs464 for compatibility.
 223         * mips-opc.c (mips_opcodes): Change Comments.
 224
 225 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 226
 227         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 228         option.
 229         (print_mips_disassembler_options): Document -M loongson-ext.
 230         * mips-opc.c (LEXT2): New macro.
 231         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 232
 233 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 234
 235          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 236          descriptors.
 237          (parse_mips_ase_option): Handle -M loongson-ext option.
 238          (print_mips_disassembler_options): Document -M loongson-ext.
 239          * mips-opc.c (IL3A): Delete.
 240          * mips-opc.c (LEXT): New macro.
 241          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 242          instructions.
 243
 244 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 245
 246         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 247         descriptors.
 248         (parse_mips_ase_option): Handle -M loongson-cam option.
 249         (print_mips_disassembler_options): Document -M loongson-cam.
 250         * mips-opc.c (LCAM): New macro.
 251         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 252         instructions.
 253
 254 2018-08-21  Alan Modra  <amodra@gmail.com>
 255
 256         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 257         (skip_optional_operands): Count optional operands, and update
 258         ppc_optional_operand_value call.
 259         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 260         (extract_vlensi): Likewise.
 261         (extract_fxm): Return default value for missing optional operand.
 262         (extract_ls, extract_raq, extract_tbr): Likewise.
 263         (insert_sxl, extract_sxl): New functions.
 264         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 265         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 266         flag and extra entry.
 267         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 268         extract_sxl.
 269
 270 2018-08-20  Alan Modra  <amodra@gmail.com>
 271
 272         * sh-opc.h (MASK): Simplify.
 273
 274 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 275
 276         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 277         BM_RESERVED0 or BM_RESERVED1
 278         (bm_rel_decode, bm_n_bytes): Ditto.
 279
 280 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 281
 282         * s12z.h: Delete.
 283
 284 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 285
 286         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 287         address with the addr32 prefix and without base nor index
 288         registers.
 289
 290 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 291
 292         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 293         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 294         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 295         (cpu_flags): Add CpuCMOV and CpuFXSR.
 296         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 297         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 298         * i386-init.h: Regenerated.
 299         * i386-tbl.h: Likewise.
 300
 301 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 302
 303         * arc-regs.h: Update auxiliary registers.
 304
 305 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 308         (RegIP, RegIZ): Define.
 309         * i386-reg.tbl: Adjust comments.
 310         (rip): Use Qword instead of BaseIndex. Use RegIP.
 311         (eip): Use Dword instead of BaseIndex. Use RegIP.
 312         (riz): Add Qword. Use RegIZ.
 313         (eiz): Add Dword. Use RegIZ.
 314         * i386-tbl.h: Re-generate.
 315
 316 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 319         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 320         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 321         * i386-tbl.h: Re-generate.
 322
 323 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-gen.c (operand_types): Remove Mem field.
 326         * i386-opc.h (union i386_operand_type): Remove mem field.
 327         * i386-init.h, i386-tbl.h: Re-generate.
 328
 329 2018-08-01  Alan Modra  <amodra@gmail.com>
 330
 331         * po/POTFILES.in: Regenerate.
 332
 333 2018-07-31  Nick Clifton  <nickc@redhat.com>
 334
 335         * po/sv.po: Updated Swedish translation.
 336
 337 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 340         * i386-init.h, i386-tbl.h: Re-generate.
 341
 342 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 343
 344         * i386-opc.h (ZEROING_MASKING) Rename to ...
 345         (DYNAMIC_MASKING): ... this. Adjust comment.
 346         * i386-opc.tbl (MaskingMorZ): Define.
 347         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 348         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 349         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 350         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 351         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 352         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 353         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 354         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 355         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 356
 357 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-opc.tbl: Use element rather than vector size for AVX512*
 360         scatter/gather insns.
 361         * i386-tbl.h: Re-generate.
 362
 363 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 366         (cpu_flags): Drop CpuVREX.
 367         * i386-opc.h (CpuVREX): Delete.
 368         (union i386_cpu_flags): Remove cpuvrex.
 369         * i386-init.h, i386-tbl.h: Re-generate.
 370
 371 2018-07-30  Jim Wilson  <jimw@sifive.com>
 372
 373         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 374         fields.
 375         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 376
 377 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 378
 379         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 380         * Makefile.in: Regenerated.
 381         * configure.ac: Add C-SKY.
 382         * configure: Regenerated.
 383         * csky-dis.c: New file.
 384         * csky-opc.h: New file.
 385         * disassemble.c (ARCH_csky): Define.
 386         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 387         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 388
 389 2018-07-27  Alan Modra  <amodra@gmail.com>
 390
 391         * ppc-opc.c (insert_sprbat): Correct function parameter and
 392         return type.
 393         (extract_sprbat): Likewise, variable too.
 394
 395 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 396             Alan Modra  <amodra@gmail.com>
 397
 398         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 399         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 400         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 401         support disjointed BAT.
 402         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 403         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 404         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 405
 406 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 407             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 408
 409         * i386-gen.c (adjust_broadcast_modifier): New function.
 410         (process_i386_opcode_modifier): Add an argument for operands.
 411         Adjust the Broadcast value based on operands.
 412         (output_i386_opcode): Pass operand_types to
 413         process_i386_opcode_modifier.
 414         (process_i386_opcodes): Pass NULL as operands to
 415         process_i386_opcode_modifier.
 416         * i386-opc.h (BYTE_BROADCAST): New.
 417         (WORD_BROADCAST): Likewise.
 418         (DWORD_BROADCAST): Likewise.
 419         (QWORD_BROADCAST): Likewise.
 420         (i386_opcode_modifier): Expand broadcast to 3 bits.
 421         * i386-tbl.h: Regenerated.
 422
 423 2018-07-24  Alan Modra  <amodra@gmail.com>
 424
 425         PR 23430
 426         * or1k-desc.h: Regenerate.
 427
 428 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 431         vcvtusi2ss, and vcvtusi2sd.
 432         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 433         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 434         * i386-tbl.h: Re-generate.
 435
 436 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 437
 438         * arc-opc.c (extract_w6): Fix extending the sign.
 439
 440 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 441
 442         * arc-tbl.h (vewt): Allow it for ARC EM family.
 443
 444 2018-07-23  Alan Modra  <amodra@gmail.com>
 445
 446         PR 23419
 447         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 448         opcode variants for mtspr/mfspr encodings.
 449
 450 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 451             Maciej W. Rozycki  <macro@mips.com>
 452
 453         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 454         loongson3a descriptors.
 455         (parse_mips_ase_option): Handle -M loongson-mmi option.
 456         (print_mips_disassembler_options): Document -M loongson-mmi.
 457         * mips-opc.c (LMMI): New macro.
 458         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 459         instructions.
 460
 461 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 462
 463         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 464         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 465         IgnoreSize and [XYZ]MMword where applicable.
 466         * i386-tbl.h: Re-generate.
 467
 468 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 471         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 472         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 473         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 474         * i386-tbl.h: Re-generate.
 475
 476 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 479         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 480         VPCLMULQDQ templates into their respective AVX512VL counterparts
 481         where possible, using Disp8ShiftVL and CheckRegSize instead of
 482         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 483         * i386-tbl.h: Re-generate.
 484
 485 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 488         AVX512VL counterparts where possible, using Disp8ShiftVL and
 489         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 490         IgnoreSize) as appropriate.
 491         * i386-tbl.h: Re-generate.
 492
 493 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-opc.tbl: Fold AVX512BW templates into their respective
 496         AVX512VL counterparts where possible, using Disp8ShiftVL and
 497         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 498         IgnoreSize) as appropriate.
 499         * i386-tbl.h: Re-generate.
 500
 501 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-opc.tbl: Fold AVX512CD templates into their respective
 504         AVX512VL counterparts where possible, using Disp8ShiftVL and
 505         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 506         IgnoreSize) as appropriate.
 507         * i386-tbl.h: Re-generate.
 508
 509 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 510
 511         * i386-opc.h (DISP8_SHIFT_VL): New.
 512         * i386-opc.tbl (Disp8ShiftVL):  Define.
 513         (various): Fold AVX512VL templates into their respective
 514         AVX512F counterparts where possible, using Disp8ShiftVL and
 515         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 516         IgnoreSize) as appropriate.
 517         * i386-tbl.h: Re-generate.
 518
 519 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 520
 521         * Makefile.am: Change dependencies and rule for
 522         $(srcdir)/i386-init.h.
 523         * Makefile.in: Re-generate.
 524         * i386-gen.c (process_i386_opcodes): New local variable
 525         "marker". Drop opening of input file. Recognize marker and line
 526         number directives.
 527         * i386-opc.tbl (OPCODE_I386_H): Define.
 528         (i386-opc.h): Include it.
 529         (None): Undefine.
 530
 531 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 532
 533         PR gas/23418
 534         * i386-opc.h (Byte): Update comments.
 535         (Word): Likewise.
 536         (Dword): Likewise.
 537         (Fword): Likewise.
 538         (Qword): Likewise.
 539         (Tbyte): Likewise.
 540         (Xmmword): Likewise.
 541         (Ymmword): Likewise.
 542         (Zmmword): Likewise.
 543         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 544         vcvttps2uqq.
 545         * i386-tbl.h: Regenerated.
 546
 547 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 548
 549         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 550         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 551         * aarch64-asm-2.c: Regenerate.
 552         * aarch64-dis-2.c: Regenerate.
 553         * aarch64-opc-2.c: Regenerate.
 554
 555 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 556
 557         PR binutils/23192
 558         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 559         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 560         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 561         sqdmulh, sqrdmulh): Use Em16.
 562
 563 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 564
 565         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 566         csdb together with them.
 567         (thumb32_opcodes): Likewise.
 568
 569 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 570
 571         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 572         requiring 32-bit registers as operands 2 and 3. Improve
 573         comments.
 574         (mwait, mwaitx): Fold templates. Improve comments.
 575         OPERAND_TYPE_INOUTPORTREG.
 576         * i386-tbl.h: Re-generate.
 577
 578 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-gen.c (operand_type_init): Remove
 581         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 582         OPERAND_TYPE_INOUTPORTREG.
 583         * i386-init.h: Re-generate.
 584
 585 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 586
 587         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 588         (wrssq, wrussq): Add Qword.
 589         * i386-tbl.h: Re-generate.
 590
 591 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 592
 593         * i386-opc.h: Rename OTMax to OTNum.
 594         (OTNumOfUints): Adjust calculation.
 595         (OTUnused): Directly alias to OTNum.
 596
 597 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 598
 599         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 600         `reg_xys'.
 601         (lea_reg_xys): Likewise.
 602         (print_insn_loop_primitive): Rename `reg' local variable to
 603         `reg_dxy'.
 604
 605 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 606
 607         PR binutils/23242
 608         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 609
 610 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 611
 612         PR binutils/23369
 613         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 614         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 615
 616 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 617
 618         PR tdep/8282
 619         * mips-dis.c (mips_option_arg_t): New enumeration.
 620         (mips_options): New variable.
 621         (disassembler_options_mips): New function.
 622         (print_mips_disassembler_options): Reimplement in terms of
 623         `disassembler_options_mips'.
 624         * arm-dis.c (disassembler_options_arm): Adapt to using the
 625         `disasm_options_and_args_t' structure.
 626         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 627         * s390-dis.c (disassembler_options_s390): Likewise.
 628
 629 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 630
 631         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 632         expected result.
 633         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 634         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 635         * testsuite/ld-arm/tls-longplt.d: Likewise.
 636
 637 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 638
 639         PR binutils/23192
 640         * aarch64-asm-2.c: Regenerate.
 641         * aarch64-dis-2.c: Likewise.
 642         * aarch64-opc-2.c: Likewise.
 643         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 644         * aarch64-opc.c (operand_general_constraint_met_p,
 645         aarch64_print_operand): Likewise.
 646         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 647         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 648         fmlal2, fmlsl2.
 649         (AARCH64_OPERANDS): Add Em2.
 650
 651 2018-06-26  Nick Clifton  <nickc@redhat.com>
 652
 653         * po/uk.po: Updated Ukranian translation.
 654         * po/de.po: Updated German translation.
 655         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 656
 657 2018-06-26  Nick Clifton  <nickc@redhat.com>
 658
 659         * nfp-dis.c: Fix spelling mistake.
 660
 661 2018-06-24  Nick Clifton  <nickc@redhat.com>
 662
 663         * configure: Regenerate.
 664         * po/opcodes.pot: Regenerate.
 665
 666 2018-06-24  Nick Clifton  <nickc@redhat.com>
 667
 668         2.31 branch created.
 669
 670 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 671
 672         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 673         * aarch64-asm-2.c: Regenerate.
 674         * aarch64-dis-2.c: Likewise.
 675
 676 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 677
 678         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 679         `-M ginv' option description.
 680
 681 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 682
 683         PR gas/23305
 684         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 685         la and lla.
 686
 687 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 688
 689         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 690         * configure.ac: Remove AC_PREREQ.
 691         * Makefile.in: Re-generate.
 692         * aclocal.m4: Re-generate.
 693         * configure: Re-generate.
 694
 695 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 696
 697         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 698         mips64r6 descriptors.
 699         (parse_mips_ase_option): Handle -Mginv option.
 700         (print_mips_disassembler_options): Document -Mginv.
 701         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 702         (GINV): New macro.
 703         (mips_opcodes): Define ginvi and ginvt.
 704
 705 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 706             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 707
 708         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 709         * mips-opc.c (CRC, CRC64): New macros.
 710         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 711         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 712         crc32cd for CRC64.
 713
 714 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 715
 716         PR 20319
 717         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 718         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 719
 720 2018-06-06  Alan Modra  <amodra@gmail.com>
 721
 722         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 723         setjmp.  Move init for some other vars later too.
 724
 725 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 726
 727         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 728         (dis_private): Add new fields for property section tracking.
 729         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 730         (xtensa_instruction_fits): New functions.
 731         (fetch_data): Bump minimal fetch size to 4.
 732         (print_insn_xtensa): Make struct dis_private static.
 733         Load and prepare property table on section change.
 734         Don't disassemble literals. Don't disassemble instructions that
 735         cross property table boundaries.
 736
 737 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 738
 739         * configure: Regenerated.
 740
 741 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 742
 743         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 744         * i386-tbl.h: Re-generate.
 745
 746 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-opc.tbl (sldt, str): Add NoRex64.
 749         * i386-tbl.h: Re-generate.
 750
 751 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-opc.tbl (invpcid): Add Oword.
 754         * i386-tbl.h: Re-generate.
 755
 756 2018-06-01  Alan Modra  <amodra@gmail.com>
 757
 758         * sysdep.h (_bfd_error_handler): Don't declare.
 759         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 760         * rl78-decode.opc: Likewise.
 761         * msp430-decode.c: Regenerate.
 762         * rl78-decode.c: Regenerate.
 763
 764 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 765
 766         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 767         * i386-init.h : Regenerated.
 768
 769 2018-05-25  Alan Modra  <amodra@gmail.com>
 770
 771         * Makefile.in: Regenerate.
 772         * po/POTFILES.in: Regenerate.
 773
 774 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 775
 776         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 777         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 778         (insert_bab, extract_bab, insert_btab, extract_btab,
 779         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 780         (BAT, BBA VBA RBS XB6S): Delete macros.
 781         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 782         (BB, BD, RBX, XC6): Update for new macros.
 783         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 784         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 785         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 786         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 787
 788 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 789
 790         * Makefile.am: Add support for s12z architecture.
 791         * configure.ac: Likewise.
 792         * disassemble.c: Likewise.
 793         * disassemble.h: Likewise.
 794         * Makefile.in: Regenerate.
 795         * configure: Regenerate.
 796         * s12z-dis.c: New file.
 797         * s12z.h: New file.
 798
 799 2018-05-18  Alan Modra  <amodra@gmail.com>
 800
 801         * nfp-dis.c: Don't #include libbfd.h.
 802         (init_nfp3200_priv): Use bfd_get_section_contents.
 803         (nit_nfp6000_mecsr_sec): Likewise.
 804
 805 2018-05-17  Nick Clifton  <nickc@redhat.com>
 806
 807         * po/zh_CN.po: Updated simplified Chinese translation.
 808
 809 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 810
 811         PR binutils/23109
 812         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 813         * aarch64-dis-2.c: Regenerate.
 814
 815 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 816
 817         PR binutils/21446
 818         * aarch64-asm.c (opintl.h): Include.
 819         (aarch64_ins_sysreg): Enforce read/write constraints.
 820         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 821         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 822         (F_REG_READ, F_REG_WRITE): New.
 823         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 824         AARCH64_OPND_SYSREG.
 825         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 826         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 827         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 828         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 829         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 830         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 831         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 832         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 833         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 834         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 835         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 836         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 837         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 838         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 839         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 840         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 841         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 842
 843 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 844
 845         PR binutils/21446
 846         * aarch64-dis.c (no_notes: New.
 847         (parse_aarch64_dis_option): Support notes.
 848         (aarch64_decode_insn, print_operands): Likewise.
 849         (print_aarch64_disassembler_options): Document notes.
 850         * aarch64-opc.c (aarch64_print_operand): Support notes.
 851
 852 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 853
 854         PR binutils/21446
 855         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 856         and take error struct.
 857         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 858         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 859         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 860         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 861         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 862         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 863         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 864         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 865         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 866         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 867         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 868         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 869         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 870         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 871         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 872         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 873         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 874         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 875         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 876         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 877         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 878         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 879         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 880         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 881         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 882         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 883         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 884         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 885         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 886         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 887         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 888         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 889         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 890         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 891         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 892         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 893         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 894         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 895         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 896         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 897         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 898         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 899         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 900         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 901         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 902         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 903         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 904         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 905         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 906         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 907         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 908         (determine_disassembling_preference, aarch64_decode_insn,
 909         print_insn_aarch64_word, print_insn_data): Take errors struct.
 910         (print_insn_aarch64): Use errors.
 911         * aarch64-asm-2.c: Regenerate.
 912         * aarch64-dis-2.c: Regenerate.
 913         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 914         boolean in aarch64_insert_operan.
 915         (print_operand_extractor): Likewise.
 916         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 917
 918 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 919
 920         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 921
 922 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 923
 924         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 925
 926 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 927
 928         * cr16-opc.c (cr16_instruction): Comment typo fix.
 929         * hppa-dis.c (print_insn_hppa): Likewise.
 930
 931 2018-05-08  Jim Wilson  <jimw@sifive.com>
 932
 933         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 934         (match_c_slli64, match_srxi_as_c_srxi): New.
 935         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 936         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 937         <c.slli, c.srli, c.srai>: Use match_s_slli.
 938         <c.slli64, c.srli64, c.srai64>: New.
 939
 940 2018-05-08  Alan Modra  <amodra@gmail.com>
 941
 942         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 943         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 944         partition opcode space for index lookup.
 945
 946 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 947
 948         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 949         <insn_length>: ...with this.  Update usage.
 950         Remove duplicate call to *info->memory_error_func.
 951
 952 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 953             H.J. Lu  <hongjiu.lu@intel.com>
 954
 955         * i386-dis.c (Gva): New.
 956         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 957         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 958         (prefix_table): New instructions (see prefix above).
 959         (mod_table): New instructions (see prefix above).
 960         (OP_G): Handle va_mode.
 961         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 962         CPU_MOVDIR64B_FLAGS.
 963         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 964         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 965         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 966         * i386-opc.tbl: Add movidir{i,64b}.
 967         * i386-init.h: Regenerated.
 968         * i386-tbl.h: Likewise.
 969
 970 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 971
 972         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 973         AddrPrefixOpReg.
 974         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 975         (AddrPrefixOpReg): This.
 976         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 977         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 978
 979 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 980
 981         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 982         (vle_num_opcodes): Likewise.
 983         (spe2_num_opcodes): Likewise.
 984         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 985         initialization loop.
 986         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 987         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 988         only once.
 989
 990 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 991
 992         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 993
 994 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 995
 996         Makefile.am: Added nfp-dis.c.
 997         configure.ac: Added bfd_nfp_arch.
 998         disassemble.h: Added print_insn_nfp prototype.
 999         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1000         nfp-dis.c: New, for NFP support.
1001         po/POTFILES.in: Added nfp-dis.c to the list.
1002         Makefile.in: Regenerate.
1003         configure: Regenerate.
1004
1005 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1006
1007         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1008         templates into their base ones.
1009         * i386-tlb.h: Re-generate.
1010
1011 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1012
1013         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1014         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1015         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1016         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1017         * i386-init.h: Re-generate.
1018
1019 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1022         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1023         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1024         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1025         comment.
1026         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1027         and CpuRegMask.
1028         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1029         CpuRegMask: Delete.
1030         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1031         cpuregzmm, and cpuregmask.
1032         * i386-init.h: Re-generate.
1033         * i386-tbl.h: Re-generate.
1034
1035 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1036
1037         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1038         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1039         * i386-init.h: Re-generate.
1040
1041 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-gen.c (VexImmExt): Delete.
1044         * i386-opc.h (VexImmExt, veximmext): Delete.
1045         * i386-opc.tbl: Drop all VexImmExt uses.
1046         * i386-tlb.h: Re-generate.
1047
1048 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1049
1050         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1051         register-only forms.
1052         * i386-tlb.h: Re-generate.
1053
1054 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1055
1056         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1057
1058 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1059
1060         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1061         PREFIX_0F1C.
1062         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1063         (cpu_flags): Add CpuCLDEMOTE.
1064         * i386-init.h: Regenerate.
1065         * i386-opc.h (enum): Add CpuCLDEMOTE,
1066         (i386_cpu_flags): Add cpucldemote.
1067         * i386-opc.tbl: Add cldemote.
1068         * i386-tbl.h: Regenerate.
1069
1070 2018-04-16  Alan Modra  <amodra@gmail.com>
1071
1072         * Makefile.am: Remove sh5 and sh64 support.
1073         * configure.ac: Likewise.
1074         * disassemble.c: Likewise.
1075         * disassemble.h: Likewise.
1076         * sh-dis.c: Likewise.
1077         * sh64-dis.c: Delete.
1078         * sh64-opc.c: Delete.
1079         * sh64-opc.h: Delete.
1080         * Makefile.in: Regenerate.
1081         * configure: Regenerate.
1082         * po/POTFILES.in: Regenerate.
1083
1084 2018-04-16  Alan Modra  <amodra@gmail.com>
1085
1086         * Makefile.am: Remove w65 support.
1087         * configure.ac: Likewise.
1088         * disassemble.c: Likewise.
1089         * disassemble.h: Likewise.
1090         * w65-dis.c: Delete.
1091         * w65-opc.h: Delete.
1092         * Makefile.in: Regenerate.
1093         * configure: Regenerate.
1094         * po/POTFILES.in: Regenerate.
1095
1096 2018-04-16  Alan Modra  <amodra@gmail.com>
1097
1098         * configure.ac: Remove we32k support.
1099         * configure: Regenerate.
1100
1101 2018-04-16  Alan Modra  <amodra@gmail.com>
1102
1103         * Makefile.am: Remove m88k support.
1104         * configure.ac: Likewise.
1105         * disassemble.c: Likewise.
1106         * disassemble.h: Likewise.
1107         * m88k-dis.c: Delete.
1108         * Makefile.in: Regenerate.
1109         * configure: Regenerate.
1110         * po/POTFILES.in: Regenerate.
1111
1112 2018-04-16  Alan Modra  <amodra@gmail.com>
1113
1114         * Makefile.am: Remove i370 support.
1115         * configure.ac: Likewise.
1116         * disassemble.c: Likewise.
1117         * disassemble.h: Likewise.
1118         * i370-dis.c: Delete.
1119         * i370-opc.c: Delete.
1120         * Makefile.in: Regenerate.
1121         * configure: Regenerate.
1122         * po/POTFILES.in: Regenerate.
1123
1124 2018-04-16  Alan Modra  <amodra@gmail.com>
1125
1126         * Makefile.am: Remove h8500 support.
1127         * configure.ac: Likewise.
1128         * disassemble.c: Likewise.
1129         * disassemble.h: Likewise.
1130         * h8500-dis.c: Delete.
1131         * h8500-opc.h: Delete.
1132         * Makefile.in: Regenerate.
1133         * configure: Regenerate.
1134         * po/POTFILES.in: Regenerate.
1135
1136 2018-04-16  Alan Modra  <amodra@gmail.com>
1137
1138         * configure.ac: Remove tahoe support.
1139         * configure: Regenerate.
1140
1141 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1142
1143         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1144         umwait.
1145         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1146         64-bit mode.
1147         * i386-tbl.h: Regenerated.
1148
1149 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1150
1151         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1152         PREFIX_MOD_1_0FAE_REG_6.
1153         (va_mode): New.
1154         (OP_E_register): Use va_mode.
1155         * i386-dis-evex.h (prefix_table):
1156         New instructions (see prefixes above).
1157         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1158         (cpu_flags): Likewise.
1159         * i386-opc.h (enum): Likewise.
1160         (i386_cpu_flags): Likewise.
1161         * i386-opc.tbl: Add umonitor, umwait, tpause.
1162         * i386-init.h: Regenerate.
1163         * i386-tbl.h: Likewise.
1164
1165 2018-04-11  Alan Modra  <amodra@gmail.com>
1166
1167         * opcodes/i860-dis.c: Delete.
1168         * opcodes/i960-dis.c: Delete.
1169         * Makefile.am: Remove i860 and i960 support.
1170         * configure.ac: Likewise.
1171         * disassemble.c: Likewise.
1172         * disassemble.h: Likewise.
1173         * Makefile.in: Regenerate.
1174         * configure: Regenerate.
1175         * po/POTFILES.in: Regenerate.
1176
1177 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1178
1179         PR binutils/23025
1180         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1181         to 0.
1182         (print_insn): Clear vex instead of vex.evex.
1183
1184 2018-04-04  Nick Clifton  <nickc@redhat.com>
1185
1186         * po/es.po: Updated Spanish translation.
1187
1188 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-gen.c (opcode_modifiers): Delete VecESize.
1191         * i386-opc.h (VecESize): Delete.
1192         (struct i386_opcode_modifier): Delete vecesize.
1193         * i386-opc.tbl: Drop VecESize.
1194         * i386-tlb.h: Re-generate.
1195
1196 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1197
1198         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1199         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1200         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1201         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1202         * i386-tlb.h: Re-generate.
1203
1204 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1205
1206         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1207         Fold AVX512 forms
1208         * i386-tlb.h: Re-generate.
1209
1210 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1211
1212         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1213         (vex_len_table): Drop Y for vcvt*2si.
1214         (putop): Replace plain 'Y' handling by abort().
1215
1216 2018-03-28  Nick Clifton  <nickc@redhat.com>
1217
1218         PR 22988
1219         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1220         instructions with only a base address register.
1221         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1222         handle AARHC64_OPND_SVE_ADDR_R.
1223         (aarch64_print_operand): Likewise.
1224         * aarch64-asm-2.c: Regenerate.
1225         * aarch64_dis-2.c: Regenerate.
1226         * aarch64-opc-2.c: Regenerate.
1227
1228 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1229
1230         * i386-opc.tbl: Drop VecESize from register only insn forms and
1231         memory forms not allowing broadcast.
1232         * i386-tlb.h: Re-generate.
1233
1234 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1235
1236         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1237         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1238         sha256*): Drop Disp<N>.
1239
1240 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1241
1242         * i386-dis.c (EbndS, bnd_swap_mode): New.
1243         (prefix_table): Use EbndS.
1244         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1245         * i386-opc.tbl (bndmov): Move misplaced Load.
1246         * i386-tlb.h: Re-generate.
1247
1248 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1249
1250         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1251         templates allowing memory operands and folded ones for register
1252         only flavors.
1253         * i386-tlb.h: Re-generate.
1254
1255 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1256
1257         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1258         256-bit templates. Drop redundant leftover Disp<N>.
1259         * i386-tlb.h: Re-generate.
1260
1261 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1262
1263         * riscv-opc.c (riscv_insn_types): New.
1264
1265 2018-03-13  Nick Clifton  <nickc@redhat.com>
1266
1267         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1268
1269 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1270
1271         * i386-opc.tbl: Add Optimize to clr.
1272         * i386-tbl.h: Regenerated.
1273
1274 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1275
1276         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1277         * i386-opc.h (OldGcc): Removed.
1278         (i386_opcode_modifier): Remove oldgcc.
1279         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1280         instructions for old (<= 2.8.1) versions of gcc.
1281         * i386-tbl.h: Regenerated.
1282
1283 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1284
1285         * i386-opc.h (EVEXDYN): New.
1286         * i386-opc.tbl: Fold various AVX512VL templates.
1287         * i386-tlb.h: Re-generate.
1288
1289 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1290
1291         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1292         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1293         vpexpandd, vpexpandq): Fold AFX512VF templates.
1294         * i386-tlb.h: Re-generate.
1295
1296 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1297
1298         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1299         Fold 128- and 256-bit VEX-encoded templates.
1300         * i386-tlb.h: Re-generate.
1301
1302 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1303
1304         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1305         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1306         vpexpandd, vpexpandq): Fold AVX512F templates.
1307         * i386-tlb.h: Re-generate.
1308
1309 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1310
1311         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1312         64-bit templates. Drop Disp<N>.
1313         * i386-tlb.h: Re-generate.
1314
1315 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1316
1317         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1318         and 256-bit templates.
1319         * i386-tlb.h: Re-generate.
1320
1321 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1322
1323         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1324         * i386-tlb.h: Re-generate.
1325
1326 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1327
1328         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1329         Drop NoAVX.
1330         * i386-tlb.h: Re-generate.
1331
1332 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1333
1334         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1335         * i386-tlb.h: Re-generate.
1336
1337 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1338
1339         * i386-gen.c (opcode_modifiers): Delete FloatD.
1340         * i386-opc.h (FloatD): Delete.
1341         (struct i386_opcode_modifier): Delete floatd.
1342         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1343         FloatD by D.
1344         * i386-tlb.h: Re-generate.
1345
1346 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1347
1348         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1349
1350 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1351
1352         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1353         * i386-tlb.h: Re-generate.
1354
1355 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1356
1357         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1358         forms.
1359         * i386-tlb.h: Re-generate.
1360
1361 2018-03-07  Alan Modra  <amodra@gmail.com>
1362
1363         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1364         bfd_arch_rs6000.
1365         * disassemble.h (print_insn_rs6000): Delete.
1366         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1367         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1368         (print_insn_rs6000): Delete.
1369
1370 2018-03-03  Alan Modra  <amodra@gmail.com>
1371
1372         * sysdep.h (opcodes_error_handler): Define.
1373         (_bfd_error_handler): Declare.
1374         * Makefile.am: Remove stray #.
1375         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1376         EDIT" comment.
1377         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1378         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1379         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1380         opcodes_error_handler to print errors.  Standardize error messages.
1381         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1382         and include opintl.h.
1383         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1384         * i386-gen.c: Standardize error messages.
1385         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1386         * Makefile.in: Regenerate.
1387         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1388         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1389         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1390         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1391         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1392         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1393         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1394         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1395         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1396         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1397         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1398         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1399         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1400
1401 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1402
1403         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1404         vpsub[bwdq] instructions.
1405         * i386-tbl.h: Regenerated.
1406
1407 2018-03-01  Alan Modra  <amodra@gmail.com>
1408
1409         * configure.ac (ALL_LINGUAS): Sort.
1410         * configure: Regenerate.
1411
1412 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1413
1414         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1415         macro by assignements.
1416
1417 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1418
1419         PR gas/22871
1420         * i386-gen.c (opcode_modifiers): Add Optimize.
1421         * i386-opc.h (Optimize): New enum.
1422         (i386_opcode_modifier): Add optimize.
1423         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1424         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1425         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1426         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1427         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1428         vpxord and vpxorq.
1429         * i386-tbl.h: Regenerated.
1430
1431 2018-02-26  Alan Modra  <amodra@gmail.com>
1432
1433         * crx-dis.c (getregliststring): Allocate a large enough buffer
1434         to silence false positive gcc8 warning.
1435
1436 2018-02-22  Shea Levy <shea@shealevy.com>
1437
1438         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1439
1440 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1441
1442         * i386-opc.tbl: Add {rex},
1443         * i386-tbl.h: Regenerated.
1444
1445 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1446
1447         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1448         (mips16_opcodes): Replace `M' with `m' for "restore".
1449
1450 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1451
1452         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1453
1454 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1455
1456         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1457         variable to `function_index'.
1458
1459 2018-02-13  Nick Clifton  <nickc@redhat.com>
1460
1461         PR 22823
1462         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1463         about truncation of printing.
1464
1465 2018-02-12  Henry Wong <henry@stuffedcow.net>
1466
1467         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1468
1469 2018-02-05  Nick Clifton  <nickc@redhat.com>
1470
1471         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1472
1473 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1474
1475         * i386-dis.c (enum): Add pconfig.
1476         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1477         (cpu_flags): Add CpuPCONFIG.
1478         * i386-opc.h (enum): Add CpuPCONFIG.
1479         (i386_cpu_flags): Add cpupconfig.
1480         * i386-opc.tbl: Add PCONFIG instruction.
1481         * i386-init.h: Regenerate.
1482         * i386-tbl.h: Likewise.
1483
1484 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1485
1486         * i386-dis.c (enum): Add PREFIX_0F09.
1487         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1488         (cpu_flags): Add CpuWBNOINVD.
1489         * i386-opc.h (enum): Add CpuWBNOINVD.
1490         (i386_cpu_flags): Add cpuwbnoinvd.
1491         * i386-opc.tbl: Add WBNOINVD instruction.
1492         * i386-init.h: Regenerate.
1493         * i386-tbl.h: Likewise.
1494
1495 2018-01-17  Jim Wilson  <jimw@sifive.com>
1496
1497         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1498
1499 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1500
1501         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1502         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1503         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1504         (cpu_flags): Add CpuIBT, CpuSHSTK.
1505         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1506         (i386_cpu_flags): Add cpuibt, cpushstk.
1507         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1508         * i386-init.h: Regenerate.
1509         * i386-tbl.h: Likewise.
1510
1511 2018-01-16  Nick Clifton  <nickc@redhat.com>
1512
1513         * po/pt_BR.po: Updated Brazilian Portugese translation.
1514         * po/de.po: Updated German translation.
1515
1516 2018-01-15  Jim Wilson  <jimw@sifive.com>
1517
1518         * riscv-opc.c (match_c_nop): New.
1519         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1520
1521 2018-01-15  Nick Clifton  <nickc@redhat.com>
1522
1523         * po/uk.po: Updated Ukranian translation.
1524
1525 2018-01-13  Nick Clifton  <nickc@redhat.com>
1526
1527         * po/opcodes.pot: Regenerated.
1528
1529 2018-01-13  Nick Clifton  <nickc@redhat.com>
1530
1531         * configure: Regenerate.
1532
1533 2018-01-13  Nick Clifton  <nickc@redhat.com>
1534
1535         2.30 branch created.
1536
1537 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1538
1539         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1540         * i386-tbl.h: Regenerate.
1541
1542 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1543
1544         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1545         * i386-tbl.h: Re-generate.
1546
1547 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1548
1549         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1550         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1551         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1552         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1553         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1554         Disp8MemShift of AVX512VL forms.
1555         * i386-tbl.h: Re-generate.
1556
1557 2018-01-09  Jim Wilson  <jimw@sifive.com>
1558
1559         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1560         then the hi_addr value is zero.
1561
1562 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1563
1564         * arm-dis.c (arm_opcodes): Add csdb.
1565         (thumb32_opcodes): Add csdb.
1566
1567 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1568
1569         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1570         * aarch64-asm-2.c: Regenerate.
1571         * aarch64-dis-2.c: Regenerate.
1572         * aarch64-opc-2.c: Regenerate.
1573
1574 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1575
1576         PR gas/22681
1577         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1578         Remove AVX512 vmovd with 64-bit operands.
1579         * i386-tbl.h: Regenerated.
1580
1581 2018-01-05  Jim Wilson  <jimw@sifive.com>
1582
1583         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1584         jalr.
1585
1586 2018-01-03  Alan Modra  <amodra@gmail.com>
1587
1588         Update year range in copyright notice of all files.
1589
1590 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1591
1592         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1593         and OPERAND_TYPE_REGZMM entries.
1594
1595 For older changes see ChangeLog-2017
1596 \f
1597 Copyright (C) 2018 Free Software Foundation, Inc.
1598
1599 Copying and distribution of this file, with or without modification,
1600 are permitted in any medium without royalty provided the copyright
1601 notice and this notice are preserved.
1602
1603 Local Variables:
1604 mode: change-log
1605 left-margin: 8
1606 fill-column: 74
1607 version-control: never
1608 End: