1 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
5 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
6 * i386-dis.c (Edqa): New.
8 (intel_operand_size): Handle dqa_mode as m_mode.
9 (OP_E_register): Handle dqa_mode as dq_mode.
10 (OP_E_memory): Set shift for dqa_mode based on address_mode.
12 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
14 * i386-dis.c (OP_E_memory): Reformat.
16 2018-09-14 Jan Beulich <jbeulich@suse.com>
18 * i386-opc.tbl (crc32): Fold byte and word forms.
19 * i386-tbl.h: Re-generate.
21 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
23 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
24 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
25 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
26 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
27 * i386-tbl.h: Regenerated.
29 2018-09-13 Jan Beulich <jbeulich@suse.com>
31 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
33 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
34 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
35 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
36 * i386-tbl.h: Re-generate.
38 2018-09-13 Jan Beulich <jbeulich@suse.com>
40 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
42 * i386-tbl.h: Re-generate.
44 2018-09-13 Jan Beulich <jbeulich@suse.com>
46 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
48 * i386-tbl.h: Re-generate.
50 2018-09-13 Jan Beulich <jbeulich@suse.com>
52 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
54 * i386-tbl.h: Re-generate.
56 2018-09-13 Jan Beulich <jbeulich@suse.com>
58 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
60 * i386-tbl.h: Re-generate.
62 2018-09-13 Jan Beulich <jbeulich@suse.com>
64 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
66 * i386-tbl.h: Re-generate.
68 2018-09-13 Jan Beulich <jbeulich@suse.com>
70 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
72 * i386-tbl.h: Re-generate.
74 2018-09-13 Jan Beulich <jbeulich@suse.com>
76 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
77 * i386-tbl.h: Re-generate.
79 2018-09-13 Jan Beulich <jbeulich@suse.com>
81 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
82 * i386-tbl.h: Re-generate.
84 2018-09-13 Jan Beulich <jbeulich@suse.com>
86 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
88 * i386-tbl.h: Re-generate.
90 2018-09-13 Jan Beulich <jbeulich@suse.com>
92 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
94 * i386-tbl.h: Re-generate.
96 2018-09-13 Jan Beulich <jbeulich@suse.com>
98 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
99 * i386-tbl.h: Re-generate.
101 2018-09-13 Jan Beulich <jbeulich@suse.com>
103 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
104 * i386-tbl.h: Re-generate.
106 2018-09-13 Jan Beulich <jbeulich@suse.com>
108 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
109 * i386-tbl.h: Re-generate.
111 2018-09-13 Jan Beulich <jbeulich@suse.com>
113 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
115 * i386-tbl.h: Re-generate.
117 2018-09-13 Jan Beulich <jbeulich@suse.com>
119 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
121 * i386-tbl.h: Re-generate.
123 2018-09-13 Jan Beulich <jbeulich@suse.com>
125 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
127 * i386-tbl.h: Re-generate.
129 2018-09-13 Jan Beulich <jbeulich@suse.com>
131 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
132 * i386-tbl.h: Re-generate.
134 2018-09-13 Jan Beulich <jbeulich@suse.com>
136 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
137 * i386-tbl.h: Re-generate.
139 2018-09-13 Jan Beulich <jbeulich@suse.com>
141 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
142 * i386-tbl.h: Re-generate.
144 2018-09-13 Jan Beulich <jbeulich@suse.com>
146 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
147 (vpbroadcastw, rdpid): Drop NoRex64.
148 * i386-tbl.h: Re-generate.
150 2018-09-13 Jan Beulich <jbeulich@suse.com>
152 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
153 store templates, adding D.
154 * i386-tbl.h: Re-generate.
156 2018-09-13 Jan Beulich <jbeulich@suse.com>
158 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
159 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
160 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
161 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
162 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
163 Fold load and store templates where possible, adding D. Drop
164 IgnoreSize where it was pointlessly present. Drop redundant
166 * i386-tbl.h: Re-generate.
168 2018-09-13 Jan Beulich <jbeulich@suse.com>
170 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
171 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
172 (intel_operand_size): Handle v_bndmk_mode.
173 (OP_E_memory): Likewise. Produce (bad) when also riprel.
175 2018-09-08 John Darrington <john@darrington.wattle.id.au>
177 * disassemble.c (ARCH_s12z): Define if ARCH_all.
179 2018-08-31 Kito Cheng <kito@andestech.com>
181 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
182 compressed floating point instructions.
184 2018-08-30 Kito Cheng <kito@andestech.com>
186 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
187 riscv_opcode.xlen_requirement.
188 * riscv-opc.c (riscv_opcodes): Update for struct change.
190 2018-08-29 Martin Aberg <maberg@gaisler.com>
192 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
193 psr (PWRPSR) instruction.
195 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
197 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
199 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
201 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
203 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
205 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
206 loongson3a as an alias of gs464 for compatibility.
207 * mips-opc.c (mips_opcodes): Change Comments.
209 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
211 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
213 (print_mips_disassembler_options): Document -M loongson-ext.
214 * mips-opc.c (LEXT2): New macro.
215 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
217 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
219 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
221 (parse_mips_ase_option): Handle -M loongson-ext option.
222 (print_mips_disassembler_options): Document -M loongson-ext.
223 * mips-opc.c (IL3A): Delete.
224 * mips-opc.c (LEXT): New macro.
225 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
228 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
230 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
232 (parse_mips_ase_option): Handle -M loongson-cam option.
233 (print_mips_disassembler_options): Document -M loongson-cam.
234 * mips-opc.c (LCAM): New macro.
235 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
238 2018-08-21 Alan Modra <amodra@gmail.com>
240 * ppc-dis.c (operand_value_powerpc): Init "invalid".
241 (skip_optional_operands): Count optional operands, and update
242 ppc_optional_operand_value call.
243 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
244 (extract_vlensi): Likewise.
245 (extract_fxm): Return default value for missing optional operand.
246 (extract_ls, extract_raq, extract_tbr): Likewise.
247 (insert_sxl, extract_sxl): New functions.
248 (insert_esync, extract_esync): Remove Power9 handling and simplify.
249 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
250 flag and extra entry.
251 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
254 2018-08-20 Alan Modra <amodra@gmail.com>
256 * sh-opc.h (MASK): Simplify.
258 2018-08-18 John Darrington <john@darrington.wattle.id.au>
260 * s12z-dis.c (bm_decode): Deal with cases where the mode is
261 BM_RESERVED0 or BM_RESERVED1
262 (bm_rel_decode, bm_n_bytes): Ditto.
264 2018-08-18 John Darrington <john@darrington.wattle.id.au>
268 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
270 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
271 address with the addr32 prefix and without base nor index
274 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
276 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
277 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
278 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
279 (cpu_flags): Add CpuCMOV and CpuFXSR.
280 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
281 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
282 * i386-init.h: Regenerated.
283 * i386-tbl.h: Likewise.
285 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
287 * arc-regs.h: Update auxiliary registers.
289 2018-08-06 Jan Beulich <jbeulich@suse.com>
291 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
292 (RegIP, RegIZ): Define.
293 * i386-reg.tbl: Adjust comments.
294 (rip): Use Qword instead of BaseIndex. Use RegIP.
295 (eip): Use Dword instead of BaseIndex. Use RegIP.
296 (riz): Add Qword. Use RegIZ.
297 (eiz): Add Dword. Use RegIZ.
298 * i386-tbl.h: Re-generate.
300 2018-08-03 Jan Beulich <jbeulich@suse.com>
302 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
303 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
304 vpmovzxdq, vpmovzxwd): Remove NoRex64.
305 * i386-tbl.h: Re-generate.
307 2018-08-03 Jan Beulich <jbeulich@suse.com>
309 * i386-gen.c (operand_types): Remove Mem field.
310 * i386-opc.h (union i386_operand_type): Remove mem field.
311 * i386-init.h, i386-tbl.h: Re-generate.
313 2018-08-01 Alan Modra <amodra@gmail.com>
315 * po/POTFILES.in: Regenerate.
317 2018-07-31 Nick Clifton <nickc@redhat.com>
319 * po/sv.po: Updated Swedish translation.
321 2018-07-31 Jan Beulich <jbeulich@suse.com>
323 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
324 * i386-init.h, i386-tbl.h: Re-generate.
326 2018-07-31 Jan Beulich <jbeulich@suse.com>
328 * i386-opc.h (ZEROING_MASKING) Rename to ...
329 (DYNAMIC_MASKING): ... this. Adjust comment.
330 * i386-opc.tbl (MaskingMorZ): Define.
331 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
332 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
333 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
334 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
335 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
336 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
337 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
338 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
339 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
341 2018-07-31 Jan Beulich <jbeulich@suse.com>
343 * i386-opc.tbl: Use element rather than vector size for AVX512*
344 scatter/gather insns.
345 * i386-tbl.h: Re-generate.
347 2018-07-31 Jan Beulich <jbeulich@suse.com>
349 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
350 (cpu_flags): Drop CpuVREX.
351 * i386-opc.h (CpuVREX): Delete.
352 (union i386_cpu_flags): Remove cpuvrex.
353 * i386-init.h, i386-tbl.h: Re-generate.
355 2018-07-30 Jim Wilson <jimw@sifive.com>
357 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
359 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
361 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
363 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
364 * Makefile.in: Regenerated.
365 * configure.ac: Add C-SKY.
366 * configure: Regenerated.
367 * csky-dis.c: New file.
368 * csky-opc.h: New file.
369 * disassemble.c (ARCH_csky): Define.
370 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
371 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
373 2018-07-27 Alan Modra <amodra@gmail.com>
375 * ppc-opc.c (insert_sprbat): Correct function parameter and
377 (extract_sprbat): Likewise, variable too.
379 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
380 Alan Modra <amodra@gmail.com>
382 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
383 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
384 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
385 support disjointed BAT.
386 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
387 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
388 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
390 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
391 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
393 * i386-gen.c (adjust_broadcast_modifier): New function.
394 (process_i386_opcode_modifier): Add an argument for operands.
395 Adjust the Broadcast value based on operands.
396 (output_i386_opcode): Pass operand_types to
397 process_i386_opcode_modifier.
398 (process_i386_opcodes): Pass NULL as operands to
399 process_i386_opcode_modifier.
400 * i386-opc.h (BYTE_BROADCAST): New.
401 (WORD_BROADCAST): Likewise.
402 (DWORD_BROADCAST): Likewise.
403 (QWORD_BROADCAST): Likewise.
404 (i386_opcode_modifier): Expand broadcast to 3 bits.
405 * i386-tbl.h: Regenerated.
407 2018-07-24 Alan Modra <amodra@gmail.com>
410 * or1k-desc.h: Regenerate.
412 2018-07-24 Jan Beulich <jbeulich@suse.com>
414 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
415 vcvtusi2ss, and vcvtusi2sd.
416 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
417 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
418 * i386-tbl.h: Re-generate.
420 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
422 * arc-opc.c (extract_w6): Fix extending the sign.
424 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
426 * arc-tbl.h (vewt): Allow it for ARC EM family.
428 2018-07-23 Alan Modra <amodra@gmail.com>
431 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
432 opcode variants for mtspr/mfspr encodings.
434 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
435 Maciej W. Rozycki <macro@mips.com>
437 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
438 loongson3a descriptors.
439 (parse_mips_ase_option): Handle -M loongson-mmi option.
440 (print_mips_disassembler_options): Document -M loongson-mmi.
441 * mips-opc.c (LMMI): New macro.
442 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
445 2018-07-19 Jan Beulich <jbeulich@suse.com>
447 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
448 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
449 IgnoreSize and [XYZ]MMword where applicable.
450 * i386-tbl.h: Re-generate.
452 2018-07-19 Jan Beulich <jbeulich@suse.com>
454 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
455 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
456 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
457 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
458 * i386-tbl.h: Re-generate.
460 2018-07-19 Jan Beulich <jbeulich@suse.com>
462 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
463 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
464 VPCLMULQDQ templates into their respective AVX512VL counterparts
465 where possible, using Disp8ShiftVL and CheckRegSize instead of
466 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
467 * i386-tbl.h: Re-generate.
469 2018-07-19 Jan Beulich <jbeulich@suse.com>
471 * i386-opc.tbl: Fold AVX512DQ templates into their respective
472 AVX512VL counterparts where possible, using Disp8ShiftVL and
473 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
474 IgnoreSize) as appropriate.
475 * i386-tbl.h: Re-generate.
477 2018-07-19 Jan Beulich <jbeulich@suse.com>
479 * i386-opc.tbl: Fold AVX512BW templates into their respective
480 AVX512VL counterparts where possible, using Disp8ShiftVL and
481 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
482 IgnoreSize) as appropriate.
483 * i386-tbl.h: Re-generate.
485 2018-07-19 Jan Beulich <jbeulich@suse.com>
487 * i386-opc.tbl: Fold AVX512CD templates into their respective
488 AVX512VL counterparts where possible, using Disp8ShiftVL and
489 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
490 IgnoreSize) as appropriate.
491 * i386-tbl.h: Re-generate.
493 2018-07-19 Jan Beulich <jbeulich@suse.com>
495 * i386-opc.h (DISP8_SHIFT_VL): New.
496 * i386-opc.tbl (Disp8ShiftVL): Define.
497 (various): Fold AVX512VL templates into their respective
498 AVX512F counterparts where possible, using Disp8ShiftVL and
499 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
500 IgnoreSize) as appropriate.
501 * i386-tbl.h: Re-generate.
503 2018-07-19 Jan Beulich <jbeulich@suse.com>
505 * Makefile.am: Change dependencies and rule for
506 $(srcdir)/i386-init.h.
507 * Makefile.in: Re-generate.
508 * i386-gen.c (process_i386_opcodes): New local variable
509 "marker". Drop opening of input file. Recognize marker and line
511 * i386-opc.tbl (OPCODE_I386_H): Define.
512 (i386-opc.h): Include it.
515 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
518 * i386-opc.h (Byte): Update comments.
527 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
529 * i386-tbl.h: Regenerated.
531 2018-07-12 Sudakshina Das <sudi.das@arm.com>
533 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
534 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
535 * aarch64-asm-2.c: Regenerate.
536 * aarch64-dis-2.c: Regenerate.
537 * aarch64-opc-2.c: Regenerate.
539 2018-07-12 Tamar Christina <tamar.christina@arm.com>
542 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
543 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
544 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
545 sqdmulh, sqrdmulh): Use Em16.
547 2018-07-11 Sudakshina Das <sudi.das@arm.com>
549 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
550 csdb together with them.
551 (thumb32_opcodes): Likewise.
553 2018-07-11 Jan Beulich <jbeulich@suse.com>
555 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
556 requiring 32-bit registers as operands 2 and 3. Improve
558 (mwait, mwaitx): Fold templates. Improve comments.
559 OPERAND_TYPE_INOUTPORTREG.
560 * i386-tbl.h: Re-generate.
562 2018-07-11 Jan Beulich <jbeulich@suse.com>
564 * i386-gen.c (operand_type_init): Remove
565 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
566 OPERAND_TYPE_INOUTPORTREG.
567 * i386-init.h: Re-generate.
569 2018-07-11 Jan Beulich <jbeulich@suse.com>
571 * i386-opc.tbl (wrssd, wrussd): Add Dword.
572 (wrssq, wrussq): Add Qword.
573 * i386-tbl.h: Re-generate.
575 2018-07-11 Jan Beulich <jbeulich@suse.com>
577 * i386-opc.h: Rename OTMax to OTNum.
578 (OTNumOfUints): Adjust calculation.
579 (OTUnused): Directly alias to OTNum.
581 2018-07-09 Maciej W. Rozycki <macro@mips.com>
583 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
585 (lea_reg_xys): Likewise.
586 (print_insn_loop_primitive): Rename `reg' local variable to
589 2018-07-06 Tamar Christina <tamar.christina@arm.com>
592 * aarch64-tbl.h (ldarh): Fix disassembly mask.
594 2018-07-06 Tamar Christina <tamar.christina@arm.com>
597 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
598 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
600 2018-07-02 Maciej W. Rozycki <macro@mips.com>
603 * mips-dis.c (mips_option_arg_t): New enumeration.
604 (mips_options): New variable.
605 (disassembler_options_mips): New function.
606 (print_mips_disassembler_options): Reimplement in terms of
607 `disassembler_options_mips'.
608 * arm-dis.c (disassembler_options_arm): Adapt to using the
609 `disasm_options_and_args_t' structure.
610 * ppc-dis.c (disassembler_options_powerpc): Likewise.
611 * s390-dis.c (disassembler_options_s390): Likewise.
613 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
615 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
617 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
618 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
619 * testsuite/ld-arm/tls-longplt.d: Likewise.
621 2018-06-29 Tamar Christina <tamar.christina@arm.com>
624 * aarch64-asm-2.c: Regenerate.
625 * aarch64-dis-2.c: Likewise.
626 * aarch64-opc-2.c: Likewise.
627 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
628 * aarch64-opc.c (operand_general_constraint_met_p,
629 aarch64_print_operand): Likewise.
630 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
631 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
633 (AARCH64_OPERANDS): Add Em2.
635 2018-06-26 Nick Clifton <nickc@redhat.com>
637 * po/uk.po: Updated Ukranian translation.
638 * po/de.po: Updated German translation.
639 * po/pt_BR.po: Updated Brazilian Portuguese translation.
641 2018-06-26 Nick Clifton <nickc@redhat.com>
643 * nfp-dis.c: Fix spelling mistake.
645 2018-06-24 Nick Clifton <nickc@redhat.com>
647 * configure: Regenerate.
648 * po/opcodes.pot: Regenerate.
650 2018-06-24 Nick Clifton <nickc@redhat.com>
654 2018-06-19 Tamar Christina <tamar.christina@arm.com>
656 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
657 * aarch64-asm-2.c: Regenerate.
658 * aarch64-dis-2.c: Likewise.
660 2018-06-21 Maciej W. Rozycki <macro@mips.com>
662 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
663 `-M ginv' option description.
665 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
668 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
671 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
673 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
674 * configure.ac: Remove AC_PREREQ.
675 * Makefile.in: Re-generate.
676 * aclocal.m4: Re-generate.
677 * configure: Re-generate.
679 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
681 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
682 mips64r6 descriptors.
683 (parse_mips_ase_option): Handle -Mginv option.
684 (print_mips_disassembler_options): Document -Mginv.
685 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
687 (mips_opcodes): Define ginvi and ginvt.
689 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
690 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
692 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
693 * mips-opc.c (CRC, CRC64): New macros.
694 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
695 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
698 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
701 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
702 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
704 2018-06-06 Alan Modra <amodra@gmail.com>
706 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
707 setjmp. Move init for some other vars later too.
709 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
711 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
712 (dis_private): Add new fields for property section tracking.
713 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
714 (xtensa_instruction_fits): New functions.
715 (fetch_data): Bump minimal fetch size to 4.
716 (print_insn_xtensa): Make struct dis_private static.
717 Load and prepare property table on section change.
718 Don't disassemble literals. Don't disassemble instructions that
719 cross property table boundaries.
721 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
723 * configure: Regenerated.
725 2018-06-01 Jan Beulich <jbeulich@suse.com>
727 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
728 * i386-tbl.h: Re-generate.
730 2018-06-01 Jan Beulich <jbeulich@suse.com>
732 * i386-opc.tbl (sldt, str): Add NoRex64.
733 * i386-tbl.h: Re-generate.
735 2018-06-01 Jan Beulich <jbeulich@suse.com>
737 * i386-opc.tbl (invpcid): Add Oword.
738 * i386-tbl.h: Re-generate.
740 2018-06-01 Alan Modra <amodra@gmail.com>
742 * sysdep.h (_bfd_error_handler): Don't declare.
743 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
744 * rl78-decode.opc: Likewise.
745 * msp430-decode.c: Regenerate.
746 * rl78-decode.c: Regenerate.
748 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
750 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
751 * i386-init.h : Regenerated.
753 2018-05-25 Alan Modra <amodra@gmail.com>
755 * Makefile.in: Regenerate.
756 * po/POTFILES.in: Regenerate.
758 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
760 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
761 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
762 (insert_bab, extract_bab, insert_btab, extract_btab,
763 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
764 (BAT, BBA VBA RBS XB6S): Delete macros.
765 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
766 (BB, BD, RBX, XC6): Update for new macros.
767 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
768 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
769 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
770 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
772 2018-05-18 John Darrington <john@darrington.wattle.id.au>
774 * Makefile.am: Add support for s12z architecture.
775 * configure.ac: Likewise.
776 * disassemble.c: Likewise.
777 * disassemble.h: Likewise.
778 * Makefile.in: Regenerate.
779 * configure: Regenerate.
780 * s12z-dis.c: New file.
783 2018-05-18 Alan Modra <amodra@gmail.com>
785 * nfp-dis.c: Don't #include libbfd.h.
786 (init_nfp3200_priv): Use bfd_get_section_contents.
787 (nit_nfp6000_mecsr_sec): Likewise.
789 2018-05-17 Nick Clifton <nickc@redhat.com>
791 * po/zh_CN.po: Updated simplified Chinese translation.
793 2018-05-16 Tamar Christina <tamar.christina@arm.com>
796 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
797 * aarch64-dis-2.c: Regenerate.
799 2018-05-15 Tamar Christina <tamar.christina@arm.com>
802 * aarch64-asm.c (opintl.h): Include.
803 (aarch64_ins_sysreg): Enforce read/write constraints.
804 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
805 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
806 (F_REG_READ, F_REG_WRITE): New.
807 * aarch64-opc.c (aarch64_print_operand): Generate notes for
809 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
810 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
811 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
812 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
813 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
814 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
815 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
816 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
817 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
818 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
819 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
820 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
821 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
822 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
823 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
824 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
825 msr (F_SYS_WRITE), mrs (F_SYS_READ).
827 2018-05-15 Tamar Christina <tamar.christina@arm.com>
830 * aarch64-dis.c (no_notes: New.
831 (parse_aarch64_dis_option): Support notes.
832 (aarch64_decode_insn, print_operands): Likewise.
833 (print_aarch64_disassembler_options): Document notes.
834 * aarch64-opc.c (aarch64_print_operand): Support notes.
836 2018-05-15 Tamar Christina <tamar.christina@arm.com>
839 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
840 and take error struct.
841 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
842 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
843 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
844 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
845 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
846 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
847 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
848 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
849 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
850 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
851 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
852 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
853 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
854 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
855 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
856 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
857 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
858 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
859 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
860 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
861 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
862 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
863 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
864 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
865 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
866 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
867 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
868 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
869 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
870 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
871 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
872 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
873 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
874 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
875 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
876 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
877 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
878 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
879 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
880 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
881 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
882 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
883 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
884 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
885 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
886 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
887 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
888 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
889 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
890 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
891 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
892 (determine_disassembling_preference, aarch64_decode_insn,
893 print_insn_aarch64_word, print_insn_data): Take errors struct.
894 (print_insn_aarch64): Use errors.
895 * aarch64-asm-2.c: Regenerate.
896 * aarch64-dis-2.c: Regenerate.
897 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
898 boolean in aarch64_insert_operan.
899 (print_operand_extractor): Likewise.
900 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
902 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
904 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
906 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
908 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
910 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
912 * cr16-opc.c (cr16_instruction): Comment typo fix.
913 * hppa-dis.c (print_insn_hppa): Likewise.
915 2018-05-08 Jim Wilson <jimw@sifive.com>
917 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
918 (match_c_slli64, match_srxi_as_c_srxi): New.
919 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
920 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
921 <c.slli, c.srli, c.srai>: Use match_s_slli.
922 <c.slli64, c.srli64, c.srai64>: New.
924 2018-05-08 Alan Modra <amodra@gmail.com>
926 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
927 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
928 partition opcode space for index lookup.
930 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
932 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
933 <insn_length>: ...with this. Update usage.
934 Remove duplicate call to *info->memory_error_func.
936 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
937 H.J. Lu <hongjiu.lu@intel.com>
939 * i386-dis.c (Gva): New.
940 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
941 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
942 (prefix_table): New instructions (see prefix above).
943 (mod_table): New instructions (see prefix above).
944 (OP_G): Handle va_mode.
945 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
947 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
948 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
949 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
950 * i386-opc.tbl: Add movidir{i,64b}.
951 * i386-init.h: Regenerated.
952 * i386-tbl.h: Likewise.
954 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
956 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
958 * i386-opc.h (AddrPrefixOp0): Renamed to ...
959 (AddrPrefixOpReg): This.
960 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
961 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
963 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
965 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
966 (vle_num_opcodes): Likewise.
967 (spe2_num_opcodes): Likewise.
968 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
970 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
971 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
974 2018-05-01 Tamar Christina <tamar.christina@arm.com>
976 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
978 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
980 Makefile.am: Added nfp-dis.c.
981 configure.ac: Added bfd_nfp_arch.
982 disassemble.h: Added print_insn_nfp prototype.
983 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
984 nfp-dis.c: New, for NFP support.
985 po/POTFILES.in: Added nfp-dis.c to the list.
986 Makefile.in: Regenerate.
987 configure: Regenerate.
989 2018-04-26 Jan Beulich <jbeulich@suse.com>
991 * i386-opc.tbl: Fold various non-memory operand AVX512VL
992 templates into their base ones.
993 * i386-tlb.h: Re-generate.
995 2018-04-26 Jan Beulich <jbeulich@suse.com>
997 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
998 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
999 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1000 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1001 * i386-init.h: Re-generate.
1003 2018-04-26 Jan Beulich <jbeulich@suse.com>
1005 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1006 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1007 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1008 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1010 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1012 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1014 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1015 cpuregzmm, and cpuregmask.
1016 * i386-init.h: Re-generate.
1017 * i386-tbl.h: Re-generate.
1019 2018-04-26 Jan Beulich <jbeulich@suse.com>
1021 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1022 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1023 * i386-init.h: Re-generate.
1025 2018-04-26 Jan Beulich <jbeulich@suse.com>
1027 * i386-gen.c (VexImmExt): Delete.
1028 * i386-opc.h (VexImmExt, veximmext): Delete.
1029 * i386-opc.tbl: Drop all VexImmExt uses.
1030 * i386-tlb.h: Re-generate.
1032 2018-04-25 Jan Beulich <jbeulich@suse.com>
1034 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1035 register-only forms.
1036 * i386-tlb.h: Re-generate.
1038 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1040 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1042 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1044 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1046 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1047 (cpu_flags): Add CpuCLDEMOTE.
1048 * i386-init.h: Regenerate.
1049 * i386-opc.h (enum): Add CpuCLDEMOTE,
1050 (i386_cpu_flags): Add cpucldemote.
1051 * i386-opc.tbl: Add cldemote.
1052 * i386-tbl.h: Regenerate.
1054 2018-04-16 Alan Modra <amodra@gmail.com>
1056 * Makefile.am: Remove sh5 and sh64 support.
1057 * configure.ac: Likewise.
1058 * disassemble.c: Likewise.
1059 * disassemble.h: Likewise.
1060 * sh-dis.c: Likewise.
1061 * sh64-dis.c: Delete.
1062 * sh64-opc.c: Delete.
1063 * sh64-opc.h: Delete.
1064 * Makefile.in: Regenerate.
1065 * configure: Regenerate.
1066 * po/POTFILES.in: Regenerate.
1068 2018-04-16 Alan Modra <amodra@gmail.com>
1070 * Makefile.am: Remove w65 support.
1071 * configure.ac: Likewise.
1072 * disassemble.c: Likewise.
1073 * disassemble.h: Likewise.
1074 * w65-dis.c: Delete.
1075 * w65-opc.h: Delete.
1076 * Makefile.in: Regenerate.
1077 * configure: Regenerate.
1078 * po/POTFILES.in: Regenerate.
1080 2018-04-16 Alan Modra <amodra@gmail.com>
1082 * configure.ac: Remove we32k support.
1083 * configure: Regenerate.
1085 2018-04-16 Alan Modra <amodra@gmail.com>
1087 * Makefile.am: Remove m88k support.
1088 * configure.ac: Likewise.
1089 * disassemble.c: Likewise.
1090 * disassemble.h: Likewise.
1091 * m88k-dis.c: Delete.
1092 * Makefile.in: Regenerate.
1093 * configure: Regenerate.
1094 * po/POTFILES.in: Regenerate.
1096 2018-04-16 Alan Modra <amodra@gmail.com>
1098 * Makefile.am: Remove i370 support.
1099 * configure.ac: Likewise.
1100 * disassemble.c: Likewise.
1101 * disassemble.h: Likewise.
1102 * i370-dis.c: Delete.
1103 * i370-opc.c: Delete.
1104 * Makefile.in: Regenerate.
1105 * configure: Regenerate.
1106 * po/POTFILES.in: Regenerate.
1108 2018-04-16 Alan Modra <amodra@gmail.com>
1110 * Makefile.am: Remove h8500 support.
1111 * configure.ac: Likewise.
1112 * disassemble.c: Likewise.
1113 * disassemble.h: Likewise.
1114 * h8500-dis.c: Delete.
1115 * h8500-opc.h: Delete.
1116 * Makefile.in: Regenerate.
1117 * configure: Regenerate.
1118 * po/POTFILES.in: Regenerate.
1120 2018-04-16 Alan Modra <amodra@gmail.com>
1122 * configure.ac: Remove tahoe support.
1123 * configure: Regenerate.
1125 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1127 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1129 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1131 * i386-tbl.h: Regenerated.
1133 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1135 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1136 PREFIX_MOD_1_0FAE_REG_6.
1138 (OP_E_register): Use va_mode.
1139 * i386-dis-evex.h (prefix_table):
1140 New instructions (see prefixes above).
1141 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1142 (cpu_flags): Likewise.
1143 * i386-opc.h (enum): Likewise.
1144 (i386_cpu_flags): Likewise.
1145 * i386-opc.tbl: Add umonitor, umwait, tpause.
1146 * i386-init.h: Regenerate.
1147 * i386-tbl.h: Likewise.
1149 2018-04-11 Alan Modra <amodra@gmail.com>
1151 * opcodes/i860-dis.c: Delete.
1152 * opcodes/i960-dis.c: Delete.
1153 * Makefile.am: Remove i860 and i960 support.
1154 * configure.ac: Likewise.
1155 * disassemble.c: Likewise.
1156 * disassemble.h: Likewise.
1157 * Makefile.in: Regenerate.
1158 * configure: Regenerate.
1159 * po/POTFILES.in: Regenerate.
1161 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1164 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1166 (print_insn): Clear vex instead of vex.evex.
1168 2018-04-04 Nick Clifton <nickc@redhat.com>
1170 * po/es.po: Updated Spanish translation.
1172 2018-03-28 Jan Beulich <jbeulich@suse.com>
1174 * i386-gen.c (opcode_modifiers): Delete VecESize.
1175 * i386-opc.h (VecESize): Delete.
1176 (struct i386_opcode_modifier): Delete vecesize.
1177 * i386-opc.tbl: Drop VecESize.
1178 * i386-tlb.h: Re-generate.
1180 2018-03-28 Jan Beulich <jbeulich@suse.com>
1182 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1183 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1184 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1185 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1186 * i386-tlb.h: Re-generate.
1188 2018-03-28 Jan Beulich <jbeulich@suse.com>
1190 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1192 * i386-tlb.h: Re-generate.
1194 2018-03-28 Jan Beulich <jbeulich@suse.com>
1196 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1197 (vex_len_table): Drop Y for vcvt*2si.
1198 (putop): Replace plain 'Y' handling by abort().
1200 2018-03-28 Nick Clifton <nickc@redhat.com>
1203 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1204 instructions with only a base address register.
1205 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1206 handle AARHC64_OPND_SVE_ADDR_R.
1207 (aarch64_print_operand): Likewise.
1208 * aarch64-asm-2.c: Regenerate.
1209 * aarch64_dis-2.c: Regenerate.
1210 * aarch64-opc-2.c: Regenerate.
1212 2018-03-22 Jan Beulich <jbeulich@suse.com>
1214 * i386-opc.tbl: Drop VecESize from register only insn forms and
1215 memory forms not allowing broadcast.
1216 * i386-tlb.h: Re-generate.
1218 2018-03-22 Jan Beulich <jbeulich@suse.com>
1220 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1221 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1222 sha256*): Drop Disp<N>.
1224 2018-03-22 Jan Beulich <jbeulich@suse.com>
1226 * i386-dis.c (EbndS, bnd_swap_mode): New.
1227 (prefix_table): Use EbndS.
1228 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1229 * i386-opc.tbl (bndmov): Move misplaced Load.
1230 * i386-tlb.h: Re-generate.
1232 2018-03-22 Jan Beulich <jbeulich@suse.com>
1234 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1235 templates allowing memory operands and folded ones for register
1237 * i386-tlb.h: Re-generate.
1239 2018-03-22 Jan Beulich <jbeulich@suse.com>
1241 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1242 256-bit templates. Drop redundant leftover Disp<N>.
1243 * i386-tlb.h: Re-generate.
1245 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1247 * riscv-opc.c (riscv_insn_types): New.
1249 2018-03-13 Nick Clifton <nickc@redhat.com>
1251 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1253 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1255 * i386-opc.tbl: Add Optimize to clr.
1256 * i386-tbl.h: Regenerated.
1258 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1260 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1261 * i386-opc.h (OldGcc): Removed.
1262 (i386_opcode_modifier): Remove oldgcc.
1263 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1264 instructions for old (<= 2.8.1) versions of gcc.
1265 * i386-tbl.h: Regenerated.
1267 2018-03-08 Jan Beulich <jbeulich@suse.com>
1269 * i386-opc.h (EVEXDYN): New.
1270 * i386-opc.tbl: Fold various AVX512VL templates.
1271 * i386-tlb.h: Re-generate.
1273 2018-03-08 Jan Beulich <jbeulich@suse.com>
1275 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1276 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1277 vpexpandd, vpexpandq): Fold AFX512VF templates.
1278 * i386-tlb.h: Re-generate.
1280 2018-03-08 Jan Beulich <jbeulich@suse.com>
1282 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1283 Fold 128- and 256-bit VEX-encoded templates.
1284 * i386-tlb.h: Re-generate.
1286 2018-03-08 Jan Beulich <jbeulich@suse.com>
1288 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1289 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1290 vpexpandd, vpexpandq): Fold AVX512F templates.
1291 * i386-tlb.h: Re-generate.
1293 2018-03-08 Jan Beulich <jbeulich@suse.com>
1295 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1296 64-bit templates. Drop Disp<N>.
1297 * i386-tlb.h: Re-generate.
1299 2018-03-08 Jan Beulich <jbeulich@suse.com>
1301 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1302 and 256-bit templates.
1303 * i386-tlb.h: Re-generate.
1305 2018-03-08 Jan Beulich <jbeulich@suse.com>
1307 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1308 * i386-tlb.h: Re-generate.
1310 2018-03-08 Jan Beulich <jbeulich@suse.com>
1312 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1314 * i386-tlb.h: Re-generate.
1316 2018-03-08 Jan Beulich <jbeulich@suse.com>
1318 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1319 * i386-tlb.h: Re-generate.
1321 2018-03-08 Jan Beulich <jbeulich@suse.com>
1323 * i386-gen.c (opcode_modifiers): Delete FloatD.
1324 * i386-opc.h (FloatD): Delete.
1325 (struct i386_opcode_modifier): Delete floatd.
1326 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1328 * i386-tlb.h: Re-generate.
1330 2018-03-08 Jan Beulich <jbeulich@suse.com>
1332 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1334 2018-03-08 Jan Beulich <jbeulich@suse.com>
1336 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1337 * i386-tlb.h: Re-generate.
1339 2018-03-08 Jan Beulich <jbeulich@suse.com>
1341 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1343 * i386-tlb.h: Re-generate.
1345 2018-03-07 Alan Modra <amodra@gmail.com>
1347 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1349 * disassemble.h (print_insn_rs6000): Delete.
1350 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1351 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1352 (print_insn_rs6000): Delete.
1354 2018-03-03 Alan Modra <amodra@gmail.com>
1356 * sysdep.h (opcodes_error_handler): Define.
1357 (_bfd_error_handler): Declare.
1358 * Makefile.am: Remove stray #.
1359 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1361 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1362 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1363 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1364 opcodes_error_handler to print errors. Standardize error messages.
1365 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1366 and include opintl.h.
1367 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1368 * i386-gen.c: Standardize error messages.
1369 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1370 * Makefile.in: Regenerate.
1371 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1372 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1373 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1374 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1375 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1376 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1377 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1378 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1379 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1380 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1381 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1382 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1383 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1385 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1387 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1388 vpsub[bwdq] instructions.
1389 * i386-tbl.h: Regenerated.
1391 2018-03-01 Alan Modra <amodra@gmail.com>
1393 * configure.ac (ALL_LINGUAS): Sort.
1394 * configure: Regenerate.
1396 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1398 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1399 macro by assignements.
1401 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1404 * i386-gen.c (opcode_modifiers): Add Optimize.
1405 * i386-opc.h (Optimize): New enum.
1406 (i386_opcode_modifier): Add optimize.
1407 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1408 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1409 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1410 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1411 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1413 * i386-tbl.h: Regenerated.
1415 2018-02-26 Alan Modra <amodra@gmail.com>
1417 * crx-dis.c (getregliststring): Allocate a large enough buffer
1418 to silence false positive gcc8 warning.
1420 2018-02-22 Shea Levy <shea@shealevy.com>
1422 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1424 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1426 * i386-opc.tbl: Add {rex},
1427 * i386-tbl.h: Regenerated.
1429 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1431 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1432 (mips16_opcodes): Replace `M' with `m' for "restore".
1434 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1436 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1438 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1440 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1441 variable to `function_index'.
1443 2018-02-13 Nick Clifton <nickc@redhat.com>
1446 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1447 about truncation of printing.
1449 2018-02-12 Henry Wong <henry@stuffedcow.net>
1451 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1453 2018-02-05 Nick Clifton <nickc@redhat.com>
1455 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1457 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1459 * i386-dis.c (enum): Add pconfig.
1460 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1461 (cpu_flags): Add CpuPCONFIG.
1462 * i386-opc.h (enum): Add CpuPCONFIG.
1463 (i386_cpu_flags): Add cpupconfig.
1464 * i386-opc.tbl: Add PCONFIG instruction.
1465 * i386-init.h: Regenerate.
1466 * i386-tbl.h: Likewise.
1468 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1470 * i386-dis.c (enum): Add PREFIX_0F09.
1471 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1472 (cpu_flags): Add CpuWBNOINVD.
1473 * i386-opc.h (enum): Add CpuWBNOINVD.
1474 (i386_cpu_flags): Add cpuwbnoinvd.
1475 * i386-opc.tbl: Add WBNOINVD instruction.
1476 * i386-init.h: Regenerate.
1477 * i386-tbl.h: Likewise.
1479 2018-01-17 Jim Wilson <jimw@sifive.com>
1481 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1483 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1485 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1486 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1487 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1488 (cpu_flags): Add CpuIBT, CpuSHSTK.
1489 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1490 (i386_cpu_flags): Add cpuibt, cpushstk.
1491 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1492 * i386-init.h: Regenerate.
1493 * i386-tbl.h: Likewise.
1495 2018-01-16 Nick Clifton <nickc@redhat.com>
1497 * po/pt_BR.po: Updated Brazilian Portugese translation.
1498 * po/de.po: Updated German translation.
1500 2018-01-15 Jim Wilson <jimw@sifive.com>
1502 * riscv-opc.c (match_c_nop): New.
1503 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1505 2018-01-15 Nick Clifton <nickc@redhat.com>
1507 * po/uk.po: Updated Ukranian translation.
1509 2018-01-13 Nick Clifton <nickc@redhat.com>
1511 * po/opcodes.pot: Regenerated.
1513 2018-01-13 Nick Clifton <nickc@redhat.com>
1515 * configure: Regenerate.
1517 2018-01-13 Nick Clifton <nickc@redhat.com>
1519 2.30 branch created.
1521 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1523 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1524 * i386-tbl.h: Regenerate.
1526 2018-01-10 Jan Beulich <jbeulich@suse.com>
1528 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1529 * i386-tbl.h: Re-generate.
1531 2018-01-10 Jan Beulich <jbeulich@suse.com>
1533 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1534 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1535 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1536 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1537 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1538 Disp8MemShift of AVX512VL forms.
1539 * i386-tbl.h: Re-generate.
1541 2018-01-09 Jim Wilson <jimw@sifive.com>
1543 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1544 then the hi_addr value is zero.
1546 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1548 * arm-dis.c (arm_opcodes): Add csdb.
1549 (thumb32_opcodes): Add csdb.
1551 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1553 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1554 * aarch64-asm-2.c: Regenerate.
1555 * aarch64-dis-2.c: Regenerate.
1556 * aarch64-opc-2.c: Regenerate.
1558 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1561 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1562 Remove AVX512 vmovd with 64-bit operands.
1563 * i386-tbl.h: Regenerated.
1565 2018-01-05 Jim Wilson <jimw@sifive.com>
1567 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1570 2018-01-03 Alan Modra <amodra@gmail.com>
1572 Update year range in copyright notice of all files.
1574 2018-01-02 Jan Beulich <jbeulich@suse.com>
1576 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1577 and OPERAND_TYPE_REGZMM entries.
1579 For older changes see ChangeLog-2017
1581 Copyright (C) 2018 Free Software Foundation, Inc.
1583 Copying and distribution of this file, with or without modification,
1584 are permitted in any medium without royalty provided the copyright
1585 notice and this notice are preserved.
1591 version-control: never