opcodes/ChangeLog

   1 2019-07-01  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
   4         Disp8MemShift from register only templates.
   5         * i386-tbl.h: Re-generate.
   6
   7 2019-07-01  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
  10         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
  11         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
  12         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
  13         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
  14         EVEX_W_0F11_P_3_M_1): Delete.
  15         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
  16         EVEX_W_0F11_P_3): New.
  17         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
  18         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
  19         MOD_EVEX_0F11_PREFIX_3 table entries.
  20         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
  21         PREFIX_EVEX_0F11 table entries.
  22         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
  23         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
  24         EVEX_W_0F11_P_3_M_{0,1} table entries.
  25
  26 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
  29         Delete.
  30
  31 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
  32
  33         PR binutils/24719
  34         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
  35         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
  36         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
  37         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
  38         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
  39         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
  40         EVEX_LEN_0F38C7_R_6_P_2_W_1.
  41         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
  42         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
  43         PREFIX_EVEX_0F38C6_REG_6 entries.
  44         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
  45         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
  46         EVEX_W_0F38C7_R_6_P_2 entries.
  47         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
  48         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
  49         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
  50         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
  51         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
  52         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
  53         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
  54
  55 2019-06-27  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
  58         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
  59         VEX_LEN_0F2D_P_3): Delete.
  60         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
  61         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
  62         (prefix_table): ... here.
  63
  64 2019-06-27  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-dis.c (Iq): Delete.
  67         (Id): New.
  68         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
  69         TBM insns.
  70         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
  71         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
  72         (OP_E_memory): Also honor needindex when deciding whether an
  73         address size prefix needs printing.
  74         (OP_I): Remove handling of q_mode. Add handling of d_mode.
  75
  76 2019-06-26  Jim Wilson  <jimw@sifive.com>
  77
  78         PR binutils/24739
  79         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
  80         Set info->display_endian to info->endian_code.
  81
  82 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
  85         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
  86         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
  87         OPERAND_TYPE_ACC64 entries.
  88         * i386-init.h: Re-generate.
  89
  90 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
  93         Delete.
  94         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
  95         of dqa_mode.
  96         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
  97         entries here.
  98         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
  99         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 100
 101 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 102
 103         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 104         variables.
 105
 106 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 107
 108         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 109         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 110         movnti.
 111         * i386-opc.tbl (movnti): Add IgnoreSize.
 112         * i386-tbl.h: Re-generate.
 113
 114 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 117         * i386-tbl.h: Re-generate.
 118
 119 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         * i386-dis-evex.h: Break into ...
 122         * i386-dis-evex-len.h: New file.
 123         * i386-dis-evex-mod.h: Likewise.
 124         * i386-dis-evex-prefix.h: Likewise.
 125         * i386-dis-evex-reg.h: Likewise.
 126         * i386-dis-evex-w.h: Likewise.
 127         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 128         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 129         i386-dis-evex-mod.h.
 130
 131 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 132
 133         PR binutils/24700
 134         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 135         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 136         EVEX_W_0F385B_P_2.
 137         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 138         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 139         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 140         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 141         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 142         EVEX_LEN_0F385B_P_2_W_1.
 143         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 144         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 145         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 146         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 147         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 148         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 149         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 150         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 151         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 152         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 153
 154 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         PR binutils/24691
 157         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 158         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 159         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 160         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 161         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 162         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 163         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 164         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 165         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 166         EVEX_LEN_0F3A43_P_2_W_1.
 167         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 168         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 169         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 170         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 171         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 172         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 173         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 174         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 175         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 176         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 177         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 178         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 179
 180 2019-06-14  Nick Clifton  <nickc@redhat.com>
 181
 182         * po/fr.po; Updated French translation.
 183
 184 2019-06-13  Stafford Horne  <shorne@gmail.com>
 185
 186         * or1k-asm.c: Regenerated.
 187         * or1k-desc.c: Regenerated.
 188         * or1k-desc.h: Regenerated.
 189         * or1k-dis.c: Regenerated.
 190         * or1k-ibld.c: Regenerated.
 191         * or1k-opc.c: Regenerated.
 192         * or1k-opc.h: Regenerated.
 193         * or1k-opinst.c: Regenerated.
 194
 195 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 196
 197         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 198
 199 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 200
 201         PR binutils/24633
 202         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 203         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 204         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 205         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 206         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 207         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 208         EVEX_LEN_0F3A1B_P_2_W_1.
 209         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 210         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 211         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 212         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 213         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 214         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 215         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 216         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 217
 218 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 219
 220         PR binutils/24626
 221         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 222         EVEX.vvvv when disassembling VEX and EVEX instructions.
 223         (OP_VEX): Set vex.register_specifier to 0 after readding
 224         vex.register_specifier.
 225         (OP_Vex_2src_1): Likewise.
 226         (OP_Vex_2src_2): Likewise.
 227         (OP_LWP_E): Likewise.
 228         (OP_EX_Vex): Don't check vex.register_specifier.
 229         (OP_XMM_Vex): Likewise.
 230
 231 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 232             Lili Cui  <lili.cui@intel.com>
 233
 234         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 235         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 236         instructions.
 237         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 238         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 239         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 240         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 241         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 242         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 243         * i386-init.h: Regenerated.
 244         * i386-tbl.h: Likewise.
 245
 246 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 247             Lili Cui  <lili.cui@intel.com>
 248
 249         * doc/c-i386.texi: Document enqcmd.
 250         * testsuite/gas/i386/enqcmd-intel.d: New file.
 251         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 252         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 253         * testsuite/gas/i386/enqcmd.d: Likewise.
 254         * testsuite/gas/i386/enqcmd.s: Likewise.
 255         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 256         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 257         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 258         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 259         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 260         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 261         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 262         and x86-64-enqcmd.
 263
 264 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 265
 266         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 267
 268 2019-06-03  Alan Modra  <amodra@gmail.com>
 269
 270         * ppc-dis.c (prefix_opcd_indices): Correct size.
 271
 272 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 273
 274         PR gas/24625
 275         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 276         Disp8ShiftVL.
 277         * i386-tbl.h: Regenerated.
 278
 279 2019-05-24  Alan Modra  <amodra@gmail.com>
 280
 281         * po/POTFILES.in: Regenerate.
 282
 283 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 284             Alan Modra  <amodra@gmail.com>
 285
 286         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 287         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 288         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 289         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 290         XTOP>): Define and add entries.
 291         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 292         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 293         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 294         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 295
 296 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 297             Alan Modra  <amodra@gmail.com>
 298
 299         * ppc-dis.c (ppc_opts): Add "future" entry.
 300         (PREFIX_OPCD_SEGS): Define.
 301         (prefix_opcd_indices): New array.
 302         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 303         (lookup_prefix): New function.
 304         (print_insn_powerpc): Handle 64-bit prefix instructions.
 305         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 306         (PMRR, POWERXX): Define.
 307         (prefix_opcodes): New instruction table.
 308         (prefix_num_opcodes): New constant.
 309
 310 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 311
 312         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 313         * configure: Regenerated.
 314         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 315         and cpu/bpf.opc.
 316         (HFILES): Add bpf-desc.h and bpf-opc.h.
 317         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 318         bpf-ibld.c and bpf-opc.c.
 319         (BPF_DEPS): Define.
 320         * Makefile.in: Regenerated.
 321         * disassemble.c (ARCH_bpf): Define.
 322         (disassembler): Add case for bfd_arch_bpf.
 323         (disassemble_init_for_target): Likewise.
 324         (enum epbf_isa_attr): Define.
 325         * disassemble.h: extern print_insn_bpf.
 326         * bpf-asm.c: Generated.
 327         * bpf-opc.h: Likewise.
 328         * bpf-opc.c: Likewise.
 329         * bpf-ibld.c: Likewise.
 330         * bpf-dis.c: Likewise.
 331         * bpf-desc.h: Likewise.
 332         * bpf-desc.c: Likewise.
 333
 334 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 335
 336         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 337         and VMSR with the new operands.
 338
 339 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 340
 341         * arm-dis.c (enum mve_instructions): New enum
 342         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 343         and cneg.
 344         (mve_opcodes): New instructions as above.
 345         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 346         csneg and csel.
 347         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 348
 349 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 350
 351         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 352         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 353         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 354         uqshl, urshrl and urshr.
 355         (is_mve_okay_in_it): Add new instructions to TRUE list.
 356         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 357         (print_insn_mve): Updated to accept new %j,
 358         %<bitfield>m and %<bitfield>n patterns.
 359
 360 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 361
 362         * mips-opc.c (mips_builtin_opcodes): Change source register
 363         constraint for DAUI.
 364
 365 2019-05-20  Nick Clifton  <nickc@redhat.com>
 366
 367         * po/fr.po: Updated French translation.
 368
 369 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 370             Michael Collison <michael.collison@arm.com>
 371
 372         * arm-dis.c (thumb32_opcodes): Add new instructions.
 373         (enum mve_instructions): Likewise.
 374         (enum mve_undefined): Add new reasons.
 375         (is_mve_encoding_conflict): Handle new instructions.
 376         (is_mve_undefined): Likewise.
 377         (is_mve_unpredictable): Likewise.
 378         (print_mve_undefined): Likewise.
 379         (print_mve_size): Likewise.
 380
 381 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 382             Michael Collison <michael.collison@arm.com>
 383
 384         * arm-dis.c (thumb32_opcodes): Add new instructions.
 385         (enum mve_instructions): Likewise.
 386         (is_mve_encoding_conflict): Handle new instructions.
 387         (is_mve_undefined): Likewise.
 388         (is_mve_unpredictable): Likewise.
 389         (print_mve_size): Likewise.
 390
 391 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 392             Michael Collison <michael.collison@arm.com>
 393
 394         * arm-dis.c (thumb32_opcodes): Add new instructions.
 395         (enum mve_instructions): Likewise.
 396         (is_mve_encoding_conflict): Likewise.
 397         (is_mve_unpredictable): Likewise.
 398         (print_mve_size): Likewise.
 399
 400 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 401             Michael Collison <michael.collison@arm.com>
 402
 403         * arm-dis.c (thumb32_opcodes): Add new instructions.
 404         (enum mve_instructions): Likewise.
 405         (is_mve_encoding_conflict): Handle new instructions.
 406         (is_mve_undefined): Likewise.
 407         (is_mve_unpredictable): Likewise.
 408         (print_mve_size): Likewise.
 409
 410 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 411             Michael Collison <michael.collison@arm.com>
 412
 413         * arm-dis.c (thumb32_opcodes): Add new instructions.
 414         (enum mve_instructions): Likewise.
 415         (is_mve_encoding_conflict): Handle new instructions.
 416         (is_mve_undefined): Likewise.
 417         (is_mve_unpredictable): Likewise.
 418         (print_mve_size): Likewise.
 419         (print_insn_mve): Likewise.
 420
 421 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 422             Michael Collison <michael.collison@arm.com>
 423
 424         * arm-dis.c (thumb32_opcodes): Add new instructions.
 425         (print_insn_thumb32): Handle new instructions.
 426
 427 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 428             Michael Collison <michael.collison@arm.com>
 429
 430         * arm-dis.c (enum mve_instructions): Add new instructions.
 431         (enum mve_undefined): Add new reasons.
 432         (is_mve_encoding_conflict): Handle new instructions.
 433         (is_mve_undefined): Likewise.
 434         (is_mve_unpredictable): Likewise.
 435         (print_mve_undefined): Likewise.
 436         (print_mve_size): Likewise.
 437         (print_mve_shift_n): Likewise.
 438         (print_insn_mve): Likewise.
 439
 440 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 441             Michael Collison <michael.collison@arm.com>
 442
 443         * arm-dis.c (enum mve_instructions): Add new instructions.
 444         (is_mve_encoding_conflict): Handle new instructions.
 445         (is_mve_unpredictable): Likewise.
 446         (print_mve_rotate): Likewise.
 447         (print_mve_size): Likewise.
 448         (print_insn_mve): Likewise.
 449
 450 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 451             Michael Collison <michael.collison@arm.com>
 452
 453         * arm-dis.c (enum mve_instructions): Add new instructions.
 454         (is_mve_encoding_conflict): Handle new instructions.
 455         (is_mve_unpredictable): Likewise.
 456         (print_mve_size): Likewise.
 457         (print_insn_mve): Likewise.
 458
 459 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 460             Michael Collison <michael.collison@arm.com>
 461
 462         * arm-dis.c (enum mve_instructions): Add new instructions.
 463         (enum mve_undefined): Add new reasons.
 464         (is_mve_encoding_conflict): Handle new instructions.
 465         (is_mve_undefined): Likewise.
 466         (is_mve_unpredictable): Likewise.
 467         (print_mve_undefined): Likewise.
 468         (print_mve_size): Likewise.
 469         (print_insn_mve): Likewise.
 470
 471 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 472             Michael Collison <michael.collison@arm.com>
 473
 474         * arm-dis.c (enum mve_instructions): Add new instructions.
 475         (is_mve_encoding_conflict): Handle new instructions.
 476         (is_mve_undefined): Likewise.
 477         (is_mve_unpredictable): Likewise.
 478         (print_mve_size): Likewise.
 479         (print_insn_mve): Likewise.
 480
 481 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 482             Michael Collison <michael.collison@arm.com>
 483
 484         * arm-dis.c (enum mve_instructions): Add new instructions.
 485         (enum mve_unpredictable): Add new reasons.
 486         (enum mve_undefined): Likewise.
 487         (is_mve_okay_in_it): Handle new isntructions.
 488         (is_mve_encoding_conflict): Likewise.
 489         (is_mve_undefined): Likewise.
 490         (is_mve_unpredictable): Likewise.
 491         (print_mve_vmov_index): Likewise.
 492         (print_simd_imm8): Likewise.
 493         (print_mve_undefined): Likewise.
 494         (print_mve_unpredictable): Likewise.
 495         (print_mve_size): Likewise.
 496         (print_insn_mve): Likewise.
 497
 498 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 499             Michael Collison <michael.collison@arm.com>
 500
 501         * arm-dis.c (enum mve_instructions): Add new instructions.
 502         (enum mve_unpredictable): Add new reasons.
 503         (enum mve_undefined): Likewise.
 504         (is_mve_encoding_conflict): Handle new instructions.
 505         (is_mve_undefined): Likewise.
 506         (is_mve_unpredictable): Likewise.
 507         (print_mve_undefined): Likewise.
 508         (print_mve_unpredictable): Likewise.
 509         (print_mve_rounding_mode): Likewise.
 510         (print_mve_vcvt_size): Likewise.
 511         (print_mve_size): Likewise.
 512         (print_insn_mve): Likewise.
 513
 514 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 515             Michael Collison <michael.collison@arm.com>
 516
 517         * arm-dis.c (enum mve_instructions): Add new instructions.
 518         (enum mve_unpredictable): Add new reasons.
 519         (enum mve_undefined): Likewise.
 520         (is_mve_undefined): Handle new instructions.
 521         (is_mve_unpredictable): Likewise.
 522         (print_mve_undefined): Likewise.
 523         (print_mve_unpredictable): Likewise.
 524         (print_mve_size): Likewise.
 525         (print_insn_mve): Likewise.
 526
 527 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 528             Michael Collison <michael.collison@arm.com>
 529
 530         * arm-dis.c (enum mve_instructions): Add new instructions.
 531         (enum mve_undefined): Add new reasons.
 532         (insns): Add new instructions.
 533         (is_mve_encoding_conflict):
 534         (print_mve_vld_str_addr): New print function.
 535         (is_mve_undefined): Handle new instructions.
 536         (is_mve_unpredictable): Likewise.
 537         (print_mve_undefined): Likewise.
 538         (print_mve_size): Likewise.
 539         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 540         (print_insn_mve):  Handle new operands.
 541
 542 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 543             Michael Collison <michael.collison@arm.com>
 544
 545         * arm-dis.c (enum mve_instructions): Add new instructions.
 546         (enum mve_unpredictable): Add new reasons.
 547         (is_mve_encoding_conflict): Handle new instructions.
 548         (is_mve_unpredictable): Likewise.
 549         (mve_opcodes): Add new instructions.
 550         (print_mve_unpredictable): Handle new reasons.
 551         (print_mve_register_blocks): New print function.
 552         (print_mve_size): Handle new instructions.
 553         (print_insn_mve): Likewise.
 554
 555 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 556             Michael Collison <michael.collison@arm.com>
 557
 558         * arm-dis.c (enum mve_instructions): Add new instructions.
 559         (enum mve_unpredictable): Add new reasons.
 560         (enum mve_undefined): Likewise.
 561         (is_mve_encoding_conflict): Handle new instructions.
 562         (is_mve_undefined): Likewise.
 563         (is_mve_unpredictable): Likewise.
 564         (coprocessor_opcodes): Move NEON VDUP from here...
 565         (neon_opcodes): ... to here.
 566         (mve_opcodes): Add new instructions.
 567         (print_mve_undefined):  Handle new reasons.
 568         (print_mve_unpredictable): Likewise.
 569         (print_mve_size): Handle new instructions.
 570         (print_insn_neon): Handle vdup.
 571         (print_insn_mve): Handle new operands.
 572
 573 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 574             Michael Collison <michael.collison@arm.com>
 575
 576         * arm-dis.c (enum mve_instructions): Add new instructions.
 577         (enum mve_unpredictable): Add new values.
 578         (mve_opcodes): Add new instructions.
 579         (vec_condnames): New array with vector conditions.
 580         (mve_predicatenames): New array with predicate suffixes.
 581         (mve_vec_sizename): New array with vector sizes.
 582         (enum vpt_pred_state): New enum with vector predication states.
 583         (struct vpt_block): New struct type for vpt blocks.
 584         (vpt_block_state): Global struct to keep track of state.
 585         (mve_extract_pred_mask): New helper function.
 586         (num_instructions_vpt_block): Likewise.
 587         (mark_outside_vpt_block): Likewise.
 588         (mark_inside_vpt_block): Likewise.
 589         (invert_next_predicate_state): Likewise.
 590         (update_next_predicate_state): Likewise.
 591         (update_vpt_block_state): Likewise.
 592         (is_vpt_instruction): Likewise.
 593         (is_mve_encoding_conflict): Add entries for new instructions.
 594         (is_mve_unpredictable): Likewise.
 595         (print_mve_unpredictable): Handle new cases.
 596         (print_instruction_predicate): Likewise.
 597         (print_mve_size): New function.
 598         (print_vec_condition): New function.
 599         (print_insn_mve): Handle vpt blocks and new print operands.
 600
 601 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 602
 603         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 604         8, 14 and 15 for Armv8.1-M Mainline.
 605
 606 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 607             Michael Collison <michael.collison@arm.com>
 608
 609         * arm-dis.c (enum mve_instructions): New enum.
 610         (enum mve_unpredictable): Likewise.
 611         (enum mve_undefined): Likewise.
 612         (struct mopcode32): New struct.
 613         (is_mve_okay_in_it): New function.
 614         (is_mve_architecture): Likewise.
 615         (arm_decode_field): Likewise.
 616         (arm_decode_field_multiple): Likewise.
 617         (is_mve_encoding_conflict): Likewise.
 618         (is_mve_undefined): Likewise.
 619         (is_mve_unpredictable): Likewise.
 620         (print_mve_undefined): Likewise.
 621         (print_mve_unpredictable): Likewise.
 622         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 623         (print_insn_mve): New function.
 624         (print_insn_thumb32): Handle MVE architecture.
 625         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 626
 627 2019-05-10  Nick Clifton  <nickc@redhat.com>
 628
 629         PR 24538
 630         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 631         end of the table prematurely.
 632
 633 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 634
 635         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 636         macros for R6.
 637
 638 2019-05-11  Alan Modra  <amodra@gmail.com>
 639
 640         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 641         when -Mraw is in effect.
 642
 643 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 644
 645         * aarch64-dis-2.c: Regenerate.
 646         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 647         (OP_SVE_BBB): New variant set.
 648         (OP_SVE_DDDD): New variant set.
 649         (OP_SVE_HHH): New variant set.
 650         (OP_SVE_HHHU): New variant set.
 651         (OP_SVE_SSS): New variant set.
 652         (OP_SVE_SSSU): New variant set.
 653         (OP_SVE_SHH): New variant set.
 654         (OP_SVE_SBBU): New variant set.
 655         (OP_SVE_DSS): New variant set.
 656         (OP_SVE_DHHU): New variant set.
 657         (OP_SVE_VMV_HSD_BHS): New variant set.
 658         (OP_SVE_VVU_HSD_BHS): New variant set.
 659         (OP_SVE_VVVU_SD_BH): New variant set.
 660         (OP_SVE_VVVU_BHSD): New variant set.
 661         (OP_SVE_VVV_QHD_DBS): New variant set.
 662         (OP_SVE_VVV_HSD_BHS): New variant set.
 663         (OP_SVE_VVV_HSD_BHS2): New variant set.
 664         (OP_SVE_VVV_BHS_HSD): New variant set.
 665         (OP_SVE_VV_BHS_HSD): New variant set.
 666         (OP_SVE_VVV_SD): New variant set.
 667         (OP_SVE_VVU_BHS_HSD): New variant set.
 668         (OP_SVE_VZVV_SD): New variant set.
 669         (OP_SVE_VZVV_BH): New variant set.
 670         (OP_SVE_VZV_SD): New variant set.
 671         (aarch64_opcode_table): Add sve2 instructions.
 672
 673 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 674
 675         * aarch64-asm-2.c: Regenerated.
 676         * aarch64-dis-2.c: Regenerated.
 677         * aarch64-opc-2.c: Regenerated.
 678         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 679         for SVE_SHLIMM_UNPRED_22.
 680         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 681         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 682         operand.
 683
 684 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 685
 686         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 687         sve_size_tsz_bhs iclass encode.
 688         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 689         sve_size_tsz_bhs iclass decode.
 690
 691 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 692
 693         * aarch64-asm-2.c: Regenerated.
 694         * aarch64-dis-2.c: Regenerated.
 695         * aarch64-opc-2.c: Regenerated.
 696         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 697         for SVE_Zm4_11_INDEX.
 698         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 699         (fields): Handle SVE_i2h field.
 700         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 701         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 702
 703 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 704
 705         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 706         sve_shift_tsz_bhsd iclass encode.
 707         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 708         sve_shift_tsz_bhsd iclass decode.
 709
 710 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 711
 712         * aarch64-asm-2.c: Regenerated.
 713         * aarch64-dis-2.c: Regenerated.
 714         * aarch64-opc-2.c: Regenerated.
 715         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 716         (aarch64_encode_variant_using_iclass): Handle
 717         sve_shift_tsz_hsd iclass encode.
 718         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 719         sve_shift_tsz_hsd iclass decode.
 720         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 721         for SVE_SHRIMM_UNPRED_22.
 722         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 723         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 724         operand.
 725
 726 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 727
 728         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 729         sve_size_013 iclass encode.
 730         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 731         sve_size_013 iclass decode.
 732
 733 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 734
 735         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 736         sve_size_bh iclass encode.
 737         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 738         sve_size_bh iclass decode.
 739
 740 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 741
 742         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 743         sve_size_sd2 iclass encode.
 744         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 745         sve_size_sd2 iclass decode.
 746         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 747         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 748
 749 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 750
 751         * aarch64-asm-2.c: Regenerated.
 752         * aarch64-dis-2.c: Regenerated.
 753         * aarch64-opc-2.c: Regenerated.
 754         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 755         for SVE_ADDR_ZX.
 756         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 757         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 758
 759 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 760
 761         * aarch64-asm-2.c: Regenerated.
 762         * aarch64-dis-2.c: Regenerated.
 763         * aarch64-opc-2.c: Regenerated.
 764         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 765         for SVE_Zm3_11_INDEX.
 766         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 767         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 768         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 769         fields.
 770         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 771
 772 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 773
 774         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 775         sve_size_hsd2 iclass encode.
 776         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 777         sve_size_hsd2 iclass decode.
 778         * aarch64-opc.c (fields): Handle SVE_size field.
 779         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 780
 781 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 782
 783         * aarch64-asm-2.c: Regenerated.
 784         * aarch64-dis-2.c: Regenerated.
 785         * aarch64-opc-2.c: Regenerated.
 786         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 787         for SVE_IMM_ROT3.
 788         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 789         (fields): Handle SVE_rot3 field.
 790         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 791         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 792
 793 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 794
 795         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 796         instructions.
 797
 798 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 799
 800         * aarch64-tbl.h
 801         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 802         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 803         aarch64_feature_sve2bitperm): New feature sets.
 804         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 805         for feature set addresses.
 806         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 807         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 808
 809 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 810             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 811
 812         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 813         argument and set ASE_EVA_R6 appropriately.
 814         (set_default_mips_dis_options): Pass ISA to above.
 815         (parse_mips_dis_option): Likewise.
 816         * mips-opc.c (EVAR6): New macro.
 817         (mips_builtin_opcodes): Add llwpe, scwpe.
 818
 819 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 820
 821         * aarch64-asm-2.c: Regenerated.
 822         * aarch64-dis-2.c: Regenerated.
 823         * aarch64-opc-2.c: Regenerated.
 824         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 825         AARCH64_OPND_TME_UIMM16.
 826         (aarch64_print_operand): Likewise.
 827         * aarch64-tbl.h (QL_IMM_NIL): New.
 828         (TME): New.
 829         (_TME_INSN): New.
 830         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 831
 832 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 833
 834         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 835
 836 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 837             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 838
 839         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 840
 841 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 842
 843         * s12z-opc.h: Add extern "C" bracketing to help
 844         users who wish to use this interface in c++ code.
 845
 846 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 847
 848         * s12z-opc.c (bm_decode): Handle bit map operations with the
 849         "reserved0" mode.
 850
 851 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 852
 853         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 854         specifier.  Add entries for VLDR and VSTR of system registers.
 855         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 856         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 857         of %J and %K format specifier.
 858
 859 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 860
 861         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 862         Add new entries for VSCCLRM instruction.
 863         (print_insn_coprocessor): Handle new %C format control code.
 864
 865 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 866
 867         * arm-dis.c (enum isa): New enum.
 868         (struct sopcode32): New structure.
 869         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 870         set isa field of all current entries to ANY.
 871         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 872         Only match an entry if its isa field allows the current mode.
 873
 874 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 875
 876         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 877         CLRM.
 878         (print_insn_thumb32): Add logic to print %n CLRM register list.
 879
 880 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 881
 882         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 883         and %Q patterns.
 884
 885 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 886
 887         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 888         (print_insn_thumb32): Edit the switch case for %Z.
 889
 890 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 891
 892         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 893
 894 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 895
 896         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 897
 898 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 899
 900         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 901
 902 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 903
 904         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 905         Arm register with r13 and r15 unpredictable.
 906         (thumb32_opcodes): New instructions for bfx and bflx.
 907
 908 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 909
 910         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 911
 912 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 913
 914         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 915
 916 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 917
 918         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 919
 920 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 921
 922         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 923
 924 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 925
 926         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 927         "optr". ("operator" is a reserved word in c++).
 928
 929 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 930
 931         * aarch64-opc.c (aarch64_print_operand): Add case for
 932         AARCH64_OPND_Rt_SP.
 933         (verify_constraints): Likewise.
 934         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 935         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 936         to accept Rt|SP as first operand.
 937         (AARCH64_OPERANDS): Add new Rt_SP.
 938         * aarch64-asm-2.c: Regenerated.
 939         * aarch64-dis-2.c: Regenerated.
 940         * aarch64-opc-2.c: Regenerated.
 941
 942 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 943
 944         * aarch64-asm-2.c: Regenerated.
 945         * aarch64-dis-2.c: Likewise.
 946         * aarch64-opc-2.c: Likewise.
 947         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 948
 949 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 950
 951         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 952
 953 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 954
 955         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 956         * i386-init.h: Regenerated.
 957
 958 2019-04-07  Alan Modra  <amodra@gmail.com>
 959
 960         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 961         op_separator to control printing of spaces, comma and parens
 962         rather than need_comma, need_paren and spaces vars.
 963
 964 2019-04-07  Alan Modra  <amodra@gmail.com>
 965
 966         PR 24421
 967         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 968         (print_insn_neon, print_insn_arm): Likewise.
 969
 970 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 971
 972         * i386-dis-evex.h (evex_table): Updated to support BF16
 973         instructions.
 974         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 975         and EVEX_W_0F3872_P_3.
 976         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 977         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 978         * i386-opc.h (enum): Add CpuAVX512_BF16.
 979         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 980         * i386-opc.tbl: Add AVX512 BF16 instructions.
 981         * i386-init.h: Regenerated.
 982         * i386-tbl.h: Likewise.
 983
 984 2019-04-05  Alan Modra  <amodra@gmail.com>
 985
 986         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 987         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 988         to favour printing of "-" branch hint when using the "y" bit.
 989         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 990
 991 2019-04-05  Alan Modra  <amodra@gmail.com>
 992
 993         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 994         opcode until first operand is output.
 995
 996 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 997
 998         PR gas/24349
 999         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1000         (valid_bo_post_v2): Add support for 'at' branch hints.
1001         (insert_bo): Only error on branch on ctr.
1002         (get_bo_hint_mask): New function.
1003         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1004         for inserting 'at' branch hints.
1005         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1006         for extracting 'at' branch hints.
1007         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1008         (BOE): Delete operand.
1009         (BOM, BOP): New operands.
1010         (RM): Update value.
1011         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1012         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1013         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1014         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1015         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1016         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1017         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1018         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1019         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1020         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1021         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1022         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1023         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1024         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1025         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1026         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1027         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1028         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1029         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1030         bttarl+>: New extended mnemonics.
1031
1032 2019-03-28  Alan Modra  <amodra@gmail.com>
1033
1034         PR 24390
1035         * ppc-opc.c (BTF): Define.
1036         (powerpc_opcodes): Use for mtfsb*.
1037         * ppc-dis.c (print_insn_powerpc): Print fields with both
1038         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1039
1040 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1041
1042         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1043         (mapping_symbol_for_insn): Implement new algorithm.
1044         (print_insn): Remove duplicate code.
1045
1046 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1047
1048         * aarch64-dis.c (print_insn_aarch64):
1049         Implement override.
1050
1051 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1052
1053         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1054         order.
1055
1056 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1057
1058         * aarch64-dis.c (last_stop_offset): New.
1059         (print_insn_aarch64): Use stop_offset.
1060
1061 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1062
1063         PR gas/24359
1064         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1065         CPU_ANY_AVX2_FLAGS.
1066         * i386-init.h: Regenerated.
1067
1068 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1069
1070         PR gas/24348
1071         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1072         vmovdqu16, vmovdqu32 and vmovdqu64.
1073         * i386-tbl.h: Regenerated.
1074
1075 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1076
1077         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1078         from vstrszb, vstrszh, and vstrszf.
1079
1080 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1081
1082         * s390-opc.txt: Add instruction descriptions.
1083
1084 2019-02-08  Jim Wilson  <jimw@sifive.com>
1085
1086         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1087         <bne>: Likewise.
1088
1089 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1090
1091         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1092
1093 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1094
1095         PR binutils/23212
1096         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1097         * aarch64-opc.c (verify_elem_sd): New.
1098         (fields): Add FLD_sz entr.
1099         * aarch64-tbl.h (_SIMD_INSN): New.
1100         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1101         fmulx scalar and vector by element isns.
1102
1103 2019-02-07  Nick Clifton  <nickc@redhat.com>
1104
1105         * po/sv.po: Updated Swedish translation.
1106
1107 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1108
1109         * s390-mkopc.c (main): Accept arch13 as cpu string.
1110         * s390-opc.c: Add new instruction formats and instruction opcode
1111         masks.
1112         * s390-opc.txt: Add new arch13 instructions.
1113
1114 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1115
1116         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1117         (aarch64_opcode): Change encoding for stg, stzg
1118         st2g and st2zg.
1119         * aarch64-asm-2.c: Regenerated.
1120         * aarch64-dis-2.c: Regenerated.
1121         * aarch64-opc-2.c: Regenerated.
1122
1123 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1124
1125         * aarch64-asm-2.c: Regenerated.
1126         * aarch64-dis-2.c: Likewise.
1127         * aarch64-opc-2.c: Likewise.
1128         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1129
1130 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1131             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1132
1133         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1134         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1135         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1136         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1137         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1138         case for ldstgv_indexed.
1139         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1140         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1141         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1142         * aarch64-asm-2.c: Regenerated.
1143         * aarch64-dis-2.c: Regenerated.
1144         * aarch64-opc-2.c: Regenerated.
1145
1146 2019-01-23  Nick Clifton  <nickc@redhat.com>
1147
1148         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1149
1150 2019-01-21  Nick Clifton  <nickc@redhat.com>
1151
1152         * po/de.po: Updated German translation.
1153         * po/uk.po: Updated Ukranian translation.
1154
1155 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1156         * mips-dis.c (mips_arch_choices): Fix typo in
1157         gs464, gs464e and gs264e descriptors.
1158
1159 2019-01-19  Nick Clifton  <nickc@redhat.com>
1160
1161         * configure: Regenerate.
1162         * po/opcodes.pot: Regenerate.
1163
1164 2018-06-24  Nick Clifton  <nickc@redhat.com>
1165
1166         2.32 branch created.
1167
1168 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1169
1170         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1171         if it is null.
1172         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1173         zero.
1174
1175 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1176
1177         * configure: Regenerate.
1178
1179 2019-01-07  Alan Modra  <amodra@gmail.com>
1180
1181         * configure: Regenerate.
1182         * po/POTFILES.in: Regenerate.
1183
1184 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1185
1186         * s12z-opc.c: New file.
1187         * s12z-opc.h: New file.
1188         * s12z-dis.c: Removed all code not directly related to display
1189         of instructions.  Used the interface provided by the new files
1190         instead.
1191         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1192         * Makefile.in: Regenerate.
1193         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1194         * configure: Regenerate.
1195
1196 2019-01-01  Alan Modra  <amodra@gmail.com>
1197
1198         Update year range in copyright notice of all files.
1199
1200 For older changes see ChangeLog-2018
1201 \f
1202 Copyright (C) 2019 Free Software Foundation, Inc.
1203
1204 Copying and distribution of this file, with or without modification,
1205 are permitted in any medium without royalty provided the copyright
1206 notice and this notice are preserved.
1207
1208 Local Variables:
1209 mode: change-log
1210 left-margin: 8
1211 fill-column: 74
1212 version-control: never
1213 End: