opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
   4         meaningless.
   5         * i386-tbl.h: Re-generate.
   6
   7 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
  10         * i386-tbl.h: Re-generate.
  11
  12 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
  15         * i386-tbl.h: Re-generate.
  16
  17 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
  20         * i386-tbl.h: Re-generate.
  21
  22 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
  25         (vpbroadcastw, rdpid): Drop NoRex64.
  26         * i386-tbl.h: Re-generate.
  27
  28 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
  31         store templates, adding D.
  32         * i386-tbl.h: Re-generate.
  33
  34 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
  37         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
  38         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
  39         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
  40         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
  41         Fold load and store templates where possible, adding D. Drop
  42         IgnoreSize where it was pointlessly present. Drop redundant
  43         *word.
  44         * i386-tbl.h: Re-generate.
  45
  46 2018-09-13  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
  49         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
  50         (intel_operand_size): Handle v_bndmk_mode.
  51         (OP_E_memory): Likewise. Produce (bad) when also riprel.
  52
  53 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
  54
  55         * disassemble.c (ARCH_s12z): Define if ARCH_all.
  56
  57 2018-08-31  Kito Cheng  <kito@andestech.com>
  58
  59         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
  60         compressed floating point instructions.
  61
  62 2018-08-30  Kito Cheng  <kito@andestech.com>
  63
  64         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
  65         riscv_opcode.xlen_requirement.
  66         * riscv-opc.c (riscv_opcodes): Update for struct change.
  67
  68 2018-08-29  Martin Aberg  <maberg@gaisler.com>
  69
  70         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
  71         psr (PWRPSR) instruction.
  72
  73 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  74
  75         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
  76
  77 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  78
  79         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
  80
  81 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  82
  83         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
  84         loongson3a as an alias of gs464 for compatibility.
  85         * mips-opc.c (mips_opcodes): Change Comments.
  86
  87 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  88
  89         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
  90         option.
  91         (print_mips_disassembler_options): Document -M loongson-ext.
  92         * mips-opc.c (LEXT2): New macro.
  93         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
  94
  95 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  96
  97          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
  98          descriptors.
  99          (parse_mips_ase_option): Handle -M loongson-ext option.
 100          (print_mips_disassembler_options): Document -M loongson-ext.
 101          * mips-opc.c (IL3A): Delete.
 102          * mips-opc.c (LEXT): New macro.
 103          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 104          instructions.
 105
 106 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 107
 108         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 109         descriptors.
 110         (parse_mips_ase_option): Handle -M loongson-cam option.
 111         (print_mips_disassembler_options): Document -M loongson-cam.
 112         * mips-opc.c (LCAM): New macro.
 113         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 114         instructions.
 115
 116 2018-08-21  Alan Modra  <amodra@gmail.com>
 117
 118         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 119         (skip_optional_operands): Count optional operands, and update
 120         ppc_optional_operand_value call.
 121         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 122         (extract_vlensi): Likewise.
 123         (extract_fxm): Return default value for missing optional operand.
 124         (extract_ls, extract_raq, extract_tbr): Likewise.
 125         (insert_sxl, extract_sxl): New functions.
 126         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 127         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 128         flag and extra entry.
 129         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 130         extract_sxl.
 131
 132 2018-08-20  Alan Modra  <amodra@gmail.com>
 133
 134         * sh-opc.h (MASK): Simplify.
 135
 136 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 137
 138         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 139         BM_RESERVED0 or BM_RESERVED1
 140         (bm_rel_decode, bm_n_bytes): Ditto.
 141
 142 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 143
 144         * s12z.h: Delete.
 145
 146 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 147
 148         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 149         address with the addr32 prefix and without base nor index
 150         registers.
 151
 152 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 153
 154         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 155         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 156         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 157         (cpu_flags): Add CpuCMOV and CpuFXSR.
 158         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 159         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 160         * i386-init.h: Regenerated.
 161         * i386-tbl.h: Likewise.
 162
 163 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 164
 165         * arc-regs.h: Update auxiliary registers.
 166
 167 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 168
 169         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 170         (RegIP, RegIZ): Define.
 171         * i386-reg.tbl: Adjust comments.
 172         (rip): Use Qword instead of BaseIndex. Use RegIP.
 173         (eip): Use Dword instead of BaseIndex. Use RegIP.
 174         (riz): Add Qword. Use RegIZ.
 175         (eiz): Add Dword. Use RegIZ.
 176         * i386-tbl.h: Re-generate.
 177
 178 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 181         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 182         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 183         * i386-tbl.h: Re-generate.
 184
 185 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-gen.c (operand_types): Remove Mem field.
 188         * i386-opc.h (union i386_operand_type): Remove mem field.
 189         * i386-init.h, i386-tbl.h: Re-generate.
 190
 191 2018-08-01  Alan Modra  <amodra@gmail.com>
 192
 193         * po/POTFILES.in: Regenerate.
 194
 195 2018-07-31  Nick Clifton  <nickc@redhat.com>
 196
 197         * po/sv.po: Updated Swedish translation.
 198
 199 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 202         * i386-init.h, i386-tbl.h: Re-generate.
 203
 204 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 205
 206         * i386-opc.h (ZEROING_MASKING) Rename to ...
 207         (DYNAMIC_MASKING): ... this. Adjust comment.
 208         * i386-opc.tbl (MaskingMorZ): Define.
 209         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 210         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 211         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 212         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 213         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 214         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 215         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 216         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 217         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 218
 219 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-opc.tbl: Use element rather than vector size for AVX512*
 222         scatter/gather insns.
 223         * i386-tbl.h: Re-generate.
 224
 225 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 228         (cpu_flags): Drop CpuVREX.
 229         * i386-opc.h (CpuVREX): Delete.
 230         (union i386_cpu_flags): Remove cpuvrex.
 231         * i386-init.h, i386-tbl.h: Re-generate.
 232
 233 2018-07-30  Jim Wilson  <jimw@sifive.com>
 234
 235         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 236         fields.
 237         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 238
 239 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 240
 241         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 242         * Makefile.in: Regenerated.
 243         * configure.ac: Add C-SKY.
 244         * configure: Regenerated.
 245         * csky-dis.c: New file.
 246         * csky-opc.h: New file.
 247         * disassemble.c (ARCH_csky): Define.
 248         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 249         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 250
 251 2018-07-27  Alan Modra  <amodra@gmail.com>
 252
 253         * ppc-opc.c (insert_sprbat): Correct function parameter and
 254         return type.
 255         (extract_sprbat): Likewise, variable too.
 256
 257 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 258             Alan Modra  <amodra@gmail.com>
 259
 260         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 261         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 262         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 263         support disjointed BAT.
 264         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 265         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 266         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 267
 268 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 269             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 270
 271         * i386-gen.c (adjust_broadcast_modifier): New function.
 272         (process_i386_opcode_modifier): Add an argument for operands.
 273         Adjust the Broadcast value based on operands.
 274         (output_i386_opcode): Pass operand_types to
 275         process_i386_opcode_modifier.
 276         (process_i386_opcodes): Pass NULL as operands to
 277         process_i386_opcode_modifier.
 278         * i386-opc.h (BYTE_BROADCAST): New.
 279         (WORD_BROADCAST): Likewise.
 280         (DWORD_BROADCAST): Likewise.
 281         (QWORD_BROADCAST): Likewise.
 282         (i386_opcode_modifier): Expand broadcast to 3 bits.
 283         * i386-tbl.h: Regenerated.
 284
 285 2018-07-24  Alan Modra  <amodra@gmail.com>
 286
 287         PR 23430
 288         * or1k-desc.h: Regenerate.
 289
 290 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 293         vcvtusi2ss, and vcvtusi2sd.
 294         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 295         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 296         * i386-tbl.h: Re-generate.
 297
 298 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 299
 300         * arc-opc.c (extract_w6): Fix extending the sign.
 301
 302 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 303
 304         * arc-tbl.h (vewt): Allow it for ARC EM family.
 305
 306 2018-07-23  Alan Modra  <amodra@gmail.com>
 307
 308         PR 23419
 309         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 310         opcode variants for mtspr/mfspr encodings.
 311
 312 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 313             Maciej W. Rozycki  <macro@mips.com>
 314
 315         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 316         loongson3a descriptors.
 317         (parse_mips_ase_option): Handle -M loongson-mmi option.
 318         (print_mips_disassembler_options): Document -M loongson-mmi.
 319         * mips-opc.c (LMMI): New macro.
 320         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 321         instructions.
 322
 323 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 326         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 327         IgnoreSize and [XYZ]MMword where applicable.
 328         * i386-tbl.h: Re-generate.
 329
 330 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 333         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 334         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 335         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 336         * i386-tbl.h: Re-generate.
 337
 338 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 339
 340         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 341         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 342         VPCLMULQDQ templates into their respective AVX512VL counterparts
 343         where possible, using Disp8ShiftVL and CheckRegSize instead of
 344         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 345         * i386-tbl.h: Re-generate.
 346
 347 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 350         AVX512VL counterparts where possible, using Disp8ShiftVL and
 351         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 352         IgnoreSize) as appropriate.
 353         * i386-tbl.h: Re-generate.
 354
 355 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 356
 357         * i386-opc.tbl: Fold AVX512BW templates into their respective
 358         AVX512VL counterparts where possible, using Disp8ShiftVL and
 359         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 360         IgnoreSize) as appropriate.
 361         * i386-tbl.h: Re-generate.
 362
 363 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-opc.tbl: Fold AVX512CD templates into their respective
 366         AVX512VL counterparts where possible, using Disp8ShiftVL and
 367         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 368         IgnoreSize) as appropriate.
 369         * i386-tbl.h: Re-generate.
 370
 371 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-opc.h (DISP8_SHIFT_VL): New.
 374         * i386-opc.tbl (Disp8ShiftVL):  Define.
 375         (various): Fold AVX512VL templates into their respective
 376         AVX512F counterparts where possible, using Disp8ShiftVL and
 377         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 378         IgnoreSize) as appropriate.
 379         * i386-tbl.h: Re-generate.
 380
 381 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 382
 383         * Makefile.am: Change dependencies and rule for
 384         $(srcdir)/i386-init.h.
 385         * Makefile.in: Re-generate.
 386         * i386-gen.c (process_i386_opcodes): New local variable
 387         "marker". Drop opening of input file. Recognize marker and line
 388         number directives.
 389         * i386-opc.tbl (OPCODE_I386_H): Define.
 390         (i386-opc.h): Include it.
 391         (None): Undefine.
 392
 393 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 394
 395         PR gas/23418
 396         * i386-opc.h (Byte): Update comments.
 397         (Word): Likewise.
 398         (Dword): Likewise.
 399         (Fword): Likewise.
 400         (Qword): Likewise.
 401         (Tbyte): Likewise.
 402         (Xmmword): Likewise.
 403         (Ymmword): Likewise.
 404         (Zmmword): Likewise.
 405         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 406         vcvttps2uqq.
 407         * i386-tbl.h: Regenerated.
 408
 409 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 410
 411         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 412         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 413         * aarch64-asm-2.c: Regenerate.
 414         * aarch64-dis-2.c: Regenerate.
 415         * aarch64-opc-2.c: Regenerate.
 416
 417 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 418
 419         PR binutils/23192
 420         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 421         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 422         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 423         sqdmulh, sqrdmulh): Use Em16.
 424
 425 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 426
 427         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 428         csdb together with them.
 429         (thumb32_opcodes): Likewise.
 430
 431 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 432
 433         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 434         requiring 32-bit registers as operands 2 and 3. Improve
 435         comments.
 436         (mwait, mwaitx): Fold templates. Improve comments.
 437         OPERAND_TYPE_INOUTPORTREG.
 438         * i386-tbl.h: Re-generate.
 439
 440 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-gen.c (operand_type_init): Remove
 443         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 444         OPERAND_TYPE_INOUTPORTREG.
 445         * i386-init.h: Re-generate.
 446
 447 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 450         (wrssq, wrussq): Add Qword.
 451         * i386-tbl.h: Re-generate.
 452
 453 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-opc.h: Rename OTMax to OTNum.
 456         (OTNumOfUints): Adjust calculation.
 457         (OTUnused): Directly alias to OTNum.
 458
 459 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 460
 461         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 462         `reg_xys'.
 463         (lea_reg_xys): Likewise.
 464         (print_insn_loop_primitive): Rename `reg' local variable to
 465         `reg_dxy'.
 466
 467 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 468
 469         PR binutils/23242
 470         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 471
 472 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 473
 474         PR binutils/23369
 475         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 476         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 477
 478 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 479
 480         PR tdep/8282
 481         * mips-dis.c (mips_option_arg_t): New enumeration.
 482         (mips_options): New variable.
 483         (disassembler_options_mips): New function.
 484         (print_mips_disassembler_options): Reimplement in terms of
 485         `disassembler_options_mips'.
 486         * arm-dis.c (disassembler_options_arm): Adapt to using the
 487         `disasm_options_and_args_t' structure.
 488         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 489         * s390-dis.c (disassembler_options_s390): Likewise.
 490
 491 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 492
 493         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 494         expected result.
 495         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 496         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 497         * testsuite/ld-arm/tls-longplt.d: Likewise.
 498
 499 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 500
 501         PR binutils/23192
 502         * aarch64-asm-2.c: Regenerate.
 503         * aarch64-dis-2.c: Likewise.
 504         * aarch64-opc-2.c: Likewise.
 505         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 506         * aarch64-opc.c (operand_general_constraint_met_p,
 507         aarch64_print_operand): Likewise.
 508         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 509         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 510         fmlal2, fmlsl2.
 511         (AARCH64_OPERANDS): Add Em2.
 512
 513 2018-06-26  Nick Clifton  <nickc@redhat.com>
 514
 515         * po/uk.po: Updated Ukranian translation.
 516         * po/de.po: Updated German translation.
 517         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 518
 519 2018-06-26  Nick Clifton  <nickc@redhat.com>
 520
 521         * nfp-dis.c: Fix spelling mistake.
 522
 523 2018-06-24  Nick Clifton  <nickc@redhat.com>
 524
 525         * configure: Regenerate.
 526         * po/opcodes.pot: Regenerate.
 527
 528 2018-06-24  Nick Clifton  <nickc@redhat.com>
 529
 530         2.31 branch created.
 531
 532 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 533
 534         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 535         * aarch64-asm-2.c: Regenerate.
 536         * aarch64-dis-2.c: Likewise.
 537
 538 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 539
 540         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 541         `-M ginv' option description.
 542
 543 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 544
 545         PR gas/23305
 546         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 547         la and lla.
 548
 549 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 550
 551         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 552         * configure.ac: Remove AC_PREREQ.
 553         * Makefile.in: Re-generate.
 554         * aclocal.m4: Re-generate.
 555         * configure: Re-generate.
 556
 557 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 558
 559         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 560         mips64r6 descriptors.
 561         (parse_mips_ase_option): Handle -Mginv option.
 562         (print_mips_disassembler_options): Document -Mginv.
 563         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 564         (GINV): New macro.
 565         (mips_opcodes): Define ginvi and ginvt.
 566
 567 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 568             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 569
 570         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 571         * mips-opc.c (CRC, CRC64): New macros.
 572         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 573         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 574         crc32cd for CRC64.
 575
 576 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 577
 578         PR 20319
 579         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 580         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 581
 582 2018-06-06  Alan Modra  <amodra@gmail.com>
 583
 584         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 585         setjmp.  Move init for some other vars later too.
 586
 587 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 588
 589         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 590         (dis_private): Add new fields for property section tracking.
 591         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 592         (xtensa_instruction_fits): New functions.
 593         (fetch_data): Bump minimal fetch size to 4.
 594         (print_insn_xtensa): Make struct dis_private static.
 595         Load and prepare property table on section change.
 596         Don't disassemble literals. Don't disassemble instructions that
 597         cross property table boundaries.
 598
 599 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 600
 601         * configure: Regenerated.
 602
 603 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 606         * i386-tbl.h: Re-generate.
 607
 608 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 609
 610         * i386-opc.tbl (sldt, str): Add NoRex64.
 611         * i386-tbl.h: Re-generate.
 612
 613 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 614
 615         * i386-opc.tbl (invpcid): Add Oword.
 616         * i386-tbl.h: Re-generate.
 617
 618 2018-06-01  Alan Modra  <amodra@gmail.com>
 619
 620         * sysdep.h (_bfd_error_handler): Don't declare.
 621         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 622         * rl78-decode.opc: Likewise.
 623         * msp430-decode.c: Regenerate.
 624         * rl78-decode.c: Regenerate.
 625
 626 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 627
 628         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 629         * i386-init.h : Regenerated.
 630
 631 2018-05-25  Alan Modra  <amodra@gmail.com>
 632
 633         * Makefile.in: Regenerate.
 634         * po/POTFILES.in: Regenerate.
 635
 636 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 637
 638         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 639         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 640         (insert_bab, extract_bab, insert_btab, extract_btab,
 641         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 642         (BAT, BBA VBA RBS XB6S): Delete macros.
 643         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 644         (BB, BD, RBX, XC6): Update for new macros.
 645         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 646         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 647         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 648         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 649
 650 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 651
 652         * Makefile.am: Add support for s12z architecture.
 653         * configure.ac: Likewise.
 654         * disassemble.c: Likewise.
 655         * disassemble.h: Likewise.
 656         * Makefile.in: Regenerate.
 657         * configure: Regenerate.
 658         * s12z-dis.c: New file.
 659         * s12z.h: New file.
 660
 661 2018-05-18  Alan Modra  <amodra@gmail.com>
 662
 663         * nfp-dis.c: Don't #include libbfd.h.
 664         (init_nfp3200_priv): Use bfd_get_section_contents.
 665         (nit_nfp6000_mecsr_sec): Likewise.
 666
 667 2018-05-17  Nick Clifton  <nickc@redhat.com>
 668
 669         * po/zh_CN.po: Updated simplified Chinese translation.
 670
 671 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 672
 673         PR binutils/23109
 674         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 675         * aarch64-dis-2.c: Regenerate.
 676
 677 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 678
 679         PR binutils/21446
 680         * aarch64-asm.c (opintl.h): Include.
 681         (aarch64_ins_sysreg): Enforce read/write constraints.
 682         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 683         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 684         (F_REG_READ, F_REG_WRITE): New.
 685         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 686         AARCH64_OPND_SYSREG.
 687         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 688         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 689         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 690         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 691         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 692         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 693         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 694         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 695         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 696         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 697         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 698         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 699         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 700         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 701         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 702         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 703         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 704
 705 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 706
 707         PR binutils/21446
 708         * aarch64-dis.c (no_notes: New.
 709         (parse_aarch64_dis_option): Support notes.
 710         (aarch64_decode_insn, print_operands): Likewise.
 711         (print_aarch64_disassembler_options): Document notes.
 712         * aarch64-opc.c (aarch64_print_operand): Support notes.
 713
 714 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 715
 716         PR binutils/21446
 717         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 718         and take error struct.
 719         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 720         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 721         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 722         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 723         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 724         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 725         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 726         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 727         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 728         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 729         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 730         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 731         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 732         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 733         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 734         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 735         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 736         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 737         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 738         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 739         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 740         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 741         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 742         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 743         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 744         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 745         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 746         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 747         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 748         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 749         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 750         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 751         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 752         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 753         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 754         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 755         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 756         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 757         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 758         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 759         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 760         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 761         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 762         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 763         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 764         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 765         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 766         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 767         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 768         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 769         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 770         (determine_disassembling_preference, aarch64_decode_insn,
 771         print_insn_aarch64_word, print_insn_data): Take errors struct.
 772         (print_insn_aarch64): Use errors.
 773         * aarch64-asm-2.c: Regenerate.
 774         * aarch64-dis-2.c: Regenerate.
 775         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 776         boolean in aarch64_insert_operan.
 777         (print_operand_extractor): Likewise.
 778         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 779
 780 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 781
 782         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 783
 784 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 785
 786         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 787
 788 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 789
 790         * cr16-opc.c (cr16_instruction): Comment typo fix.
 791         * hppa-dis.c (print_insn_hppa): Likewise.
 792
 793 2018-05-08  Jim Wilson  <jimw@sifive.com>
 794
 795         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 796         (match_c_slli64, match_srxi_as_c_srxi): New.
 797         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 798         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 799         <c.slli, c.srli, c.srai>: Use match_s_slli.
 800         <c.slli64, c.srli64, c.srai64>: New.
 801
 802 2018-05-08  Alan Modra  <amodra@gmail.com>
 803
 804         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 805         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 806         partition opcode space for index lookup.
 807
 808 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 809
 810         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 811         <insn_length>: ...with this.  Update usage.
 812         Remove duplicate call to *info->memory_error_func.
 813
 814 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 815             H.J. Lu  <hongjiu.lu@intel.com>
 816
 817         * i386-dis.c (Gva): New.
 818         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 819         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 820         (prefix_table): New instructions (see prefix above).
 821         (mod_table): New instructions (see prefix above).
 822         (OP_G): Handle va_mode.
 823         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 824         CPU_MOVDIR64B_FLAGS.
 825         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 826         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 827         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 828         * i386-opc.tbl: Add movidir{i,64b}.
 829         * i386-init.h: Regenerated.
 830         * i386-tbl.h: Likewise.
 831
 832 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 833
 834         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 835         AddrPrefixOpReg.
 836         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 837         (AddrPrefixOpReg): This.
 838         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 839         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 840
 841 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 842
 843         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 844         (vle_num_opcodes): Likewise.
 845         (spe2_num_opcodes): Likewise.
 846         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 847         initialization loop.
 848         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 849         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 850         only once.
 851
 852 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 853
 854         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 855
 856 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 857
 858         Makefile.am: Added nfp-dis.c.
 859         configure.ac: Added bfd_nfp_arch.
 860         disassemble.h: Added print_insn_nfp prototype.
 861         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 862         nfp-dis.c: New, for NFP support.
 863         po/POTFILES.in: Added nfp-dis.c to the list.
 864         Makefile.in: Regenerate.
 865         configure: Regenerate.
 866
 867 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 870         templates into their base ones.
 871         * i386-tlb.h: Re-generate.
 872
 873 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 874
 875         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 876         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 877         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 878         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 879         * i386-init.h: Re-generate.
 880
 881 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 882
 883         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 884         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 885         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 886         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 887         comment.
 888         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 889         and CpuRegMask.
 890         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 891         CpuRegMask: Delete.
 892         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 893         cpuregzmm, and cpuregmask.
 894         * i386-init.h: Re-generate.
 895         * i386-tbl.h: Re-generate.
 896
 897 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 898
 899         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 900         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 901         * i386-init.h: Re-generate.
 902
 903 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 904
 905         * i386-gen.c (VexImmExt): Delete.
 906         * i386-opc.h (VexImmExt, veximmext): Delete.
 907         * i386-opc.tbl: Drop all VexImmExt uses.
 908         * i386-tlb.h: Re-generate.
 909
 910 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 911
 912         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 913         register-only forms.
 914         * i386-tlb.h: Re-generate.
 915
 916 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 917
 918         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 919
 920 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 921
 922         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 923         PREFIX_0F1C.
 924         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 925         (cpu_flags): Add CpuCLDEMOTE.
 926         * i386-init.h: Regenerate.
 927         * i386-opc.h (enum): Add CpuCLDEMOTE,
 928         (i386_cpu_flags): Add cpucldemote.
 929         * i386-opc.tbl: Add cldemote.
 930         * i386-tbl.h: Regenerate.
 931
 932 2018-04-16  Alan Modra  <amodra@gmail.com>
 933
 934         * Makefile.am: Remove sh5 and sh64 support.
 935         * configure.ac: Likewise.
 936         * disassemble.c: Likewise.
 937         * disassemble.h: Likewise.
 938         * sh-dis.c: Likewise.
 939         * sh64-dis.c: Delete.
 940         * sh64-opc.c: Delete.
 941         * sh64-opc.h: Delete.
 942         * Makefile.in: Regenerate.
 943         * configure: Regenerate.
 944         * po/POTFILES.in: Regenerate.
 945
 946 2018-04-16  Alan Modra  <amodra@gmail.com>
 947
 948         * Makefile.am: Remove w65 support.
 949         * configure.ac: Likewise.
 950         * disassemble.c: Likewise.
 951         * disassemble.h: Likewise.
 952         * w65-dis.c: Delete.
 953         * w65-opc.h: Delete.
 954         * Makefile.in: Regenerate.
 955         * configure: Regenerate.
 956         * po/POTFILES.in: Regenerate.
 957
 958 2018-04-16  Alan Modra  <amodra@gmail.com>
 959
 960         * configure.ac: Remove we32k support.
 961         * configure: Regenerate.
 962
 963 2018-04-16  Alan Modra  <amodra@gmail.com>
 964
 965         * Makefile.am: Remove m88k support.
 966         * configure.ac: Likewise.
 967         * disassemble.c: Likewise.
 968         * disassemble.h: Likewise.
 969         * m88k-dis.c: Delete.
 970         * Makefile.in: Regenerate.
 971         * configure: Regenerate.
 972         * po/POTFILES.in: Regenerate.
 973
 974 2018-04-16  Alan Modra  <amodra@gmail.com>
 975
 976         * Makefile.am: Remove i370 support.
 977         * configure.ac: Likewise.
 978         * disassemble.c: Likewise.
 979         * disassemble.h: Likewise.
 980         * i370-dis.c: Delete.
 981         * i370-opc.c: Delete.
 982         * Makefile.in: Regenerate.
 983         * configure: Regenerate.
 984         * po/POTFILES.in: Regenerate.
 985
 986 2018-04-16  Alan Modra  <amodra@gmail.com>
 987
 988         * Makefile.am: Remove h8500 support.
 989         * configure.ac: Likewise.
 990         * disassemble.c: Likewise.
 991         * disassemble.h: Likewise.
 992         * h8500-dis.c: Delete.
 993         * h8500-opc.h: Delete.
 994         * Makefile.in: Regenerate.
 995         * configure: Regenerate.
 996         * po/POTFILES.in: Regenerate.
 997
 998 2018-04-16  Alan Modra  <amodra@gmail.com>
 999
1000         * configure.ac: Remove tahoe support.
1001         * configure: Regenerate.
1002
1003 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1004
1005         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1006         umwait.
1007         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1008         64-bit mode.
1009         * i386-tbl.h: Regenerated.
1010
1011 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1012
1013         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1014         PREFIX_MOD_1_0FAE_REG_6.
1015         (va_mode): New.
1016         (OP_E_register): Use va_mode.
1017         * i386-dis-evex.h (prefix_table):
1018         New instructions (see prefixes above).
1019         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1020         (cpu_flags): Likewise.
1021         * i386-opc.h (enum): Likewise.
1022         (i386_cpu_flags): Likewise.
1023         * i386-opc.tbl: Add umonitor, umwait, tpause.
1024         * i386-init.h: Regenerate.
1025         * i386-tbl.h: Likewise.
1026
1027 2018-04-11  Alan Modra  <amodra@gmail.com>
1028
1029         * opcodes/i860-dis.c: Delete.
1030         * opcodes/i960-dis.c: Delete.
1031         * Makefile.am: Remove i860 and i960 support.
1032         * configure.ac: Likewise.
1033         * disassemble.c: Likewise.
1034         * disassemble.h: Likewise.
1035         * Makefile.in: Regenerate.
1036         * configure: Regenerate.
1037         * po/POTFILES.in: Regenerate.
1038
1039 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1040
1041         PR binutils/23025
1042         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1043         to 0.
1044         (print_insn): Clear vex instead of vex.evex.
1045
1046 2018-04-04  Nick Clifton  <nickc@redhat.com>
1047
1048         * po/es.po: Updated Spanish translation.
1049
1050 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1051
1052         * i386-gen.c (opcode_modifiers): Delete VecESize.
1053         * i386-opc.h (VecESize): Delete.
1054         (struct i386_opcode_modifier): Delete vecesize.
1055         * i386-opc.tbl: Drop VecESize.
1056         * i386-tlb.h: Re-generate.
1057
1058 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1061         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1062         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1063         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1064         * i386-tlb.h: Re-generate.
1065
1066 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1067
1068         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1069         Fold AVX512 forms
1070         * i386-tlb.h: Re-generate.
1071
1072 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1075         (vex_len_table): Drop Y for vcvt*2si.
1076         (putop): Replace plain 'Y' handling by abort().
1077
1078 2018-03-28  Nick Clifton  <nickc@redhat.com>
1079
1080         PR 22988
1081         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1082         instructions with only a base address register.
1083         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1084         handle AARHC64_OPND_SVE_ADDR_R.
1085         (aarch64_print_operand): Likewise.
1086         * aarch64-asm-2.c: Regenerate.
1087         * aarch64_dis-2.c: Regenerate.
1088         * aarch64-opc-2.c: Regenerate.
1089
1090 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1091
1092         * i386-opc.tbl: Drop VecESize from register only insn forms and
1093         memory forms not allowing broadcast.
1094         * i386-tlb.h: Re-generate.
1095
1096 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1097
1098         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1099         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1100         sha256*): Drop Disp<N>.
1101
1102 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1103
1104         * i386-dis.c (EbndS, bnd_swap_mode): New.
1105         (prefix_table): Use EbndS.
1106         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1107         * i386-opc.tbl (bndmov): Move misplaced Load.
1108         * i386-tlb.h: Re-generate.
1109
1110 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1111
1112         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1113         templates allowing memory operands and folded ones for register
1114         only flavors.
1115         * i386-tlb.h: Re-generate.
1116
1117 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1118
1119         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1120         256-bit templates. Drop redundant leftover Disp<N>.
1121         * i386-tlb.h: Re-generate.
1122
1123 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1124
1125         * riscv-opc.c (riscv_insn_types): New.
1126
1127 2018-03-13  Nick Clifton  <nickc@redhat.com>
1128
1129         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1130
1131 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1132
1133         * i386-opc.tbl: Add Optimize to clr.
1134         * i386-tbl.h: Regenerated.
1135
1136 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1137
1138         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1139         * i386-opc.h (OldGcc): Removed.
1140         (i386_opcode_modifier): Remove oldgcc.
1141         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1142         instructions for old (<= 2.8.1) versions of gcc.
1143         * i386-tbl.h: Regenerated.
1144
1145 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-opc.h (EVEXDYN): New.
1148         * i386-opc.tbl: Fold various AVX512VL templates.
1149         * i386-tlb.h: Re-generate.
1150
1151 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1154         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1155         vpexpandd, vpexpandq): Fold AFX512VF templates.
1156         * i386-tlb.h: Re-generate.
1157
1158 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1159
1160         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1161         Fold 128- and 256-bit VEX-encoded templates.
1162         * i386-tlb.h: Re-generate.
1163
1164 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1165
1166         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1167         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1168         vpexpandd, vpexpandq): Fold AVX512F templates.
1169         * i386-tlb.h: Re-generate.
1170
1171 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1172
1173         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1174         64-bit templates. Drop Disp<N>.
1175         * i386-tlb.h: Re-generate.
1176
1177 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1178
1179         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1180         and 256-bit templates.
1181         * i386-tlb.h: Re-generate.
1182
1183 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1186         * i386-tlb.h: Re-generate.
1187
1188 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1191         Drop NoAVX.
1192         * i386-tlb.h: Re-generate.
1193
1194 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1195
1196         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1197         * i386-tlb.h: Re-generate.
1198
1199 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1200
1201         * i386-gen.c (opcode_modifiers): Delete FloatD.
1202         * i386-opc.h (FloatD): Delete.
1203         (struct i386_opcode_modifier): Delete floatd.
1204         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1205         FloatD by D.
1206         * i386-tlb.h: Re-generate.
1207
1208 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1209
1210         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1211
1212 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1213
1214         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1215         * i386-tlb.h: Re-generate.
1216
1217 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1218
1219         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1220         forms.
1221         * i386-tlb.h: Re-generate.
1222
1223 2018-03-07  Alan Modra  <amodra@gmail.com>
1224
1225         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1226         bfd_arch_rs6000.
1227         * disassemble.h (print_insn_rs6000): Delete.
1228         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1229         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1230         (print_insn_rs6000): Delete.
1231
1232 2018-03-03  Alan Modra  <amodra@gmail.com>
1233
1234         * sysdep.h (opcodes_error_handler): Define.
1235         (_bfd_error_handler): Declare.
1236         * Makefile.am: Remove stray #.
1237         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1238         EDIT" comment.
1239         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1240         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1241         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1242         opcodes_error_handler to print errors.  Standardize error messages.
1243         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1244         and include opintl.h.
1245         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1246         * i386-gen.c: Standardize error messages.
1247         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1248         * Makefile.in: Regenerate.
1249         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1250         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1251         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1252         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1253         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1254         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1255         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1256         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1257         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1258         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1259         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1260         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1261         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1262
1263 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1264
1265         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1266         vpsub[bwdq] instructions.
1267         * i386-tbl.h: Regenerated.
1268
1269 2018-03-01  Alan Modra  <amodra@gmail.com>
1270
1271         * configure.ac (ALL_LINGUAS): Sort.
1272         * configure: Regenerate.
1273
1274 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1275
1276         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1277         macro by assignements.
1278
1279 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1280
1281         PR gas/22871
1282         * i386-gen.c (opcode_modifiers): Add Optimize.
1283         * i386-opc.h (Optimize): New enum.
1284         (i386_opcode_modifier): Add optimize.
1285         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1286         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1287         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1288         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1289         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1290         vpxord and vpxorq.
1291         * i386-tbl.h: Regenerated.
1292
1293 2018-02-26  Alan Modra  <amodra@gmail.com>
1294
1295         * crx-dis.c (getregliststring): Allocate a large enough buffer
1296         to silence false positive gcc8 warning.
1297
1298 2018-02-22  Shea Levy <shea@shealevy.com>
1299
1300         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1301
1302 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1303
1304         * i386-opc.tbl: Add {rex},
1305         * i386-tbl.h: Regenerated.
1306
1307 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1308
1309         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1310         (mips16_opcodes): Replace `M' with `m' for "restore".
1311
1312 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1313
1314         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1315
1316 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1317
1318         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1319         variable to `function_index'.
1320
1321 2018-02-13  Nick Clifton  <nickc@redhat.com>
1322
1323         PR 22823
1324         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1325         about truncation of printing.
1326
1327 2018-02-12  Henry Wong <henry@stuffedcow.net>
1328
1329         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1330
1331 2018-02-05  Nick Clifton  <nickc@redhat.com>
1332
1333         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1334
1335 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1336
1337         * i386-dis.c (enum): Add pconfig.
1338         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1339         (cpu_flags): Add CpuPCONFIG.
1340         * i386-opc.h (enum): Add CpuPCONFIG.
1341         (i386_cpu_flags): Add cpupconfig.
1342         * i386-opc.tbl: Add PCONFIG instruction.
1343         * i386-init.h: Regenerate.
1344         * i386-tbl.h: Likewise.
1345
1346 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1347
1348         * i386-dis.c (enum): Add PREFIX_0F09.
1349         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1350         (cpu_flags): Add CpuWBNOINVD.
1351         * i386-opc.h (enum): Add CpuWBNOINVD.
1352         (i386_cpu_flags): Add cpuwbnoinvd.
1353         * i386-opc.tbl: Add WBNOINVD instruction.
1354         * i386-init.h: Regenerate.
1355         * i386-tbl.h: Likewise.
1356
1357 2018-01-17  Jim Wilson  <jimw@sifive.com>
1358
1359         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1360
1361 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1362
1363         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1364         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1365         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1366         (cpu_flags): Add CpuIBT, CpuSHSTK.
1367         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1368         (i386_cpu_flags): Add cpuibt, cpushstk.
1369         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1370         * i386-init.h: Regenerate.
1371         * i386-tbl.h: Likewise.
1372
1373 2018-01-16  Nick Clifton  <nickc@redhat.com>
1374
1375         * po/pt_BR.po: Updated Brazilian Portugese translation.
1376         * po/de.po: Updated German translation.
1377
1378 2018-01-15  Jim Wilson  <jimw@sifive.com>
1379
1380         * riscv-opc.c (match_c_nop): New.
1381         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1382
1383 2018-01-15  Nick Clifton  <nickc@redhat.com>
1384
1385         * po/uk.po: Updated Ukranian translation.
1386
1387 2018-01-13  Nick Clifton  <nickc@redhat.com>
1388
1389         * po/opcodes.pot: Regenerated.
1390
1391 2018-01-13  Nick Clifton  <nickc@redhat.com>
1392
1393         * configure: Regenerate.
1394
1395 2018-01-13  Nick Clifton  <nickc@redhat.com>
1396
1397         2.30 branch created.
1398
1399 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1400
1401         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1402         * i386-tbl.h: Regenerate.
1403
1404 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1405
1406         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1407         * i386-tbl.h: Re-generate.
1408
1409 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1410
1411         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1412         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1413         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1414         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1415         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1416         Disp8MemShift of AVX512VL forms.
1417         * i386-tbl.h: Re-generate.
1418
1419 2018-01-09  Jim Wilson  <jimw@sifive.com>
1420
1421         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1422         then the hi_addr value is zero.
1423
1424 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1425
1426         * arm-dis.c (arm_opcodes): Add csdb.
1427         (thumb32_opcodes): Add csdb.
1428
1429 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1430
1431         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1432         * aarch64-asm-2.c: Regenerate.
1433         * aarch64-dis-2.c: Regenerate.
1434         * aarch64-opc-2.c: Regenerate.
1435
1436 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1437
1438         PR gas/22681
1439         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1440         Remove AVX512 vmovd with 64-bit operands.
1441         * i386-tbl.h: Regenerated.
1442
1443 2018-01-05  Jim Wilson  <jimw@sifive.com>
1444
1445         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1446         jalr.
1447
1448 2018-01-03  Alan Modra  <amodra@gmail.com>
1449
1450         Update year range in copyright notice of all files.
1451
1452 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1453
1454         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1455         and OPERAND_TYPE_REGZMM entries.
1456
1457 For older changes see ChangeLog-2017
1458 \f
1459 Copyright (C) 2018 Free Software Foundation, Inc.
1460
1461 Copying and distribution of this file, with or without modification,
1462 are permitted in any medium without royalty provided the copyright
1463 notice and this notice are preserved.
1464
1465 Local Variables:
1466 mode: change-log
1467 left-margin: 8
1468 fill-column: 74
1469 version-control: never
1470 End: