opcodes/ChangeLog

   1 2018-09-13  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
   4         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
   5         (intel_operand_size): Handle v_bndmk_mode.
   6         (OP_E_memory): Likewise. Produce (bad) when also riprel.
   7
   8 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
   9
  10         * disassemble.c (ARCH_s12z): Define if ARCH_all.
  11
  12 2018-08-31  Kito Cheng  <kito@andestech.com>
  13
  14         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
  15         compressed floating point instructions.
  16
  17 2018-08-30  Kito Cheng  <kito@andestech.com>
  18
  19         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
  20         riscv_opcode.xlen_requirement.
  21         * riscv-opc.c (riscv_opcodes): Update for struct change.
  22
  23 2018-08-29  Martin Aberg  <maberg@gaisler.com>
  24
  25         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
  26         psr (PWRPSR) instruction.
  27
  28 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  29
  30         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
  31
  32 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  33
  34         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
  35
  36 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  37
  38         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
  39         loongson3a as an alias of gs464 for compatibility.
  40         * mips-opc.c (mips_opcodes): Change Comments.
  41
  42 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  43
  44         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
  45         option.
  46         (print_mips_disassembler_options): Document -M loongson-ext.
  47         * mips-opc.c (LEXT2): New macro.
  48         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
  49
  50 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  51
  52          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
  53          descriptors.
  54          (parse_mips_ase_option): Handle -M loongson-ext option.
  55          (print_mips_disassembler_options): Document -M loongson-ext.
  56          * mips-opc.c (IL3A): Delete.
  57          * mips-opc.c (LEXT): New macro.
  58          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
  59          instructions.
  60
  61 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
  62
  63         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
  64         descriptors.
  65         (parse_mips_ase_option): Handle -M loongson-cam option.
  66         (print_mips_disassembler_options): Document -M loongson-cam.
  67         * mips-opc.c (LCAM): New macro.
  68         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
  69         instructions.
  70
  71 2018-08-21  Alan Modra  <amodra@gmail.com>
  72
  73         * ppc-dis.c (operand_value_powerpc): Init "invalid".
  74         (skip_optional_operands): Count optional operands, and update
  75         ppc_optional_operand_value call.
  76         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
  77         (extract_vlensi): Likewise.
  78         (extract_fxm): Return default value for missing optional operand.
  79         (extract_ls, extract_raq, extract_tbr): Likewise.
  80         (insert_sxl, extract_sxl): New functions.
  81         (insert_esync, extract_esync): Remove Power9 handling and simplify.
  82         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
  83         flag and extra entry.
  84         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
  85         extract_sxl.
  86
  87 2018-08-20  Alan Modra  <amodra@gmail.com>
  88
  89         * sh-opc.h (MASK): Simplify.
  90
  91 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
  92
  93         * s12z-dis.c (bm_decode): Deal with cases where the mode is
  94         BM_RESERVED0 or BM_RESERVED1
  95         (bm_rel_decode, bm_n_bytes): Ditto.
  96
  97 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
  98
  99         * s12z.h: Delete.
 100
 101 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 102
 103         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 104         address with the addr32 prefix and without base nor index
 105         registers.
 106
 107 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 108
 109         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 110         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 111         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 112         (cpu_flags): Add CpuCMOV and CpuFXSR.
 113         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 114         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 115         * i386-init.h: Regenerated.
 116         * i386-tbl.h: Likewise.
 117
 118 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 119
 120         * arc-regs.h: Update auxiliary registers.
 121
 122 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 123
 124         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 125         (RegIP, RegIZ): Define.
 126         * i386-reg.tbl: Adjust comments.
 127         (rip): Use Qword instead of BaseIndex. Use RegIP.
 128         (eip): Use Dword instead of BaseIndex. Use RegIP.
 129         (riz): Add Qword. Use RegIZ.
 130         (eiz): Add Dword. Use RegIZ.
 131         * i386-tbl.h: Re-generate.
 132
 133 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 136         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 137         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 138         * i386-tbl.h: Re-generate.
 139
 140 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-gen.c (operand_types): Remove Mem field.
 143         * i386-opc.h (union i386_operand_type): Remove mem field.
 144         * i386-init.h, i386-tbl.h: Re-generate.
 145
 146 2018-08-01  Alan Modra  <amodra@gmail.com>
 147
 148         * po/POTFILES.in: Regenerate.
 149
 150 2018-07-31  Nick Clifton  <nickc@redhat.com>
 151
 152         * po/sv.po: Updated Swedish translation.
 153
 154 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 157         * i386-init.h, i386-tbl.h: Re-generate.
 158
 159 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-opc.h (ZEROING_MASKING) Rename to ...
 162         (DYNAMIC_MASKING): ... this. Adjust comment.
 163         * i386-opc.tbl (MaskingMorZ): Define.
 164         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 165         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 166         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 167         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 168         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 169         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 170         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 171         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 172         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 173
 174 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-opc.tbl: Use element rather than vector size for AVX512*
 177         scatter/gather insns.
 178         * i386-tbl.h: Re-generate.
 179
 180 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 183         (cpu_flags): Drop CpuVREX.
 184         * i386-opc.h (CpuVREX): Delete.
 185         (union i386_cpu_flags): Remove cpuvrex.
 186         * i386-init.h, i386-tbl.h: Re-generate.
 187
 188 2018-07-30  Jim Wilson  <jimw@sifive.com>
 189
 190         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 191         fields.
 192         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 193
 194 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 195
 196         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 197         * Makefile.in: Regenerated.
 198         * configure.ac: Add C-SKY.
 199         * configure: Regenerated.
 200         * csky-dis.c: New file.
 201         * csky-opc.h: New file.
 202         * disassemble.c (ARCH_csky): Define.
 203         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 204         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 205
 206 2018-07-27  Alan Modra  <amodra@gmail.com>
 207
 208         * ppc-opc.c (insert_sprbat): Correct function parameter and
 209         return type.
 210         (extract_sprbat): Likewise, variable too.
 211
 212 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 213             Alan Modra  <amodra@gmail.com>
 214
 215         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 216         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 217         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 218         support disjointed BAT.
 219         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 220         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 221         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 222
 223 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 224             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 225
 226         * i386-gen.c (adjust_broadcast_modifier): New function.
 227         (process_i386_opcode_modifier): Add an argument for operands.
 228         Adjust the Broadcast value based on operands.
 229         (output_i386_opcode): Pass operand_types to
 230         process_i386_opcode_modifier.
 231         (process_i386_opcodes): Pass NULL as operands to
 232         process_i386_opcode_modifier.
 233         * i386-opc.h (BYTE_BROADCAST): New.
 234         (WORD_BROADCAST): Likewise.
 235         (DWORD_BROADCAST): Likewise.
 236         (QWORD_BROADCAST): Likewise.
 237         (i386_opcode_modifier): Expand broadcast to 3 bits.
 238         * i386-tbl.h: Regenerated.
 239
 240 2018-07-24  Alan Modra  <amodra@gmail.com>
 241
 242         PR 23430
 243         * or1k-desc.h: Regenerate.
 244
 245 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 248         vcvtusi2ss, and vcvtusi2sd.
 249         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 250         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 251         * i386-tbl.h: Re-generate.
 252
 253 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 254
 255         * arc-opc.c (extract_w6): Fix extending the sign.
 256
 257 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 258
 259         * arc-tbl.h (vewt): Allow it for ARC EM family.
 260
 261 2018-07-23  Alan Modra  <amodra@gmail.com>
 262
 263         PR 23419
 264         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 265         opcode variants for mtspr/mfspr encodings.
 266
 267 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 268             Maciej W. Rozycki  <macro@mips.com>
 269
 270         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 271         loongson3a descriptors.
 272         (parse_mips_ase_option): Handle -M loongson-mmi option.
 273         (print_mips_disassembler_options): Document -M loongson-mmi.
 274         * mips-opc.c (LMMI): New macro.
 275         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 276         instructions.
 277
 278 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 279
 280         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 281         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 282         IgnoreSize and [XYZ]MMword where applicable.
 283         * i386-tbl.h: Re-generate.
 284
 285 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 288         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 289         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 290         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 291         * i386-tbl.h: Re-generate.
 292
 293 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 294
 295         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 296         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 297         VPCLMULQDQ templates into their respective AVX512VL counterparts
 298         where possible, using Disp8ShiftVL and CheckRegSize instead of
 299         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 300         * i386-tbl.h: Re-generate.
 301
 302 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 305         AVX512VL counterparts where possible, using Disp8ShiftVL and
 306         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 307         IgnoreSize) as appropriate.
 308         * i386-tbl.h: Re-generate.
 309
 310 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 311
 312         * i386-opc.tbl: Fold AVX512BW templates into their respective
 313         AVX512VL counterparts where possible, using Disp8ShiftVL and
 314         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 315         IgnoreSize) as appropriate.
 316         * i386-tbl.h: Re-generate.
 317
 318 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-opc.tbl: Fold AVX512CD templates into their respective
 321         AVX512VL counterparts where possible, using Disp8ShiftVL and
 322         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 323         IgnoreSize) as appropriate.
 324         * i386-tbl.h: Re-generate.
 325
 326 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-opc.h (DISP8_SHIFT_VL): New.
 329         * i386-opc.tbl (Disp8ShiftVL):  Define.
 330         (various): Fold AVX512VL templates into their respective
 331         AVX512F counterparts where possible, using Disp8ShiftVL and
 332         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 333         IgnoreSize) as appropriate.
 334         * i386-tbl.h: Re-generate.
 335
 336 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 337
 338         * Makefile.am: Change dependencies and rule for
 339         $(srcdir)/i386-init.h.
 340         * Makefile.in: Re-generate.
 341         * i386-gen.c (process_i386_opcodes): New local variable
 342         "marker". Drop opening of input file. Recognize marker and line
 343         number directives.
 344         * i386-opc.tbl (OPCODE_I386_H): Define.
 345         (i386-opc.h): Include it.
 346         (None): Undefine.
 347
 348 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 349
 350         PR gas/23418
 351         * i386-opc.h (Byte): Update comments.
 352         (Word): Likewise.
 353         (Dword): Likewise.
 354         (Fword): Likewise.
 355         (Qword): Likewise.
 356         (Tbyte): Likewise.
 357         (Xmmword): Likewise.
 358         (Ymmword): Likewise.
 359         (Zmmword): Likewise.
 360         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 361         vcvttps2uqq.
 362         * i386-tbl.h: Regenerated.
 363
 364 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 365
 366         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 367         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 368         * aarch64-asm-2.c: Regenerate.
 369         * aarch64-dis-2.c: Regenerate.
 370         * aarch64-opc-2.c: Regenerate.
 371
 372 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 373
 374         PR binutils/23192
 375         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 376         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 377         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 378         sqdmulh, sqrdmulh): Use Em16.
 379
 380 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 381
 382         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 383         csdb together with them.
 384         (thumb32_opcodes): Likewise.
 385
 386 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 387
 388         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 389         requiring 32-bit registers as operands 2 and 3. Improve
 390         comments.
 391         (mwait, mwaitx): Fold templates. Improve comments.
 392         OPERAND_TYPE_INOUTPORTREG.
 393         * i386-tbl.h: Re-generate.
 394
 395 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-gen.c (operand_type_init): Remove
 398         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 399         OPERAND_TYPE_INOUTPORTREG.
 400         * i386-init.h: Re-generate.
 401
 402 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 403
 404         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 405         (wrssq, wrussq): Add Qword.
 406         * i386-tbl.h: Re-generate.
 407
 408 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 409
 410         * i386-opc.h: Rename OTMax to OTNum.
 411         (OTNumOfUints): Adjust calculation.
 412         (OTUnused): Directly alias to OTNum.
 413
 414 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 415
 416         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 417         `reg_xys'.
 418         (lea_reg_xys): Likewise.
 419         (print_insn_loop_primitive): Rename `reg' local variable to
 420         `reg_dxy'.
 421
 422 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 423
 424         PR binutils/23242
 425         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 426
 427 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 428
 429         PR binutils/23369
 430         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 431         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 432
 433 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 434
 435         PR tdep/8282
 436         * mips-dis.c (mips_option_arg_t): New enumeration.
 437         (mips_options): New variable.
 438         (disassembler_options_mips): New function.
 439         (print_mips_disassembler_options): Reimplement in terms of
 440         `disassembler_options_mips'.
 441         * arm-dis.c (disassembler_options_arm): Adapt to using the
 442         `disasm_options_and_args_t' structure.
 443         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 444         * s390-dis.c (disassembler_options_s390): Likewise.
 445
 446 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 447
 448         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 449         expected result.
 450         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 451         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 452         * testsuite/ld-arm/tls-longplt.d: Likewise.
 453
 454 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 455
 456         PR binutils/23192
 457         * aarch64-asm-2.c: Regenerate.
 458         * aarch64-dis-2.c: Likewise.
 459         * aarch64-opc-2.c: Likewise.
 460         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 461         * aarch64-opc.c (operand_general_constraint_met_p,
 462         aarch64_print_operand): Likewise.
 463         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 464         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 465         fmlal2, fmlsl2.
 466         (AARCH64_OPERANDS): Add Em2.
 467
 468 2018-06-26  Nick Clifton  <nickc@redhat.com>
 469
 470         * po/uk.po: Updated Ukranian translation.
 471         * po/de.po: Updated German translation.
 472         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 473
 474 2018-06-26  Nick Clifton  <nickc@redhat.com>
 475
 476         * nfp-dis.c: Fix spelling mistake.
 477
 478 2018-06-24  Nick Clifton  <nickc@redhat.com>
 479
 480         * configure: Regenerate.
 481         * po/opcodes.pot: Regenerate.
 482
 483 2018-06-24  Nick Clifton  <nickc@redhat.com>
 484
 485         2.31 branch created.
 486
 487 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 488
 489         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 490         * aarch64-asm-2.c: Regenerate.
 491         * aarch64-dis-2.c: Likewise.
 492
 493 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 494
 495         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 496         `-M ginv' option description.
 497
 498 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 499
 500         PR gas/23305
 501         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 502         la and lla.
 503
 504 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 505
 506         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 507         * configure.ac: Remove AC_PREREQ.
 508         * Makefile.in: Re-generate.
 509         * aclocal.m4: Re-generate.
 510         * configure: Re-generate.
 511
 512 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 513
 514         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 515         mips64r6 descriptors.
 516         (parse_mips_ase_option): Handle -Mginv option.
 517         (print_mips_disassembler_options): Document -Mginv.
 518         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 519         (GINV): New macro.
 520         (mips_opcodes): Define ginvi and ginvt.
 521
 522 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 523             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 524
 525         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 526         * mips-opc.c (CRC, CRC64): New macros.
 527         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 528         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 529         crc32cd for CRC64.
 530
 531 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 532
 533         PR 20319
 534         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 535         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 536
 537 2018-06-06  Alan Modra  <amodra@gmail.com>
 538
 539         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 540         setjmp.  Move init for some other vars later too.
 541
 542 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 543
 544         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 545         (dis_private): Add new fields for property section tracking.
 546         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 547         (xtensa_instruction_fits): New functions.
 548         (fetch_data): Bump minimal fetch size to 4.
 549         (print_insn_xtensa): Make struct dis_private static.
 550         Load and prepare property table on section change.
 551         Don't disassemble literals. Don't disassemble instructions that
 552         cross property table boundaries.
 553
 554 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 555
 556         * configure: Regenerated.
 557
 558 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 561         * i386-tbl.h: Re-generate.
 562
 563 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 564
 565         * i386-opc.tbl (sldt, str): Add NoRex64.
 566         * i386-tbl.h: Re-generate.
 567
 568 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-opc.tbl (invpcid): Add Oword.
 571         * i386-tbl.h: Re-generate.
 572
 573 2018-06-01  Alan Modra  <amodra@gmail.com>
 574
 575         * sysdep.h (_bfd_error_handler): Don't declare.
 576         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 577         * rl78-decode.opc: Likewise.
 578         * msp430-decode.c: Regenerate.
 579         * rl78-decode.c: Regenerate.
 580
 581 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 582
 583         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 584         * i386-init.h : Regenerated.
 585
 586 2018-05-25  Alan Modra  <amodra@gmail.com>
 587
 588         * Makefile.in: Regenerate.
 589         * po/POTFILES.in: Regenerate.
 590
 591 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 592
 593         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 594         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 595         (insert_bab, extract_bab, insert_btab, extract_btab,
 596         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 597         (BAT, BBA VBA RBS XB6S): Delete macros.
 598         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 599         (BB, BD, RBX, XC6): Update for new macros.
 600         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 601         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 602         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 603         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 604
 605 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 606
 607         * Makefile.am: Add support for s12z architecture.
 608         * configure.ac: Likewise.
 609         * disassemble.c: Likewise.
 610         * disassemble.h: Likewise.
 611         * Makefile.in: Regenerate.
 612         * configure: Regenerate.
 613         * s12z-dis.c: New file.
 614         * s12z.h: New file.
 615
 616 2018-05-18  Alan Modra  <amodra@gmail.com>
 617
 618         * nfp-dis.c: Don't #include libbfd.h.
 619         (init_nfp3200_priv): Use bfd_get_section_contents.
 620         (nit_nfp6000_mecsr_sec): Likewise.
 621
 622 2018-05-17  Nick Clifton  <nickc@redhat.com>
 623
 624         * po/zh_CN.po: Updated simplified Chinese translation.
 625
 626 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 627
 628         PR binutils/23109
 629         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 630         * aarch64-dis-2.c: Regenerate.
 631
 632 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 633
 634         PR binutils/21446
 635         * aarch64-asm.c (opintl.h): Include.
 636         (aarch64_ins_sysreg): Enforce read/write constraints.
 637         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 638         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 639         (F_REG_READ, F_REG_WRITE): New.
 640         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 641         AARCH64_OPND_SYSREG.
 642         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 643         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 644         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 645         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 646         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 647         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 648         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 649         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 650         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 651         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 652         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 653         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 654         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 655         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 656         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 657         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 658         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 659
 660 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 661
 662         PR binutils/21446
 663         * aarch64-dis.c (no_notes: New.
 664         (parse_aarch64_dis_option): Support notes.
 665         (aarch64_decode_insn, print_operands): Likewise.
 666         (print_aarch64_disassembler_options): Document notes.
 667         * aarch64-opc.c (aarch64_print_operand): Support notes.
 668
 669 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 670
 671         PR binutils/21446
 672         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 673         and take error struct.
 674         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 675         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 676         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 677         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 678         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 679         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 680         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 681         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 682         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 683         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 684         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 685         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 686         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 687         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 688         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 689         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 690         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 691         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 692         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 693         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 694         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 695         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 696         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 697         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 698         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 699         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 700         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 701         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 702         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 703         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 704         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 705         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 706         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 707         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 708         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 709         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 710         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 711         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 712         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 713         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 714         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 715         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 716         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 717         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 718         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 719         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 720         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 721         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 722         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 723         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 724         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 725         (determine_disassembling_preference, aarch64_decode_insn,
 726         print_insn_aarch64_word, print_insn_data): Take errors struct.
 727         (print_insn_aarch64): Use errors.
 728         * aarch64-asm-2.c: Regenerate.
 729         * aarch64-dis-2.c: Regenerate.
 730         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 731         boolean in aarch64_insert_operan.
 732         (print_operand_extractor): Likewise.
 733         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 734
 735 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 736
 737         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 738
 739 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 740
 741         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 742
 743 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 744
 745         * cr16-opc.c (cr16_instruction): Comment typo fix.
 746         * hppa-dis.c (print_insn_hppa): Likewise.
 747
 748 2018-05-08  Jim Wilson  <jimw@sifive.com>
 749
 750         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 751         (match_c_slli64, match_srxi_as_c_srxi): New.
 752         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 753         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 754         <c.slli, c.srli, c.srai>: Use match_s_slli.
 755         <c.slli64, c.srli64, c.srai64>: New.
 756
 757 2018-05-08  Alan Modra  <amodra@gmail.com>
 758
 759         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 760         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 761         partition opcode space for index lookup.
 762
 763 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 764
 765         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 766         <insn_length>: ...with this.  Update usage.
 767         Remove duplicate call to *info->memory_error_func.
 768
 769 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 770             H.J. Lu  <hongjiu.lu@intel.com>
 771
 772         * i386-dis.c (Gva): New.
 773         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 774         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 775         (prefix_table): New instructions (see prefix above).
 776         (mod_table): New instructions (see prefix above).
 777         (OP_G): Handle va_mode.
 778         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 779         CPU_MOVDIR64B_FLAGS.
 780         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 781         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 782         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 783         * i386-opc.tbl: Add movidir{i,64b}.
 784         * i386-init.h: Regenerated.
 785         * i386-tbl.h: Likewise.
 786
 787 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 788
 789         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 790         AddrPrefixOpReg.
 791         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 792         (AddrPrefixOpReg): This.
 793         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 794         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 795
 796 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 797
 798         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 799         (vle_num_opcodes): Likewise.
 800         (spe2_num_opcodes): Likewise.
 801         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 802         initialization loop.
 803         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 804         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 805         only once.
 806
 807 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 808
 809         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 810
 811 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 812
 813         Makefile.am: Added nfp-dis.c.
 814         configure.ac: Added bfd_nfp_arch.
 815         disassemble.h: Added print_insn_nfp prototype.
 816         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 817         nfp-dis.c: New, for NFP support.
 818         po/POTFILES.in: Added nfp-dis.c to the list.
 819         Makefile.in: Regenerate.
 820         configure: Regenerate.
 821
 822 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 823
 824         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 825         templates into their base ones.
 826         * i386-tlb.h: Re-generate.
 827
 828 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 829
 830         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 831         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 832         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 833         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 834         * i386-init.h: Re-generate.
 835
 836 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 839         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 840         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 841         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 842         comment.
 843         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 844         and CpuRegMask.
 845         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 846         CpuRegMask: Delete.
 847         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 848         cpuregzmm, and cpuregmask.
 849         * i386-init.h: Re-generate.
 850         * i386-tbl.h: Re-generate.
 851
 852 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 853
 854         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 855         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 856         * i386-init.h: Re-generate.
 857
 858 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 859
 860         * i386-gen.c (VexImmExt): Delete.
 861         * i386-opc.h (VexImmExt, veximmext): Delete.
 862         * i386-opc.tbl: Drop all VexImmExt uses.
 863         * i386-tlb.h: Re-generate.
 864
 865 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 866
 867         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 868         register-only forms.
 869         * i386-tlb.h: Re-generate.
 870
 871 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 872
 873         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 874
 875 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 876
 877         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 878         PREFIX_0F1C.
 879         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 880         (cpu_flags): Add CpuCLDEMOTE.
 881         * i386-init.h: Regenerate.
 882         * i386-opc.h (enum): Add CpuCLDEMOTE,
 883         (i386_cpu_flags): Add cpucldemote.
 884         * i386-opc.tbl: Add cldemote.
 885         * i386-tbl.h: Regenerate.
 886
 887 2018-04-16  Alan Modra  <amodra@gmail.com>
 888
 889         * Makefile.am: Remove sh5 and sh64 support.
 890         * configure.ac: Likewise.
 891         * disassemble.c: Likewise.
 892         * disassemble.h: Likewise.
 893         * sh-dis.c: Likewise.
 894         * sh64-dis.c: Delete.
 895         * sh64-opc.c: Delete.
 896         * sh64-opc.h: Delete.
 897         * Makefile.in: Regenerate.
 898         * configure: Regenerate.
 899         * po/POTFILES.in: Regenerate.
 900
 901 2018-04-16  Alan Modra  <amodra@gmail.com>
 902
 903         * Makefile.am: Remove w65 support.
 904         * configure.ac: Likewise.
 905         * disassemble.c: Likewise.
 906         * disassemble.h: Likewise.
 907         * w65-dis.c: Delete.
 908         * w65-opc.h: Delete.
 909         * Makefile.in: Regenerate.
 910         * configure: Regenerate.
 911         * po/POTFILES.in: Regenerate.
 912
 913 2018-04-16  Alan Modra  <amodra@gmail.com>
 914
 915         * configure.ac: Remove we32k support.
 916         * configure: Regenerate.
 917
 918 2018-04-16  Alan Modra  <amodra@gmail.com>
 919
 920         * Makefile.am: Remove m88k support.
 921         * configure.ac: Likewise.
 922         * disassemble.c: Likewise.
 923         * disassemble.h: Likewise.
 924         * m88k-dis.c: Delete.
 925         * Makefile.in: Regenerate.
 926         * configure: Regenerate.
 927         * po/POTFILES.in: Regenerate.
 928
 929 2018-04-16  Alan Modra  <amodra@gmail.com>
 930
 931         * Makefile.am: Remove i370 support.
 932         * configure.ac: Likewise.
 933         * disassemble.c: Likewise.
 934         * disassemble.h: Likewise.
 935         * i370-dis.c: Delete.
 936         * i370-opc.c: Delete.
 937         * Makefile.in: Regenerate.
 938         * configure: Regenerate.
 939         * po/POTFILES.in: Regenerate.
 940
 941 2018-04-16  Alan Modra  <amodra@gmail.com>
 942
 943         * Makefile.am: Remove h8500 support.
 944         * configure.ac: Likewise.
 945         * disassemble.c: Likewise.
 946         * disassemble.h: Likewise.
 947         * h8500-dis.c: Delete.
 948         * h8500-opc.h: Delete.
 949         * Makefile.in: Regenerate.
 950         * configure: Regenerate.
 951         * po/POTFILES.in: Regenerate.
 952
 953 2018-04-16  Alan Modra  <amodra@gmail.com>
 954
 955         * configure.ac: Remove tahoe support.
 956         * configure: Regenerate.
 957
 958 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 959
 960         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 961         umwait.
 962         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 963         64-bit mode.
 964         * i386-tbl.h: Regenerated.
 965
 966 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 967
 968         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 969         PREFIX_MOD_1_0FAE_REG_6.
 970         (va_mode): New.
 971         (OP_E_register): Use va_mode.
 972         * i386-dis-evex.h (prefix_table):
 973         New instructions (see prefixes above).
 974         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 975         (cpu_flags): Likewise.
 976         * i386-opc.h (enum): Likewise.
 977         (i386_cpu_flags): Likewise.
 978         * i386-opc.tbl: Add umonitor, umwait, tpause.
 979         * i386-init.h: Regenerate.
 980         * i386-tbl.h: Likewise.
 981
 982 2018-04-11  Alan Modra  <amodra@gmail.com>
 983
 984         * opcodes/i860-dis.c: Delete.
 985         * opcodes/i960-dis.c: Delete.
 986         * Makefile.am: Remove i860 and i960 support.
 987         * configure.ac: Likewise.
 988         * disassemble.c: Likewise.
 989         * disassemble.h: Likewise.
 990         * Makefile.in: Regenerate.
 991         * configure: Regenerate.
 992         * po/POTFILES.in: Regenerate.
 993
 994 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 995
 996         PR binutils/23025
 997         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 998         to 0.
 999         (print_insn): Clear vex instead of vex.evex.
1000
1001 2018-04-04  Nick Clifton  <nickc@redhat.com>
1002
1003         * po/es.po: Updated Spanish translation.
1004
1005 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1006
1007         * i386-gen.c (opcode_modifiers): Delete VecESize.
1008         * i386-opc.h (VecESize): Delete.
1009         (struct i386_opcode_modifier): Delete vecesize.
1010         * i386-opc.tbl: Drop VecESize.
1011         * i386-tlb.h: Re-generate.
1012
1013 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1014
1015         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1016         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1017         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1018         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1019         * i386-tlb.h: Re-generate.
1020
1021 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1022
1023         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1024         Fold AVX512 forms
1025         * i386-tlb.h: Re-generate.
1026
1027 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1030         (vex_len_table): Drop Y for vcvt*2si.
1031         (putop): Replace plain 'Y' handling by abort().
1032
1033 2018-03-28  Nick Clifton  <nickc@redhat.com>
1034
1035         PR 22988
1036         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1037         instructions with only a base address register.
1038         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1039         handle AARHC64_OPND_SVE_ADDR_R.
1040         (aarch64_print_operand): Likewise.
1041         * aarch64-asm-2.c: Regenerate.
1042         * aarch64_dis-2.c: Regenerate.
1043         * aarch64-opc-2.c: Regenerate.
1044
1045 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1046
1047         * i386-opc.tbl: Drop VecESize from register only insn forms and
1048         memory forms not allowing broadcast.
1049         * i386-tlb.h: Re-generate.
1050
1051 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1052
1053         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1054         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1055         sha256*): Drop Disp<N>.
1056
1057 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1058
1059         * i386-dis.c (EbndS, bnd_swap_mode): New.
1060         (prefix_table): Use EbndS.
1061         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1062         * i386-opc.tbl (bndmov): Move misplaced Load.
1063         * i386-tlb.h: Re-generate.
1064
1065 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1066
1067         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1068         templates allowing memory operands and folded ones for register
1069         only flavors.
1070         * i386-tlb.h: Re-generate.
1071
1072 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1075         256-bit templates. Drop redundant leftover Disp<N>.
1076         * i386-tlb.h: Re-generate.
1077
1078 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1079
1080         * riscv-opc.c (riscv_insn_types): New.
1081
1082 2018-03-13  Nick Clifton  <nickc@redhat.com>
1083
1084         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1085
1086 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1087
1088         * i386-opc.tbl: Add Optimize to clr.
1089         * i386-tbl.h: Regenerated.
1090
1091 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1092
1093         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1094         * i386-opc.h (OldGcc): Removed.
1095         (i386_opcode_modifier): Remove oldgcc.
1096         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1097         instructions for old (<= 2.8.1) versions of gcc.
1098         * i386-tbl.h: Regenerated.
1099
1100 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1101
1102         * i386-opc.h (EVEXDYN): New.
1103         * i386-opc.tbl: Fold various AVX512VL templates.
1104         * i386-tlb.h: Re-generate.
1105
1106 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1107
1108         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1109         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1110         vpexpandd, vpexpandq): Fold AFX512VF templates.
1111         * i386-tlb.h: Re-generate.
1112
1113 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1114
1115         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1116         Fold 128- and 256-bit VEX-encoded templates.
1117         * i386-tlb.h: Re-generate.
1118
1119 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1120
1121         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1122         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1123         vpexpandd, vpexpandq): Fold AVX512F templates.
1124         * i386-tlb.h: Re-generate.
1125
1126 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1127
1128         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1129         64-bit templates. Drop Disp<N>.
1130         * i386-tlb.h: Re-generate.
1131
1132 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1135         and 256-bit templates.
1136         * i386-tlb.h: Re-generate.
1137
1138 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1139
1140         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1141         * i386-tlb.h: Re-generate.
1142
1143 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1144
1145         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1146         Drop NoAVX.
1147         * i386-tlb.h: Re-generate.
1148
1149 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1150
1151         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1152         * i386-tlb.h: Re-generate.
1153
1154 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1155
1156         * i386-gen.c (opcode_modifiers): Delete FloatD.
1157         * i386-opc.h (FloatD): Delete.
1158         (struct i386_opcode_modifier): Delete floatd.
1159         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1160         FloatD by D.
1161         * i386-tlb.h: Re-generate.
1162
1163 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1164
1165         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1166
1167 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1168
1169         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1170         * i386-tlb.h: Re-generate.
1171
1172 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1173
1174         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1175         forms.
1176         * i386-tlb.h: Re-generate.
1177
1178 2018-03-07  Alan Modra  <amodra@gmail.com>
1179
1180         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1181         bfd_arch_rs6000.
1182         * disassemble.h (print_insn_rs6000): Delete.
1183         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1184         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1185         (print_insn_rs6000): Delete.
1186
1187 2018-03-03  Alan Modra  <amodra@gmail.com>
1188
1189         * sysdep.h (opcodes_error_handler): Define.
1190         (_bfd_error_handler): Declare.
1191         * Makefile.am: Remove stray #.
1192         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1193         EDIT" comment.
1194         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1195         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1196         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1197         opcodes_error_handler to print errors.  Standardize error messages.
1198         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1199         and include opintl.h.
1200         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1201         * i386-gen.c: Standardize error messages.
1202         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1203         * Makefile.in: Regenerate.
1204         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1205         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1206         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1207         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1208         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1209         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1210         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1211         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1212         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1213         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1214         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1215         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1216         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1217
1218 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1219
1220         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1221         vpsub[bwdq] instructions.
1222         * i386-tbl.h: Regenerated.
1223
1224 2018-03-01  Alan Modra  <amodra@gmail.com>
1225
1226         * configure.ac (ALL_LINGUAS): Sort.
1227         * configure: Regenerate.
1228
1229 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1230
1231         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1232         macro by assignements.
1233
1234 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1235
1236         PR gas/22871
1237         * i386-gen.c (opcode_modifiers): Add Optimize.
1238         * i386-opc.h (Optimize): New enum.
1239         (i386_opcode_modifier): Add optimize.
1240         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1241         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1242         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1243         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1244         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1245         vpxord and vpxorq.
1246         * i386-tbl.h: Regenerated.
1247
1248 2018-02-26  Alan Modra  <amodra@gmail.com>
1249
1250         * crx-dis.c (getregliststring): Allocate a large enough buffer
1251         to silence false positive gcc8 warning.
1252
1253 2018-02-22  Shea Levy <shea@shealevy.com>
1254
1255         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1256
1257 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1258
1259         * i386-opc.tbl: Add {rex},
1260         * i386-tbl.h: Regenerated.
1261
1262 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1263
1264         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1265         (mips16_opcodes): Replace `M' with `m' for "restore".
1266
1267 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1268
1269         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1270
1271 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1272
1273         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1274         variable to `function_index'.
1275
1276 2018-02-13  Nick Clifton  <nickc@redhat.com>
1277
1278         PR 22823
1279         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1280         about truncation of printing.
1281
1282 2018-02-12  Henry Wong <henry@stuffedcow.net>
1283
1284         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1285
1286 2018-02-05  Nick Clifton  <nickc@redhat.com>
1287
1288         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1289
1290 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1291
1292         * i386-dis.c (enum): Add pconfig.
1293         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1294         (cpu_flags): Add CpuPCONFIG.
1295         * i386-opc.h (enum): Add CpuPCONFIG.
1296         (i386_cpu_flags): Add cpupconfig.
1297         * i386-opc.tbl: Add PCONFIG instruction.
1298         * i386-init.h: Regenerate.
1299         * i386-tbl.h: Likewise.
1300
1301 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1302
1303         * i386-dis.c (enum): Add PREFIX_0F09.
1304         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1305         (cpu_flags): Add CpuWBNOINVD.
1306         * i386-opc.h (enum): Add CpuWBNOINVD.
1307         (i386_cpu_flags): Add cpuwbnoinvd.
1308         * i386-opc.tbl: Add WBNOINVD instruction.
1309         * i386-init.h: Regenerate.
1310         * i386-tbl.h: Likewise.
1311
1312 2018-01-17  Jim Wilson  <jimw@sifive.com>
1313
1314         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1315
1316 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1317
1318         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1319         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1320         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1321         (cpu_flags): Add CpuIBT, CpuSHSTK.
1322         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1323         (i386_cpu_flags): Add cpuibt, cpushstk.
1324         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1325         * i386-init.h: Regenerate.
1326         * i386-tbl.h: Likewise.
1327
1328 2018-01-16  Nick Clifton  <nickc@redhat.com>
1329
1330         * po/pt_BR.po: Updated Brazilian Portugese translation.
1331         * po/de.po: Updated German translation.
1332
1333 2018-01-15  Jim Wilson  <jimw@sifive.com>
1334
1335         * riscv-opc.c (match_c_nop): New.
1336         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1337
1338 2018-01-15  Nick Clifton  <nickc@redhat.com>
1339
1340         * po/uk.po: Updated Ukranian translation.
1341
1342 2018-01-13  Nick Clifton  <nickc@redhat.com>
1343
1344         * po/opcodes.pot: Regenerated.
1345
1346 2018-01-13  Nick Clifton  <nickc@redhat.com>
1347
1348         * configure: Regenerate.
1349
1350 2018-01-13  Nick Clifton  <nickc@redhat.com>
1351
1352         2.30 branch created.
1353
1354 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1355
1356         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1357         * i386-tbl.h: Regenerate.
1358
1359 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1360
1361         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1362         * i386-tbl.h: Re-generate.
1363
1364 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1365
1366         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1367         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1368         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1369         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1370         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1371         Disp8MemShift of AVX512VL forms.
1372         * i386-tbl.h: Re-generate.
1373
1374 2018-01-09  Jim Wilson  <jimw@sifive.com>
1375
1376         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1377         then the hi_addr value is zero.
1378
1379 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1380
1381         * arm-dis.c (arm_opcodes): Add csdb.
1382         (thumb32_opcodes): Add csdb.
1383
1384 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1385
1386         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1387         * aarch64-asm-2.c: Regenerate.
1388         * aarch64-dis-2.c: Regenerate.
1389         * aarch64-opc-2.c: Regenerate.
1390
1391 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1392
1393         PR gas/22681
1394         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1395         Remove AVX512 vmovd with 64-bit operands.
1396         * i386-tbl.h: Regenerated.
1397
1398 2018-01-05  Jim Wilson  <jimw@sifive.com>
1399
1400         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1401         jalr.
1402
1403 2018-01-03  Alan Modra  <amodra@gmail.com>
1404
1405         Update year range in copyright notice of all files.
1406
1407 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1408
1409         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1410         and OPERAND_TYPE_REGZMM entries.
1411
1412 For older changes see ChangeLog-2017
1413 \f
1414 Copyright (C) 2018 Free Software Foundation, Inc.
1415
1416 Copying and distribution of this file, with or without modification,
1417 are permitted in any medium without royalty provided the copyright
1418 notice and this notice are preserved.
1419
1420 Local Variables:
1421 mode: change-log
1422 left-margin: 8
1423 fill-column: 74
1424 version-control: never
1425 End: