opcodes/ChangeLog

   1 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
   2             Michael Collison <michael.collison@arm.com>
   3
   4         * arm-dis.c (enum mve_instructions): Add new instructions.
   5         (is_mve_encoding_conflict): Handle new instructions.
   6         (is_mve_undefined): Likewise.
   7         (is_mve_unpredictable): Likewise.
   8         (print_mve_size): Likewise.
   9         (print_insn_mve): Likewise.
  10
  11 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  12             Michael Collison <michael.collison@arm.com>
  13
  14         * arm-dis.c (enum mve_instructions): Add new instructions.
  15         (enum mve_unpredictable): Add new reasons.
  16         (enum mve_undefined): Likewise.
  17         (is_mve_okay_in_it): Handle new isntructions.
  18         (is_mve_encoding_conflict): Likewise.
  19         (is_mve_undefined): Likewise.
  20         (is_mve_unpredictable): Likewise.
  21         (print_mve_vmov_index): Likewise.
  22         (print_simd_imm8): Likewise.
  23         (print_mve_undefined): Likewise.
  24         (print_mve_unpredictable): Likewise.
  25         (print_mve_size): Likewise.
  26         (print_insn_mve): Likewise.
  27
  28 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  29             Michael Collison <michael.collison@arm.com>
  30
  31         * arm-dis.c (enum mve_instructions): Add new instructions.
  32         (enum mve_unpredictable): Add new reasons.
  33         (enum mve_undefined): Likewise.
  34         (is_mve_encoding_conflict): Handle new instructions.
  35         (is_mve_undefined): Likewise.
  36         (is_mve_unpredictable): Likewise.
  37         (print_mve_undefined): Likewise.
  38         (print_mve_unpredictable): Likewise.
  39         (print_mve_rounding_mode): Likewise.
  40         (print_mve_vcvt_size): Likewise.
  41         (print_mve_size): Likewise.
  42         (print_insn_mve): Likewise.
  43
  44 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  45             Michael Collison <michael.collison@arm.com>
  46
  47         * arm-dis.c (enum mve_instructions): Add new instructions.
  48         (enum mve_unpredictable): Add new reasons.
  49         (enum mve_undefined): Likewise.
  50         (is_mve_undefined): Handle new instructions.
  51         (is_mve_unpredictable): Likewise.
  52         (print_mve_undefined): Likewise.
  53         (print_mve_unpredictable): Likewise.
  54         (print_mve_size): Likewise.
  55         (print_insn_mve): Likewise.
  56
  57 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  58             Michael Collison <michael.collison@arm.com>
  59
  60         * arm-dis.c (enum mve_instructions): Add new instructions.
  61         (enum mve_undefined): Add new reasons.
  62         (insns): Add new instructions.
  63         (is_mve_encoding_conflict):
  64         (print_mve_vld_str_addr): New print function.
  65         (is_mve_undefined): Handle new instructions.
  66         (is_mve_unpredictable): Likewise.
  67         (print_mve_undefined): Likewise.
  68         (print_mve_size): Likewise.
  69         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
  70         (print_insn_mve):  Handle new operands.
  71
  72 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  73             Michael Collison <michael.collison@arm.com>
  74
  75         * arm-dis.c (enum mve_instructions): Add new instructions.
  76         (enum mve_unpredictable): Add new reasons.
  77         (is_mve_encoding_conflict): Handle new instructions.
  78         (is_mve_unpredictable): Likewise.
  79         (mve_opcodes): Add new instructions.
  80         (print_mve_unpredictable): Handle new reasons.
  81         (print_mve_register_blocks): New print function.
  82         (print_mve_size): Handle new instructions.
  83         (print_insn_mve): Likewise.
  84
  85 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  86             Michael Collison <michael.collison@arm.com>
  87
  88         * arm-dis.c (enum mve_instructions): Add new instructions.
  89         (enum mve_unpredictable): Add new reasons.
  90         (enum mve_undefined): Likewise.
  91         (is_mve_encoding_conflict): Handle new instructions.
  92         (is_mve_undefined): Likewise.
  93         (is_mve_unpredictable): Likewise.
  94         (coprocessor_opcodes): Move NEON VDUP from here...
  95         (neon_opcodes): ... to here.
  96         (mve_opcodes): Add new instructions.
  97         (print_mve_undefined):  Handle new reasons.
  98         (print_mve_unpredictable): Likewise.
  99         (print_mve_size): Handle new instructions.
 100         (print_insn_neon): Handle vdup.
 101         (print_insn_mve): Handle new operands.
 102
 103 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 104             Michael Collison <michael.collison@arm.com>
 105
 106         * arm-dis.c (enum mve_instructions): Add new instructions.
 107         (enum mve_unpredictable): Add new values.
 108         (mve_opcodes): Add new instructions.
 109         (vec_condnames): New array with vector conditions.
 110         (mve_predicatenames): New array with predicate suffixes.
 111         (mve_vec_sizename): New array with vector sizes.
 112         (enum vpt_pred_state): New enum with vector predication states.
 113         (struct vpt_block): New struct type for vpt blocks.
 114         (vpt_block_state): Global struct to keep track of state.
 115         (mve_extract_pred_mask): New helper function.
 116         (num_instructions_vpt_block): Likewise.
 117         (mark_outside_vpt_block): Likewise.
 118         (mark_inside_vpt_block): Likewise.
 119         (invert_next_predicate_state): Likewise.
 120         (update_next_predicate_state): Likewise.
 121         (update_vpt_block_state): Likewise.
 122         (is_vpt_instruction): Likewise.
 123         (is_mve_encoding_conflict): Add entries for new instructions.
 124         (is_mve_unpredictable): Likewise.
 125         (print_mve_unpredictable): Handle new cases.
 126         (print_instruction_predicate): Likewise.
 127         (print_mve_size): New function.
 128         (print_vec_condition): New function.
 129         (print_insn_mve): Handle vpt blocks and new print operands.
 130
 131 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 132
 133         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 134         8, 14 and 15 for Armv8.1-M Mainline.
 135
 136 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 137             Michael Collison <michael.collison@arm.com>
 138
 139         * arm-dis.c (enum mve_instructions): New enum.
 140         (enum mve_unpredictable): Likewise.
 141         (enum mve_undefined): Likewise.
 142         (struct mopcode32): New struct.
 143         (is_mve_okay_in_it): New function.
 144         (is_mve_architecture): Likewise.
 145         (arm_decode_field): Likewise.
 146         (arm_decode_field_multiple): Likewise.
 147         (is_mve_encoding_conflict): Likewise.
 148         (is_mve_undefined): Likewise.
 149         (is_mve_unpredictable): Likewise.
 150         (print_mve_undefined): Likewise.
 151         (print_mve_unpredictable): Likewise.
 152         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 153         (print_insn_mve): New function.
 154         (print_insn_thumb32): Handle MVE architecture.
 155         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 156
 157 2019-05-10  Nick Clifton  <nickc@redhat.com>
 158
 159         PR 24538
 160         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 161         end of the table prematurely.
 162
 163 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 164
 165         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 166         macros for R6.
 167
 168 2019-05-11  Alan Modra  <amodra@gmail.com>
 169
 170         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 171         when -Mraw is in effect.
 172
 173 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 174
 175         * aarch64-dis-2.c: Regenerate.
 176         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 177         (OP_SVE_BBB): New variant set.
 178         (OP_SVE_DDDD): New variant set.
 179         (OP_SVE_HHH): New variant set.
 180         (OP_SVE_HHHU): New variant set.
 181         (OP_SVE_SSS): New variant set.
 182         (OP_SVE_SSSU): New variant set.
 183         (OP_SVE_SHH): New variant set.
 184         (OP_SVE_SBBU): New variant set.
 185         (OP_SVE_DSS): New variant set.
 186         (OP_SVE_DHHU): New variant set.
 187         (OP_SVE_VMV_HSD_BHS): New variant set.
 188         (OP_SVE_VVU_HSD_BHS): New variant set.
 189         (OP_SVE_VVVU_SD_BH): New variant set.
 190         (OP_SVE_VVVU_BHSD): New variant set.
 191         (OP_SVE_VVV_QHD_DBS): New variant set.
 192         (OP_SVE_VVV_HSD_BHS): New variant set.
 193         (OP_SVE_VVV_HSD_BHS2): New variant set.
 194         (OP_SVE_VVV_BHS_HSD): New variant set.
 195         (OP_SVE_VV_BHS_HSD): New variant set.
 196         (OP_SVE_VVV_SD): New variant set.
 197         (OP_SVE_VVU_BHS_HSD): New variant set.
 198         (OP_SVE_VZVV_SD): New variant set.
 199         (OP_SVE_VZVV_BH): New variant set.
 200         (OP_SVE_VZV_SD): New variant set.
 201         (aarch64_opcode_table): Add sve2 instructions.
 202
 203 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 204
 205         * aarch64-asm-2.c: Regenerated.
 206         * aarch64-dis-2.c: Regenerated.
 207         * aarch64-opc-2.c: Regenerated.
 208         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 209         for SVE_SHLIMM_UNPRED_22.
 210         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 211         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 212         operand.
 213
 214 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 215
 216         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 217         sve_size_tsz_bhs iclass encode.
 218         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 219         sve_size_tsz_bhs iclass decode.
 220
 221 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 222
 223         * aarch64-asm-2.c: Regenerated.
 224         * aarch64-dis-2.c: Regenerated.
 225         * aarch64-opc-2.c: Regenerated.
 226         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 227         for SVE_Zm4_11_INDEX.
 228         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 229         (fields): Handle SVE_i2h field.
 230         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 231         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 232
 233 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 234
 235         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 236         sve_shift_tsz_bhsd iclass encode.
 237         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 238         sve_shift_tsz_bhsd iclass decode.
 239
 240 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 241
 242         * aarch64-asm-2.c: Regenerated.
 243         * aarch64-dis-2.c: Regenerated.
 244         * aarch64-opc-2.c: Regenerated.
 245         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 246         (aarch64_encode_variant_using_iclass): Handle
 247         sve_shift_tsz_hsd iclass encode.
 248         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 249         sve_shift_tsz_hsd iclass decode.
 250         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 251         for SVE_SHRIMM_UNPRED_22.
 252         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 253         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 254         operand.
 255
 256 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 257
 258         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 259         sve_size_013 iclass encode.
 260         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 261         sve_size_013 iclass decode.
 262
 263 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 264
 265         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 266         sve_size_bh iclass encode.
 267         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 268         sve_size_bh iclass decode.
 269
 270 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 271
 272         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 273         sve_size_sd2 iclass encode.
 274         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 275         sve_size_sd2 iclass decode.
 276         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 277         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 278
 279 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 280
 281         * aarch64-asm-2.c: Regenerated.
 282         * aarch64-dis-2.c: Regenerated.
 283         * aarch64-opc-2.c: Regenerated.
 284         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 285         for SVE_ADDR_ZX.
 286         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 287         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 288
 289 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 290
 291         * aarch64-asm-2.c: Regenerated.
 292         * aarch64-dis-2.c: Regenerated.
 293         * aarch64-opc-2.c: Regenerated.
 294         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 295         for SVE_Zm3_11_INDEX.
 296         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 297         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 298         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 299         fields.
 300         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 301
 302 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 303
 304         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 305         sve_size_hsd2 iclass encode.
 306         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 307         sve_size_hsd2 iclass decode.
 308         * aarch64-opc.c (fields): Handle SVE_size field.
 309         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 310
 311 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 312
 313         * aarch64-asm-2.c: Regenerated.
 314         * aarch64-dis-2.c: Regenerated.
 315         * aarch64-opc-2.c: Regenerated.
 316         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 317         for SVE_IMM_ROT3.
 318         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 319         (fields): Handle SVE_rot3 field.
 320         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 321         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 322
 323 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 324
 325         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 326         instructions.
 327
 328 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 329
 330         * aarch64-tbl.h
 331         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 332         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 333         aarch64_feature_sve2bitperm): New feature sets.
 334         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 335         for feature set addresses.
 336         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 337         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 338
 339 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 340             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 341
 342         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 343         argument and set ASE_EVA_R6 appropriately.
 344         (set_default_mips_dis_options): Pass ISA to above.
 345         (parse_mips_dis_option): Likewise.
 346         * mips-opc.c (EVAR6): New macro.
 347         (mips_builtin_opcodes): Add llwpe, scwpe.
 348
 349 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 350
 351         * aarch64-asm-2.c: Regenerated.
 352         * aarch64-dis-2.c: Regenerated.
 353         * aarch64-opc-2.c: Regenerated.
 354         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 355         AARCH64_OPND_TME_UIMM16.
 356         (aarch64_print_operand): Likewise.
 357         * aarch64-tbl.h (QL_IMM_NIL): New.
 358         (TME): New.
 359         (_TME_INSN): New.
 360         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 361
 362 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 363
 364         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 365
 366 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 367             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 368
 369         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 370
 371 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 372
 373         * s12z-opc.h: Add extern "C" bracketing to help
 374         users who wish to use this interface in c++ code.
 375
 376 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 377
 378         * s12z-opc.c (bm_decode): Handle bit map operations with the
 379         "reserved0" mode.
 380
 381 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 382
 383         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 384         specifier.  Add entries for VLDR and VSTR of system registers.
 385         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 386         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 387         of %J and %K format specifier.
 388
 389 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 390
 391         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 392         Add new entries for VSCCLRM instruction.
 393         (print_insn_coprocessor): Handle new %C format control code.
 394
 395 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 396
 397         * arm-dis.c (enum isa): New enum.
 398         (struct sopcode32): New structure.
 399         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 400         set isa field of all current entries to ANY.
 401         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 402         Only match an entry if its isa field allows the current mode.
 403
 404 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 405
 406         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 407         CLRM.
 408         (print_insn_thumb32): Add logic to print %n CLRM register list.
 409
 410 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 411
 412         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 413         and %Q patterns.
 414
 415 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 416
 417         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 418         (print_insn_thumb32): Edit the switch case for %Z.
 419
 420 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 421
 422         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 423
 424 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 425
 426         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 427
 428 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 429
 430         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 431
 432 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 433
 434         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 435         Arm register with r13 and r15 unpredictable.
 436         (thumb32_opcodes): New instructions for bfx and bflx.
 437
 438 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 439
 440         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 441
 442 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 443
 444         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 445
 446 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 447
 448         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 449
 450 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 451
 452         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 453
 454 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 455
 456         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 457         "optr". ("operator" is a reserved word in c++).
 458
 459 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 460
 461         * aarch64-opc.c (aarch64_print_operand): Add case for
 462         AARCH64_OPND_Rt_SP.
 463         (verify_constraints): Likewise.
 464         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 465         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 466         to accept Rt|SP as first operand.
 467         (AARCH64_OPERANDS): Add new Rt_SP.
 468         * aarch64-asm-2.c: Regenerated.
 469         * aarch64-dis-2.c: Regenerated.
 470         * aarch64-opc-2.c: Regenerated.
 471
 472 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 473
 474         * aarch64-asm-2.c: Regenerated.
 475         * aarch64-dis-2.c: Likewise.
 476         * aarch64-opc-2.c: Likewise.
 477         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 478
 479 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 480
 481         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 482
 483 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 484
 485         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 486         * i386-init.h: Regenerated.
 487
 488 2019-04-07  Alan Modra  <amodra@gmail.com>
 489
 490         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 491         op_separator to control printing of spaces, comma and parens
 492         rather than need_comma, need_paren and spaces vars.
 493
 494 2019-04-07  Alan Modra  <amodra@gmail.com>
 495
 496         PR 24421
 497         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 498         (print_insn_neon, print_insn_arm): Likewise.
 499
 500 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 501
 502         * i386-dis-evex.h (evex_table): Updated to support BF16
 503         instructions.
 504         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 505         and EVEX_W_0F3872_P_3.
 506         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 507         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 508         * i386-opc.h (enum): Add CpuAVX512_BF16.
 509         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 510         * i386-opc.tbl: Add AVX512 BF16 instructions.
 511         * i386-init.h: Regenerated.
 512         * i386-tbl.h: Likewise.
 513
 514 2019-04-05  Alan Modra  <amodra@gmail.com>
 515
 516         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 517         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 518         to favour printing of "-" branch hint when using the "y" bit.
 519         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 520
 521 2019-04-05  Alan Modra  <amodra@gmail.com>
 522
 523         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 524         opcode until first operand is output.
 525
 526 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 527
 528         PR gas/24349
 529         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 530         (valid_bo_post_v2): Add support for 'at' branch hints.
 531         (insert_bo): Only error on branch on ctr.
 532         (get_bo_hint_mask): New function.
 533         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 534         for inserting 'at' branch hints.
 535         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 536         for extracting 'at' branch hints.
 537         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 538         (BOE): Delete operand.
 539         (BOM, BOP): New operands.
 540         (RM): Update value.
 541         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 542         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 543         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 544         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 545         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 546         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 547         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 548         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 549         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 550         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 551         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 552         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 553         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 554         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 555         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 556         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 557         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 558         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 559         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 560         bttarl+>: New extended mnemonics.
 561
 562 2019-03-28  Alan Modra  <amodra@gmail.com>
 563
 564         PR 24390
 565         * ppc-opc.c (BTF): Define.
 566         (powerpc_opcodes): Use for mtfsb*.
 567         * ppc-dis.c (print_insn_powerpc): Print fields with both
 568         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 569
 570 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 571
 572         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 573         (mapping_symbol_for_insn): Implement new algorithm.
 574         (print_insn): Remove duplicate code.
 575
 576 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 577
 578         * aarch64-dis.c (print_insn_aarch64):
 579         Implement override.
 580
 581 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 582
 583         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 584         order.
 585
 586 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 587
 588         * aarch64-dis.c (last_stop_offset): New.
 589         (print_insn_aarch64): Use stop_offset.
 590
 591 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 592
 593         PR gas/24359
 594         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 595         CPU_ANY_AVX2_FLAGS.
 596         * i386-init.h: Regenerated.
 597
 598 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 599
 600         PR gas/24348
 601         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 602         vmovdqu16, vmovdqu32 and vmovdqu64.
 603         * i386-tbl.h: Regenerated.
 604
 605 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 606
 607         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 608         from vstrszb, vstrszh, and vstrszf.
 609
 610 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 611
 612         * s390-opc.txt: Add instruction descriptions.
 613
 614 2019-02-08  Jim Wilson  <jimw@sifive.com>
 615
 616         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 617         <bne>: Likewise.
 618
 619 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 620
 621         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 622
 623 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 624
 625         PR binutils/23212
 626         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 627         * aarch64-opc.c (verify_elem_sd): New.
 628         (fields): Add FLD_sz entr.
 629         * aarch64-tbl.h (_SIMD_INSN): New.
 630         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 631         fmulx scalar and vector by element isns.
 632
 633 2019-02-07  Nick Clifton  <nickc@redhat.com>
 634
 635         * po/sv.po: Updated Swedish translation.
 636
 637 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 638
 639         * s390-mkopc.c (main): Accept arch13 as cpu string.
 640         * s390-opc.c: Add new instruction formats and instruction opcode
 641         masks.
 642         * s390-opc.txt: Add new arch13 instructions.
 643
 644 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 645
 646         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 647         (aarch64_opcode): Change encoding for stg, stzg
 648         st2g and st2zg.
 649         * aarch64-asm-2.c: Regenerated.
 650         * aarch64-dis-2.c: Regenerated.
 651         * aarch64-opc-2.c: Regenerated.
 652
 653 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 654
 655         * aarch64-asm-2.c: Regenerated.
 656         * aarch64-dis-2.c: Likewise.
 657         * aarch64-opc-2.c: Likewise.
 658         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 659
 660 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 661             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 662
 663         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 664         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 665         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 666         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 667         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 668         case for ldstgv_indexed.
 669         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 670         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 671         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 672         * aarch64-asm-2.c: Regenerated.
 673         * aarch64-dis-2.c: Regenerated.
 674         * aarch64-opc-2.c: Regenerated.
 675
 676 2019-01-23  Nick Clifton  <nickc@redhat.com>
 677
 678         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 679
 680 2019-01-21  Nick Clifton  <nickc@redhat.com>
 681
 682         * po/de.po: Updated German translation.
 683         * po/uk.po: Updated Ukranian translation.
 684
 685 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 686         * mips-dis.c (mips_arch_choices): Fix typo in
 687         gs464, gs464e and gs264e descriptors.
 688
 689 2019-01-19  Nick Clifton  <nickc@redhat.com>
 690
 691         * configure: Regenerate.
 692         * po/opcodes.pot: Regenerate.
 693
 694 2018-06-24  Nick Clifton  <nickc@redhat.com>
 695
 696         2.32 branch created.
 697
 698 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 699
 700         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 701         if it is null.
 702         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 703         zero.
 704
 705 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 706
 707         * configure: Regenerate.
 708
 709 2019-01-07  Alan Modra  <amodra@gmail.com>
 710
 711         * configure: Regenerate.
 712         * po/POTFILES.in: Regenerate.
 713
 714 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 715
 716         * s12z-opc.c: New file.
 717         * s12z-opc.h: New file.
 718         * s12z-dis.c: Removed all code not directly related to display
 719         of instructions.  Used the interface provided by the new files
 720         instead.
 721         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 722         * Makefile.in: Regenerate.
 723         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 724         * configure: Regenerate.
 725
 726 2019-01-01  Alan Modra  <amodra@gmail.com>
 727
 728         Update year range in copyright notice of all files.
 729
 730 For older changes see ChangeLog-2018
 731 \f
 732 Copyright (C) 2019 Free Software Foundation, Inc.
 733
 734 Copying and distribution of this file, with or without modification,
 735 are permitted in any medium without royalty provided the copyright
 736 notice and this notice are preserved.
 737
 738 Local Variables:
 739 mode: change-log
 740 left-margin: 8
 741 fill-column: 74
 742 version-control: never
 743 End: