1 2019-12-11 Alan Modra <amodra@gmail.com>
3 * h8300-dis.c (extract_immediate): Avoid signed overflow.
4 (bfd_h8_disassemble): Likewise.
6 2019-12-11 Alan Modra <amodra@gmail.com>
8 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
9 past end of operands array.
11 2019-12-11 Alan Modra <amodra@gmail.com>
13 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
14 overflow when collecting bytes of a number.
16 2019-12-11 Alan Modra <amodra@gmail.com>
18 * cris-dis.c (print_with_operands): Avoid signed integer
19 overflow when collecting bytes of a 32-bit integer.
21 2019-12-11 Alan Modra <amodra@gmail.com>
23 * cr16-dis.c (EXTRACT, SBM): Rewrite.
24 (cr16_match_opcode): Delete duplicate bcond test.
26 2019-12-11 Alan Modra <amodra@gmail.com>
28 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
30 (MASKBITS, SIGNEXTEND): Rewrite.
31 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
32 unsigned arithmetic, instead assign result of SIGNEXTEND back
34 (fmtconst_val): Use 1u in shift expression.
36 2019-12-11 Alan Modra <amodra@gmail.com>
38 * arc-dis.c (find_format_from_table): Use ull constant when
41 2019-12-11 Alan Modra <amodra@gmail.com>
44 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
45 false when field is zero for sve_size_tsz_bhs.
47 2019-12-11 Alan Modra <amodra@gmail.com>
49 * epiphany-ibld.c: Regenerate.
51 2019-12-10 Alan Modra <amodra@gmail.com>
54 * disassemble.c (disassemble_free_target): New function.
56 2019-12-10 Alan Modra <amodra@gmail.com>
58 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
59 * disassemble.c (disassemble_init_for_target): Likewise.
60 * bpf-dis.c: Regenerate.
61 * epiphany-dis.c: Regenerate.
62 * fr30-dis.c: Regenerate.
63 * frv-dis.c: Regenerate.
64 * ip2k-dis.c: Regenerate.
65 * iq2000-dis.c: Regenerate.
66 * lm32-dis.c: Regenerate.
67 * m32c-dis.c: Regenerate.
68 * m32r-dis.c: Regenerate.
69 * mep-dis.c: Regenerate.
70 * mt-dis.c: Regenerate.
71 * or1k-dis.c: Regenerate.
72 * xc16x-dis.c: Regenerate.
73 * xstormy16-dis.c: Regenerate.
75 2019-12-10 Alan Modra <amodra@gmail.com>
77 * ppc-dis.c (private): Delete variable.
78 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
79 (powerpc_init_dialect): Don't use global private.
81 2019-12-10 Alan Modra <amodra@gmail.com>
83 * s12z-opc.c: Formatting.
85 2019-12-08 Alan Modra <amodra@gmail.com>
87 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
90 2019-12-05 Jan Beulich <jbeulich@suse.com>
92 * aarch64-tbl.h (aarch64_feature_crypto,
93 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
94 CRYPTO_V8_2_INSN): Delete.
96 2019-12-05 Alan Modra <amodra@gmail.com>
99 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
100 (struct string_buf): New.
101 (strbuf): New function.
102 (get_field): Use strbuf rather than strdup of local temp.
103 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
104 (get_field_rfsl, get_field_imm15): Likewise.
105 (get_field_rd, get_field_r1, get_field_r2): Update macros.
106 (get_field_special): Likewise. Don't strcpy spr. Formatting.
107 (print_insn_microblaze): Formatting. Init and pass string_buf to
110 2019-12-04 Jan Beulich <jbeulich@suse.com>
112 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
113 * i386-tbl.h: Re-generate.
115 2019-12-04 Jan Beulich <jbeulich@suse.com>
117 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
119 2019-12-04 Jan Beulich <jbeulich@suse.com>
121 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
123 (xbegin): Drop DefaultSize.
124 * i386-tbl.h: Re-generate.
126 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
128 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
129 Change the coproc CRC conditions to use the extension
130 feature set, second word, base on ARM_EXT2_CRC.
132 2019-11-14 Jan Beulich <jbeulich@suse.com>
134 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
135 * i386-tbl.h: Re-generate.
137 2019-11-14 Jan Beulich <jbeulich@suse.com>
139 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
140 JumpInterSegment, and JumpAbsolute entries.
141 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
142 JUMP_ABSOLUTE): Define.
143 (struct i386_opcode_modifier): Extend jump field to 3 bits.
144 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
146 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
147 JumpInterSegment): Define.
148 * i386-tbl.h: Re-generate.
150 2019-11-14 Jan Beulich <jbeulich@suse.com>
152 * i386-gen.c (operand_type_init): Remove
153 OPERAND_TYPE_JUMPABSOLUTE entry.
154 (opcode_modifiers): Add JumpAbsolute entry.
155 (operand_types): Remove JumpAbsolute entry.
156 * i386-opc.h (JumpAbsolute): Move between enums.
157 (struct i386_opcode_modifier): Add jumpabsolute field.
158 (union i386_operand_type): Remove jumpabsolute field.
159 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
160 * i386-init.h, i386-tbl.h: Re-generate.
162 2019-11-14 Jan Beulich <jbeulich@suse.com>
164 * i386-gen.c (opcode_modifiers): Add AnySize entry.
165 (operand_types): Remove AnySize entry.
166 * i386-opc.h (AnySize): Move between enums.
167 (struct i386_opcode_modifier): Add anysize field.
168 (OTUnused): Un-comment.
169 (union i386_operand_type): Remove anysize field.
170 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
171 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
172 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
174 * i386-tbl.h: Re-generate.
176 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
178 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
179 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
180 use the floating point register (FPR).
182 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
184 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
186 (is_mve_encoding_conflict): Update cmode conflict checks for
189 2019-11-12 Jan Beulich <jbeulich@suse.com>
191 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
193 (operand_types): Remove EsSeg entry.
194 (main): Replace stale use of OTMax.
195 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
196 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
198 (OTUnused): Comment out.
199 (union i386_operand_type): Remove esseg field.
200 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
201 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
202 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
203 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
204 * i386-init.h, i386-tbl.h: Re-generate.
206 2019-11-12 Jan Beulich <jbeulich@suse.com>
208 * i386-gen.c (operand_instances): Add RegB entry.
209 * i386-opc.h (enum operand_instance): Add RegB.
210 * i386-opc.tbl (RegC, RegD, RegB): Define.
211 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
212 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
213 monitorx, mwaitx): Drop ImmExt and convert encodings
215 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
216 (edx, rdx): Add Instance=RegD.
217 (ebx, rbx): Add Instance=RegB.
218 * i386-tbl.h: Re-generate.
220 2019-11-12 Jan Beulich <jbeulich@suse.com>
222 * i386-gen.c (operand_type_init): Adjust
223 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
224 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
225 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
226 (operand_instances): New.
227 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
228 (output_operand_type): New parameter "instance". Process it.
229 (process_i386_operand_type): New local variable "instance".
230 (main): Adjust static assertions.
231 * i386-opc.h (INSTANCE_WIDTH): Define.
232 (enum operand_instance): New.
233 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
234 (union i386_operand_type): Replace acc, inoutportreg, and
235 shiftcount by instance.
236 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
237 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
239 * i386-init.h, i386-tbl.h: Re-generate.
241 2019-11-11 Jan Beulich <jbeulich@suse.com>
243 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
244 smaxp/sminp entries' "tied_operand" field to 2.
246 2019-11-11 Jan Beulich <jbeulich@suse.com>
248 * aarch64-opc.c (operand_general_constraint_met_p): Replace
249 "index" local variable by that of the already existing "num".
251 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
254 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
255 * i386-tbl.h: Regenerated.
257 2019-11-08 Jan Beulich <jbeulich@suse.com>
259 * i386-gen.c (operand_type_init): Add Class= to
260 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
261 OPERAND_TYPE_REGBND entry.
262 (operand_classes): Add RegMask and RegBND entries.
263 (operand_types): Drop RegMask and RegBND entry.
264 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
265 (RegMask, RegBND): Delete.
266 (union i386_operand_type): Remove regmask and regbnd fields.
267 * i386-opc.tbl (RegMask, RegBND): Define.
268 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
270 * i386-init.h, i386-tbl.h: Re-generate.
272 2019-11-08 Jan Beulich <jbeulich@suse.com>
274 * i386-gen.c (operand_type_init): Add Class= to
275 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
276 OPERAND_TYPE_REGZMM entries.
277 (operand_classes): Add RegMMX and RegSIMD entries.
278 (operand_types): Drop RegMMX and RegSIMD entries.
279 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
280 (RegMMX, RegSIMD): Delete.
281 (union i386_operand_type): Remove regmmx and regsimd fields.
282 * i386-opc.tbl (RegMMX): Define.
283 (RegXMM, RegYMM, RegZMM): Add Class=.
284 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
286 * i386-init.h, i386-tbl.h: Re-generate.
288 2019-11-08 Jan Beulich <jbeulich@suse.com>
290 * i386-gen.c (operand_type_init): Add Class= to
291 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
293 (operand_classes): Add RegCR, RegDR, and RegTR entries.
294 (operand_types): Drop Control, Debug, and Test entries.
295 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
296 (Control, Debug, Test): Delete.
297 (union i386_operand_type): Remove control, debug, and test
299 * i386-opc.tbl (Control, Debug, Test): Define.
300 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
301 Class=RegDR, and Test by Class=RegTR.
302 * i386-init.h, i386-tbl.h: Re-generate.
304 2019-11-08 Jan Beulich <jbeulich@suse.com>
306 * i386-gen.c (operand_type_init): Add Class= to
307 OPERAND_TYPE_SREG entry.
308 (operand_classes): Add SReg entry.
309 (operand_types): Drop SReg entry.
310 * i386-opc.h (enum operand_class): Add SReg.
312 (union i386_operand_type): Remove sreg field.
313 * i386-opc.tbl (SReg): Define.
314 * i386-reg.tbl: Replace SReg by Class=SReg.
315 * i386-init.h, i386-tbl.h: Re-generate.
317 2019-11-08 Jan Beulich <jbeulich@suse.com>
319 * i386-gen.c (operand_type_init): Add Class=. New
320 OPERAND_TYPE_ANYIMM entry.
321 (operand_classes): New.
322 (operand_types): Drop Reg entry.
323 (output_operand_type): New parameter "class". Process it.
324 (process_i386_operand_type): New local variable "class".
325 (main): Adjust static assertions.
326 * i386-opc.h (CLASS_WIDTH): Define.
327 (enum operand_class): New.
328 (Reg): Replace by Class. Adjust comment.
329 (union i386_operand_type): Replace reg by class.
330 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
332 * i386-reg.tbl: Replace Reg by Class=Reg.
333 * i386-init.h: Re-generate.
335 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
337 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
338 (aarch64_opcode_table): Add data gathering hint mnemonic.
339 * opcodes/aarch64-dis-2.c: Account for new instruction.
341 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
343 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
346 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
348 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
349 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
350 aarch64_feature_f64mm): New feature sets.
351 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
352 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
354 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
356 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
357 (OP_SVE_QQQ): New qualifier.
358 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
359 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
360 the movprfx constraint.
361 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
362 (aarch64_opcode_table): Define new instructions smmla,
363 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
365 * aarch64-opc.c (operand_general_constraint_met_p): Handle
366 AARCH64_OPND_SVE_ADDR_RI_S4x32.
367 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
368 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
369 Account for new instructions.
370 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
372 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
374 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
375 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
377 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
379 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
380 (neon_opcodes): Add bfloat SIMD instructions.
381 (print_insn_coprocessor): Add new control character %b to print
382 condition code without checking cp_num.
383 (print_insn_neon): Account for BFloat16 instructions that have no
384 special top-byte handling.
386 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
387 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
389 * arm-dis.c (print_insn_coprocessor,
390 print_insn_generic_coprocessor): Create wrapper functions around
391 the implementation of the print_insn_coprocessor control codes.
392 (print_insn_coprocessor_1): Original print_insn_coprocessor
393 function that now takes which array to look at as an argument.
394 (print_insn_arm): Use both print_insn_coprocessor and
395 print_insn_generic_coprocessor.
396 (print_insn_thumb32): As above.
398 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
399 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
401 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
402 in reglane special case.
403 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
404 aarch64_find_next_opcode): Account for new instructions.
405 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
406 in reglane special case.
407 * aarch64-opc.c (struct operand_qualifier_data): Add data for
408 new AARCH64_OPND_QLF_S_2H qualifier.
409 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
410 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
411 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
413 (BFLOAT_SVE, BFLOAT): New feature set macros.
414 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
416 (aarch64_opcode_table): Define new instructions bfdot,
417 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
420 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
421 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
423 * aarch64-tbl.h (ARMV8_6): New macro.
425 2019-11-07 Jan Beulich <jbeulich@suse.com>
427 * i386-dis.c (prefix_table): Add mcommit.
428 (rm_table): Add rdpru.
429 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
430 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
431 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
432 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
433 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
434 * i386-opc.tbl (mcommit, rdpru): New.
435 * i386-init.h, i386-tbl.h: Re-generate.
437 2019-11-07 Jan Beulich <jbeulich@suse.com>
439 * i386-dis.c (OP_Mwait): Drop local variable "names", use
441 (OP_Monitor): Drop local variable "op1_names", re-purpose
442 "names" for it instead, and replace former "names" uses by
445 2019-11-07 Jan Beulich <jbeulich@suse.com>
448 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
450 * opcodes/i386-tbl.h: Re-generate.
452 2019-11-05 Jan Beulich <jbeulich@suse.com>
454 * i386-dis.c (OP_Mwaitx): Delete.
455 (prefix_table): Use OP_Mwait for mwaitx entry.
456 (OP_Mwait): Also handle mwaitx.
458 2019-11-05 Jan Beulich <jbeulich@suse.com>
460 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
461 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
462 (prefix_table): Add respective entries.
463 (rm_table): Link to those entries.
465 2019-11-05 Jan Beulich <jbeulich@suse.com>
467 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
468 (REG_0F1C_P_0_MOD_0): ... this.
469 (REG_0F1E_MOD_3): Rename to ...
470 (REG_0F1E_P_1_MOD_3): ... this.
471 (RM_0F01_REG_5): Rename to ...
472 (RM_0F01_REG_5_MOD_3): ... this.
473 (RM_0F01_REG_7): Rename to ...
474 (RM_0F01_REG_7_MOD_3): ... this.
475 (RM_0F1E_MOD_3_REG_7): Rename to ...
476 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
477 (RM_0FAE_REG_6): Rename to ...
478 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
479 (RM_0FAE_REG_7): Rename to ...
480 (RM_0FAE_REG_7_MOD_3): ... this.
481 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
482 (PREFIX_0F01_REG_5_MOD_0): ... this.
483 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
484 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
485 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
486 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
487 (PREFIX_0FAE_REG_0): Rename to ...
488 (PREFIX_0FAE_REG_0_MOD_3): ... this.
489 (PREFIX_0FAE_REG_1): Rename to ...
490 (PREFIX_0FAE_REG_1_MOD_3): ... this.
491 (PREFIX_0FAE_REG_2): Rename to ...
492 (PREFIX_0FAE_REG_2_MOD_3): ... this.
493 (PREFIX_0FAE_REG_3): Rename to ...
494 (PREFIX_0FAE_REG_3_MOD_3): ... this.
495 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
496 (PREFIX_0FAE_REG_4_MOD_0): ... this.
497 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
498 (PREFIX_0FAE_REG_4_MOD_3): ... this.
499 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
500 (PREFIX_0FAE_REG_5_MOD_0): ... this.
501 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
502 (PREFIX_0FAE_REG_5_MOD_3): ... this.
503 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
504 (PREFIX_0FAE_REG_6_MOD_0): ... this.
505 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
506 (PREFIX_0FAE_REG_6_MOD_3): ... this.
507 (PREFIX_0FAE_REG_7): Rename to ...
508 (PREFIX_0FAE_REG_7_MOD_0): ... this.
509 (PREFIX_MOD_0_0FC3): Rename to ...
510 (PREFIX_0FC3_MOD_0): ... this.
511 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
512 (PREFIX_0FC7_REG_6_MOD_0): ... this.
513 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
514 (PREFIX_0FC7_REG_6_MOD_3): ... this.
515 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
516 (PREFIX_0FC7_REG_7_MOD_3): ... this.
517 (reg_table, prefix_table, mod_table, rm_table): Adjust
520 2019-11-04 Nick Clifton <nickc@redhat.com>
522 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
523 of a v850 system register. Move the v850_sreg_names array into
525 (get_v850_reg_name): Likewise for ordinary register names.
526 (get_v850_vreg_name): Likewise for vector register names.
527 (get_v850_cc_name): Likewise for condition codes.
528 * get_v850_float_cc_name): Likewise for floating point condition
530 (get_v850_cacheop_name): Likewise for cache-ops.
531 (get_v850_prefop_name): Likewise for pref-ops.
532 (disassemble): Use the new accessor functions.
534 2019-10-30 Delia Burduv <delia.burduv@arm.com>
536 * aarch64-opc.c (print_immediate_offset_address): Don't print the
537 immediate for the writeback form of ldraa/ldrab if it is 0.
538 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
539 * aarch64-opc-2.c: Regenerated.
541 2019-10-30 Jan Beulich <jbeulich@suse.com>
543 * i386-gen.c (operand_type_shorthands): Delete.
544 (operand_type_init): Expand previous shorthands.
545 (set_bitfield_from_shorthand): Rename back to ...
546 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
547 of operand_type_init[].
548 (set_bitfield): Adjust call to the above function.
549 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
550 RegXMM, RegYMM, RegZMM): Define.
551 * i386-reg.tbl: Expand prior shorthands.
553 2019-10-30 Jan Beulich <jbeulich@suse.com>
555 * i386-gen.c (output_i386_opcode): Change order of fields
557 * i386-opc.h (struct insn_template): Move operands field.
558 Convert extension_opcode field to unsigned short.
559 * i386-tbl.h: Re-generate.
561 2019-10-30 Jan Beulich <jbeulich@suse.com>
563 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
565 * i386-opc.h (W): Extend comment.
566 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
567 general purpose variants not allowing for byte operands.
568 * i386-tbl.h: Re-generate.
570 2019-10-29 Nick Clifton <nickc@redhat.com>
572 * tic30-dis.c (print_branch): Correct size of operand array.
574 2019-10-29 Nick Clifton <nickc@redhat.com>
576 * d30v-dis.c (print_insn): Check that operand index is valid
577 before attempting to access the operands array.
579 2019-10-29 Nick Clifton <nickc@redhat.com>
581 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
582 locating the bit to be tested.
584 2019-10-29 Nick Clifton <nickc@redhat.com>
586 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
588 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
589 (print_insn_s12z): Check for illegal size values.
591 2019-10-28 Nick Clifton <nickc@redhat.com>
593 * csky-dis.c (csky_chars_to_number): Check for a negative
594 count. Use an unsigned integer to construct the return value.
596 2019-10-28 Nick Clifton <nickc@redhat.com>
598 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
599 operand buffer. Set value to 15 not 13.
600 (get_register_operand): Use OPERAND_BUFFER_LEN.
601 (get_indirect_operand): Likewise.
602 (print_two_operand): Likewise.
603 (print_three_operand): Likewise.
604 (print_oar_insn): Likewise.
606 2019-10-28 Nick Clifton <nickc@redhat.com>
608 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
609 (bit_extract_simple): Likewise.
610 (bit_copy): Likewise.
611 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
612 index_offset array are not accessed.
614 2019-10-28 Nick Clifton <nickc@redhat.com>
616 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
619 2019-10-25 Nick Clifton <nickc@redhat.com>
621 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
622 access to opcodes.op array element.
624 2019-10-23 Nick Clifton <nickc@redhat.com>
626 * rx-dis.c (get_register_name): Fix spelling typo in error
628 (get_condition_name, get_flag_name, get_double_register_name)
629 (get_double_register_high_name, get_double_register_low_name)
630 (get_double_control_register_name, get_double_condition_name)
631 (get_opsize_name, get_size_name): Likewise.
633 2019-10-22 Nick Clifton <nickc@redhat.com>
635 * rx-dis.c (get_size_name): New function. Provides safe
636 access to name array.
637 (get_opsize_name): Likewise.
638 (print_insn_rx): Use the accessor functions.
640 2019-10-16 Nick Clifton <nickc@redhat.com>
642 * rx-dis.c (get_register_name): New function. Provides safe
643 access to name array.
644 (get_condition_name, get_flag_name, get_double_register_name)
645 (get_double_register_high_name, get_double_register_low_name)
646 (get_double_control_register_name, get_double_condition_name):
648 (print_insn_rx): Use the accessor functions.
650 2019-10-09 Nick Clifton <nickc@redhat.com>
653 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
656 2019-10-07 Jan Beulich <jbeulich@suse.com>
658 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
659 (cmpsd): Likewise. Move EsSeg to other operand.
660 * opcodes/i386-tbl.h: Re-generate.
662 2019-09-23 Alan Modra <amodra@gmail.com>
664 * m68k-dis.c: Include cpu-m68k.h
666 2019-09-23 Alan Modra <amodra@gmail.com>
668 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
669 "elf/mips.h" earlier.
671 2018-09-20 Jan Beulich <jbeulich@suse.com>
674 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
676 * i386-tbl.h: Re-generate.
678 2019-09-18 Alan Modra <amodra@gmail.com>
680 * arc-ext.c: Update throughout for bfd section macro changes.
682 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
684 * Makefile.in: Re-generate.
685 * configure: Re-generate.
687 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
689 * riscv-opc.c (riscv_opcodes): Change subset field
690 to insn_class field for all instructions.
691 (riscv_insn_types): Likewise.
693 2019-09-16 Phil Blundell <pb@pbcl.net>
695 * configure: Regenerated.
697 2019-09-10 Miod Vallat <miod@online.fr>
700 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
702 2019-09-09 Phil Blundell <pb@pbcl.net>
704 binutils 2.33 branch created.
706 2019-09-03 Nick Clifton <nickc@redhat.com>
709 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
710 greater than zero before indexing via (bufcnt -1).
712 2019-09-03 Nick Clifton <nickc@redhat.com>
715 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
716 (MAX_SPEC_REG_NAME_LEN): Define.
717 (struct mmix_dis_info): Use defined constants for array lengths.
718 (get_reg_name): New function.
719 (get_sprec_reg_name): New function.
720 (print_insn_mmix): Use new functions.
722 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
724 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
725 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
726 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
728 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
730 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
731 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
732 (aarch64_sys_reg_supported_p): Update checks for the above.
734 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
736 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
737 cases MVE_SQRSHRL and MVE_UQRSHLL.
738 (print_insn_mve): Add case for specifier 'k' to check
739 specific bit of the instruction.
741 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
744 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
745 encountering an unknown machine type.
746 (print_insn_arc): Handle arc_insn_length returning 0. In error
747 cases return -1 rather than calling abort.
749 2019-08-07 Jan Beulich <jbeulich@suse.com>
751 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
752 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
754 * i386-tbl.h: Re-generate.
756 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
758 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
761 2019-07-30 Mel Chen <mel.chen@sifive.com>
763 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
764 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
766 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
769 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
771 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
772 and MPY class instructions.
773 (parse_option): Add nps400 option.
774 (print_arc_disassembler_options): Add nps400 info.
776 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
778 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
781 * arc-opc.c (RAD_CHK): Add.
782 * arc-tbl.h: Regenerate.
784 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
786 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
787 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
789 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
791 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
792 instructions as UNPREDICTABLE.
794 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
796 * bpf-desc.c: Regenerated.
798 2019-07-17 Jan Beulich <jbeulich@suse.com>
800 * i386-gen.c (static_assert): Define.
802 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
803 (Opcode_Modifier_Num): ... this.
806 2019-07-16 Jan Beulich <jbeulich@suse.com>
808 * i386-gen.c (operand_types): Move RegMem ...
809 (opcode_modifiers): ... here.
810 * i386-opc.h (RegMem): Move to opcode modifer enum.
811 (union i386_operand_type): Move regmem field ...
812 (struct i386_opcode_modifier): ... here.
813 * i386-opc.tbl (RegMem): Define.
814 (mov, movq): Move RegMem on segment, control, debug, and test
816 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
817 to non-SSE2AVX flavor.
818 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
819 Move RegMem on register only flavors. Drop IgnoreSize from
820 legacy encoding flavors.
821 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
823 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
824 register only flavors.
825 (vmovd): Move RegMem and drop IgnoreSize on register only
826 flavor. Change opcode and operand order to store form.
827 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
829 2019-07-16 Jan Beulich <jbeulich@suse.com>
831 * i386-gen.c (operand_type_init, operand_types): Replace SReg
833 * i386-opc.h (SReg2, SReg3): Replace by ...
835 (union i386_operand_type): Replace sreg fields.
836 * i386-opc.tbl (mov, ): Use SReg.
837 (push, pop): Likewies. Drop i386 and x86-64 specific segment
839 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
840 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
842 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
844 * bpf-desc.c: Regenerate.
845 * bpf-opc.c: Likewise.
846 * bpf-opc.h: Likewise.
848 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
850 * bpf-desc.c: Regenerate.
851 * bpf-opc.c: Likewise.
853 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
855 * arm-dis.c (print_insn_coprocessor): Rename index to
858 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
860 * riscv-opc.c (riscv_insn_types): Add r4 type.
862 * riscv-opc.c (riscv_insn_types): Add b and j type.
864 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
865 format for sb type and correct s type.
867 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
869 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
870 SVE FMOV alias of FCPY.
872 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
874 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
875 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
877 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
879 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
880 registers in an instruction prefixed by MOVPRFX.
882 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
884 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
885 sve_size_13 icode to account for variant behaviour of
887 * aarch64-dis-2.c: Regenerate.
888 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
889 sve_size_13 icode to account for variant behaviour of
891 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
892 (OP_SVE_VVV_Q_D): Add new qualifier.
893 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
894 (struct aarch64_opcode): Split pmull{t,b} into those requiring
897 2019-07-01 Jan Beulich <jbeulich@suse.com>
899 * opcodes/i386-gen.c (operand_type_init): Remove
900 OPERAND_TYPE_VEC_IMM4 entry.
901 (operand_types): Remove Vec_Imm4.
902 * opcodes/i386-opc.h (Vec_Imm4): Delete.
903 (union i386_operand_type): Remove vec_imm4.
904 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
905 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
907 2019-07-01 Jan Beulich <jbeulich@suse.com>
909 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
910 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
911 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
912 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
913 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
914 monitorx, mwaitx): Drop ImmExt from operand-less forms.
915 * i386-tbl.h: Re-generate.
917 2019-07-01 Jan Beulich <jbeulich@suse.com>
919 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
921 * i386-tbl.h: Re-generate.
923 2019-07-01 Jan Beulich <jbeulich@suse.com>
925 * i386-opc.tbl (C): New.
926 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
927 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
928 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
929 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
930 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
931 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
932 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
933 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
934 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
935 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
936 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
937 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
938 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
939 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
940 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
941 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
942 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
943 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
944 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
945 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
946 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
947 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
948 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
949 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
950 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
951 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
953 * i386-tbl.h: Re-generate.
955 2019-07-01 Jan Beulich <jbeulich@suse.com>
957 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
959 * i386-tbl.h: Re-generate.
961 2019-07-01 Jan Beulich <jbeulich@suse.com>
963 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
964 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
965 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
966 * i386-tbl.h: Re-generate.
968 2019-07-01 Jan Beulich <jbeulich@suse.com>
970 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
971 Disp8MemShift from register only templates.
972 * i386-tbl.h: Re-generate.
974 2019-07-01 Jan Beulich <jbeulich@suse.com>
976 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
977 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
978 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
979 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
980 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
981 EVEX_W_0F11_P_3_M_1): Delete.
982 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
983 EVEX_W_0F11_P_3): New.
984 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
985 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
986 MOD_EVEX_0F11_PREFIX_3 table entries.
987 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
988 PREFIX_EVEX_0F11 table entries.
989 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
990 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
991 EVEX_W_0F11_P_3_M_{0,1} table entries.
993 2019-07-01 Jan Beulich <jbeulich@suse.com>
995 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
998 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1001 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1002 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1003 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1004 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1005 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1006 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1007 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1008 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1009 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1010 PREFIX_EVEX_0F38C6_REG_6 entries.
1011 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1012 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1013 EVEX_W_0F38C7_R_6_P_2 entries.
1014 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1015 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1016 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1017 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1018 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1019 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1020 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1022 2019-06-27 Jan Beulich <jbeulich@suse.com>
1024 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1025 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1026 VEX_LEN_0F2D_P_3): Delete.
1027 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1028 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1029 (prefix_table): ... here.
1031 2019-06-27 Jan Beulich <jbeulich@suse.com>
1033 * i386-dis.c (Iq): Delete.
1035 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1037 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1038 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1039 (OP_E_memory): Also honor needindex when deciding whether an
1040 address size prefix needs printing.
1041 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1043 2019-06-26 Jim Wilson <jimw@sifive.com>
1046 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1047 Set info->display_endian to info->endian_code.
1049 2019-06-25 Jan Beulich <jbeulich@suse.com>
1051 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1052 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1053 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1054 OPERAND_TYPE_ACC64 entries.
1055 * i386-init.h: Re-generate.
1057 2019-06-25 Jan Beulich <jbeulich@suse.com>
1059 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1061 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1063 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1065 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1066 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1068 2019-06-25 Jan Beulich <jbeulich@suse.com>
1070 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1073 2019-06-25 Jan Beulich <jbeulich@suse.com>
1075 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1076 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1078 * i386-opc.tbl (movnti): Add IgnoreSize.
1079 * i386-tbl.h: Re-generate.
1081 2019-06-25 Jan Beulich <jbeulich@suse.com>
1083 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1084 * i386-tbl.h: Re-generate.
1086 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1088 * i386-dis-evex.h: Break into ...
1089 * i386-dis-evex-len.h: New file.
1090 * i386-dis-evex-mod.h: Likewise.
1091 * i386-dis-evex-prefix.h: Likewise.
1092 * i386-dis-evex-reg.h: Likewise.
1093 * i386-dis-evex-w.h: Likewise.
1094 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1095 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1096 i386-dis-evex-mod.h.
1098 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1101 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1102 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1104 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1105 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1106 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1107 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1108 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1109 EVEX_LEN_0F385B_P_2_W_1.
1110 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1111 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1112 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1113 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1114 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1115 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1116 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1117 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1118 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1119 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1121 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1124 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1125 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1126 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1127 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1128 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1129 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1130 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1131 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1132 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1133 EVEX_LEN_0F3A43_P_2_W_1.
1134 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1135 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1136 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1137 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1138 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1139 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1140 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1141 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1142 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1143 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1144 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1145 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1147 2019-06-14 Nick Clifton <nickc@redhat.com>
1149 * po/fr.po; Updated French translation.
1151 2019-06-13 Stafford Horne <shorne@gmail.com>
1153 * or1k-asm.c: Regenerated.
1154 * or1k-desc.c: Regenerated.
1155 * or1k-desc.h: Regenerated.
1156 * or1k-dis.c: Regenerated.
1157 * or1k-ibld.c: Regenerated.
1158 * or1k-opc.c: Regenerated.
1159 * or1k-opc.h: Regenerated.
1160 * or1k-opinst.c: Regenerated.
1162 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1164 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1166 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1169 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1170 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1171 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1172 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1173 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1174 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1175 EVEX_LEN_0F3A1B_P_2_W_1.
1176 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1177 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1178 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1179 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1180 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1181 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1182 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1183 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1185 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1188 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1189 EVEX.vvvv when disassembling VEX and EVEX instructions.
1190 (OP_VEX): Set vex.register_specifier to 0 after readding
1191 vex.register_specifier.
1192 (OP_Vex_2src_1): Likewise.
1193 (OP_Vex_2src_2): Likewise.
1194 (OP_LWP_E): Likewise.
1195 (OP_EX_Vex): Don't check vex.register_specifier.
1196 (OP_XMM_Vex): Likewise.
1198 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1199 Lili Cui <lili.cui@intel.com>
1201 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1202 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1204 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1205 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1206 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1207 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1208 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1209 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1210 * i386-init.h: Regenerated.
1211 * i386-tbl.h: Likewise.
1213 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1214 Lili Cui <lili.cui@intel.com>
1216 * doc/c-i386.texi: Document enqcmd.
1217 * testsuite/gas/i386/enqcmd-intel.d: New file.
1218 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1219 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1220 * testsuite/gas/i386/enqcmd.d: Likewise.
1221 * testsuite/gas/i386/enqcmd.s: Likewise.
1222 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1223 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1224 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1225 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1226 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1227 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1228 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1231 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1233 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1235 2019-06-03 Alan Modra <amodra@gmail.com>
1237 * ppc-dis.c (prefix_opcd_indices): Correct size.
1239 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1242 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1244 * i386-tbl.h: Regenerated.
1246 2019-05-24 Alan Modra <amodra@gmail.com>
1248 * po/POTFILES.in: Regenerate.
1250 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1251 Alan Modra <amodra@gmail.com>
1253 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1254 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1255 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1256 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1257 XTOP>): Define and add entries.
1258 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1259 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1260 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1261 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1263 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1264 Alan Modra <amodra@gmail.com>
1266 * ppc-dis.c (ppc_opts): Add "future" entry.
1267 (PREFIX_OPCD_SEGS): Define.
1268 (prefix_opcd_indices): New array.
1269 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1270 (lookup_prefix): New function.
1271 (print_insn_powerpc): Handle 64-bit prefix instructions.
1272 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1273 (PMRR, POWERXX): Define.
1274 (prefix_opcodes): New instruction table.
1275 (prefix_num_opcodes): New constant.
1277 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1279 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1280 * configure: Regenerated.
1281 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1283 (HFILES): Add bpf-desc.h and bpf-opc.h.
1284 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1285 bpf-ibld.c and bpf-opc.c.
1287 * Makefile.in: Regenerated.
1288 * disassemble.c (ARCH_bpf): Define.
1289 (disassembler): Add case for bfd_arch_bpf.
1290 (disassemble_init_for_target): Likewise.
1291 (enum epbf_isa_attr): Define.
1292 * disassemble.h: extern print_insn_bpf.
1293 * bpf-asm.c: Generated.
1294 * bpf-opc.h: Likewise.
1295 * bpf-opc.c: Likewise.
1296 * bpf-ibld.c: Likewise.
1297 * bpf-dis.c: Likewise.
1298 * bpf-desc.h: Likewise.
1299 * bpf-desc.c: Likewise.
1301 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1303 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1304 and VMSR with the new operands.
1306 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1308 * arm-dis.c (enum mve_instructions): New enum
1309 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1311 (mve_opcodes): New instructions as above.
1312 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1314 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1316 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1318 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1319 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1320 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1321 uqshl, urshrl and urshr.
1322 (is_mve_okay_in_it): Add new instructions to TRUE list.
1323 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1324 (print_insn_mve): Updated to accept new %j,
1325 %<bitfield>m and %<bitfield>n patterns.
1327 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1329 * mips-opc.c (mips_builtin_opcodes): Change source register
1330 constraint for DAUI.
1332 2019-05-20 Nick Clifton <nickc@redhat.com>
1334 * po/fr.po: Updated French translation.
1336 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1337 Michael Collison <michael.collison@arm.com>
1339 * arm-dis.c (thumb32_opcodes): Add new instructions.
1340 (enum mve_instructions): Likewise.
1341 (enum mve_undefined): Add new reasons.
1342 (is_mve_encoding_conflict): Handle new instructions.
1343 (is_mve_undefined): Likewise.
1344 (is_mve_unpredictable): Likewise.
1345 (print_mve_undefined): Likewise.
1346 (print_mve_size): Likewise.
1348 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1349 Michael Collison <michael.collison@arm.com>
1351 * arm-dis.c (thumb32_opcodes): Add new instructions.
1352 (enum mve_instructions): Likewise.
1353 (is_mve_encoding_conflict): Handle new instructions.
1354 (is_mve_undefined): Likewise.
1355 (is_mve_unpredictable): Likewise.
1356 (print_mve_size): Likewise.
1358 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1359 Michael Collison <michael.collison@arm.com>
1361 * arm-dis.c (thumb32_opcodes): Add new instructions.
1362 (enum mve_instructions): Likewise.
1363 (is_mve_encoding_conflict): Likewise.
1364 (is_mve_unpredictable): Likewise.
1365 (print_mve_size): Likewise.
1367 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1368 Michael Collison <michael.collison@arm.com>
1370 * arm-dis.c (thumb32_opcodes): Add new instructions.
1371 (enum mve_instructions): Likewise.
1372 (is_mve_encoding_conflict): Handle new instructions.
1373 (is_mve_undefined): Likewise.
1374 (is_mve_unpredictable): Likewise.
1375 (print_mve_size): Likewise.
1377 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1378 Michael Collison <michael.collison@arm.com>
1380 * arm-dis.c (thumb32_opcodes): Add new instructions.
1381 (enum mve_instructions): Likewise.
1382 (is_mve_encoding_conflict): Handle new instructions.
1383 (is_mve_undefined): Likewise.
1384 (is_mve_unpredictable): Likewise.
1385 (print_mve_size): Likewise.
1386 (print_insn_mve): Likewise.
1388 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1389 Michael Collison <michael.collison@arm.com>
1391 * arm-dis.c (thumb32_opcodes): Add new instructions.
1392 (print_insn_thumb32): Handle new instructions.
1394 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1395 Michael Collison <michael.collison@arm.com>
1397 * arm-dis.c (enum mve_instructions): Add new instructions.
1398 (enum mve_undefined): Add new reasons.
1399 (is_mve_encoding_conflict): Handle new instructions.
1400 (is_mve_undefined): Likewise.
1401 (is_mve_unpredictable): Likewise.
1402 (print_mve_undefined): Likewise.
1403 (print_mve_size): Likewise.
1404 (print_mve_shift_n): Likewise.
1405 (print_insn_mve): Likewise.
1407 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1408 Michael Collison <michael.collison@arm.com>
1410 * arm-dis.c (enum mve_instructions): Add new instructions.
1411 (is_mve_encoding_conflict): Handle new instructions.
1412 (is_mve_unpredictable): Likewise.
1413 (print_mve_rotate): Likewise.
1414 (print_mve_size): Likewise.
1415 (print_insn_mve): Likewise.
1417 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1418 Michael Collison <michael.collison@arm.com>
1420 * arm-dis.c (enum mve_instructions): Add new instructions.
1421 (is_mve_encoding_conflict): Handle new instructions.
1422 (is_mve_unpredictable): Likewise.
1423 (print_mve_size): Likewise.
1424 (print_insn_mve): Likewise.
1426 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1427 Michael Collison <michael.collison@arm.com>
1429 * arm-dis.c (enum mve_instructions): Add new instructions.
1430 (enum mve_undefined): Add new reasons.
1431 (is_mve_encoding_conflict): Handle new instructions.
1432 (is_mve_undefined): Likewise.
1433 (is_mve_unpredictable): Likewise.
1434 (print_mve_undefined): Likewise.
1435 (print_mve_size): Likewise.
1436 (print_insn_mve): Likewise.
1438 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1439 Michael Collison <michael.collison@arm.com>
1441 * arm-dis.c (enum mve_instructions): Add new instructions.
1442 (is_mve_encoding_conflict): Handle new instructions.
1443 (is_mve_undefined): Likewise.
1444 (is_mve_unpredictable): Likewise.
1445 (print_mve_size): Likewise.
1446 (print_insn_mve): Likewise.
1448 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1449 Michael Collison <michael.collison@arm.com>
1451 * arm-dis.c (enum mve_instructions): Add new instructions.
1452 (enum mve_unpredictable): Add new reasons.
1453 (enum mve_undefined): Likewise.
1454 (is_mve_okay_in_it): Handle new isntructions.
1455 (is_mve_encoding_conflict): Likewise.
1456 (is_mve_undefined): Likewise.
1457 (is_mve_unpredictable): Likewise.
1458 (print_mve_vmov_index): Likewise.
1459 (print_simd_imm8): Likewise.
1460 (print_mve_undefined): Likewise.
1461 (print_mve_unpredictable): Likewise.
1462 (print_mve_size): Likewise.
1463 (print_insn_mve): Likewise.
1465 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1466 Michael Collison <michael.collison@arm.com>
1468 * arm-dis.c (enum mve_instructions): Add new instructions.
1469 (enum mve_unpredictable): Add new reasons.
1470 (enum mve_undefined): Likewise.
1471 (is_mve_encoding_conflict): Handle new instructions.
1472 (is_mve_undefined): Likewise.
1473 (is_mve_unpredictable): Likewise.
1474 (print_mve_undefined): Likewise.
1475 (print_mve_unpredictable): Likewise.
1476 (print_mve_rounding_mode): Likewise.
1477 (print_mve_vcvt_size): Likewise.
1478 (print_mve_size): Likewise.
1479 (print_insn_mve): Likewise.
1481 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1482 Michael Collison <michael.collison@arm.com>
1484 * arm-dis.c (enum mve_instructions): Add new instructions.
1485 (enum mve_unpredictable): Add new reasons.
1486 (enum mve_undefined): Likewise.
1487 (is_mve_undefined): Handle new instructions.
1488 (is_mve_unpredictable): Likewise.
1489 (print_mve_undefined): Likewise.
1490 (print_mve_unpredictable): Likewise.
1491 (print_mve_size): Likewise.
1492 (print_insn_mve): Likewise.
1494 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1495 Michael Collison <michael.collison@arm.com>
1497 * arm-dis.c (enum mve_instructions): Add new instructions.
1498 (enum mve_undefined): Add new reasons.
1499 (insns): Add new instructions.
1500 (is_mve_encoding_conflict):
1501 (print_mve_vld_str_addr): New print function.
1502 (is_mve_undefined): Handle new instructions.
1503 (is_mve_unpredictable): Likewise.
1504 (print_mve_undefined): Likewise.
1505 (print_mve_size): Likewise.
1506 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1507 (print_insn_mve): Handle new operands.
1509 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1510 Michael Collison <michael.collison@arm.com>
1512 * arm-dis.c (enum mve_instructions): Add new instructions.
1513 (enum mve_unpredictable): Add new reasons.
1514 (is_mve_encoding_conflict): Handle new instructions.
1515 (is_mve_unpredictable): Likewise.
1516 (mve_opcodes): Add new instructions.
1517 (print_mve_unpredictable): Handle new reasons.
1518 (print_mve_register_blocks): New print function.
1519 (print_mve_size): Handle new instructions.
1520 (print_insn_mve): Likewise.
1522 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1523 Michael Collison <michael.collison@arm.com>
1525 * arm-dis.c (enum mve_instructions): Add new instructions.
1526 (enum mve_unpredictable): Add new reasons.
1527 (enum mve_undefined): Likewise.
1528 (is_mve_encoding_conflict): Handle new instructions.
1529 (is_mve_undefined): Likewise.
1530 (is_mve_unpredictable): Likewise.
1531 (coprocessor_opcodes): Move NEON VDUP from here...
1532 (neon_opcodes): ... to here.
1533 (mve_opcodes): Add new instructions.
1534 (print_mve_undefined): Handle new reasons.
1535 (print_mve_unpredictable): Likewise.
1536 (print_mve_size): Handle new instructions.
1537 (print_insn_neon): Handle vdup.
1538 (print_insn_mve): Handle new operands.
1540 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1541 Michael Collison <michael.collison@arm.com>
1543 * arm-dis.c (enum mve_instructions): Add new instructions.
1544 (enum mve_unpredictable): Add new values.
1545 (mve_opcodes): Add new instructions.
1546 (vec_condnames): New array with vector conditions.
1547 (mve_predicatenames): New array with predicate suffixes.
1548 (mve_vec_sizename): New array with vector sizes.
1549 (enum vpt_pred_state): New enum with vector predication states.
1550 (struct vpt_block): New struct type for vpt blocks.
1551 (vpt_block_state): Global struct to keep track of state.
1552 (mve_extract_pred_mask): New helper function.
1553 (num_instructions_vpt_block): Likewise.
1554 (mark_outside_vpt_block): Likewise.
1555 (mark_inside_vpt_block): Likewise.
1556 (invert_next_predicate_state): Likewise.
1557 (update_next_predicate_state): Likewise.
1558 (update_vpt_block_state): Likewise.
1559 (is_vpt_instruction): Likewise.
1560 (is_mve_encoding_conflict): Add entries for new instructions.
1561 (is_mve_unpredictable): Likewise.
1562 (print_mve_unpredictable): Handle new cases.
1563 (print_instruction_predicate): Likewise.
1564 (print_mve_size): New function.
1565 (print_vec_condition): New function.
1566 (print_insn_mve): Handle vpt blocks and new print operands.
1568 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1570 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1571 8, 14 and 15 for Armv8.1-M Mainline.
1573 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1574 Michael Collison <michael.collison@arm.com>
1576 * arm-dis.c (enum mve_instructions): New enum.
1577 (enum mve_unpredictable): Likewise.
1578 (enum mve_undefined): Likewise.
1579 (struct mopcode32): New struct.
1580 (is_mve_okay_in_it): New function.
1581 (is_mve_architecture): Likewise.
1582 (arm_decode_field): Likewise.
1583 (arm_decode_field_multiple): Likewise.
1584 (is_mve_encoding_conflict): Likewise.
1585 (is_mve_undefined): Likewise.
1586 (is_mve_unpredictable): Likewise.
1587 (print_mve_undefined): Likewise.
1588 (print_mve_unpredictable): Likewise.
1589 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1590 (print_insn_mve): New function.
1591 (print_insn_thumb32): Handle MVE architecture.
1592 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1594 2019-05-10 Nick Clifton <nickc@redhat.com>
1597 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1598 end of the table prematurely.
1600 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1602 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1605 2019-05-11 Alan Modra <amodra@gmail.com>
1607 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1608 when -Mraw is in effect.
1610 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1612 * aarch64-dis-2.c: Regenerate.
1613 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1614 (OP_SVE_BBB): New variant set.
1615 (OP_SVE_DDDD): New variant set.
1616 (OP_SVE_HHH): New variant set.
1617 (OP_SVE_HHHU): New variant set.
1618 (OP_SVE_SSS): New variant set.
1619 (OP_SVE_SSSU): New variant set.
1620 (OP_SVE_SHH): New variant set.
1621 (OP_SVE_SBBU): New variant set.
1622 (OP_SVE_DSS): New variant set.
1623 (OP_SVE_DHHU): New variant set.
1624 (OP_SVE_VMV_HSD_BHS): New variant set.
1625 (OP_SVE_VVU_HSD_BHS): New variant set.
1626 (OP_SVE_VVVU_SD_BH): New variant set.
1627 (OP_SVE_VVVU_BHSD): New variant set.
1628 (OP_SVE_VVV_QHD_DBS): New variant set.
1629 (OP_SVE_VVV_HSD_BHS): New variant set.
1630 (OP_SVE_VVV_HSD_BHS2): New variant set.
1631 (OP_SVE_VVV_BHS_HSD): New variant set.
1632 (OP_SVE_VV_BHS_HSD): New variant set.
1633 (OP_SVE_VVV_SD): New variant set.
1634 (OP_SVE_VVU_BHS_HSD): New variant set.
1635 (OP_SVE_VZVV_SD): New variant set.
1636 (OP_SVE_VZVV_BH): New variant set.
1637 (OP_SVE_VZV_SD): New variant set.
1638 (aarch64_opcode_table): Add sve2 instructions.
1640 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1642 * aarch64-asm-2.c: Regenerated.
1643 * aarch64-dis-2.c: Regenerated.
1644 * aarch64-opc-2.c: Regenerated.
1645 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1646 for SVE_SHLIMM_UNPRED_22.
1647 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1648 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1651 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1653 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1654 sve_size_tsz_bhs iclass encode.
1655 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1656 sve_size_tsz_bhs iclass decode.
1658 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1660 * aarch64-asm-2.c: Regenerated.
1661 * aarch64-dis-2.c: Regenerated.
1662 * aarch64-opc-2.c: Regenerated.
1663 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1664 for SVE_Zm4_11_INDEX.
1665 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1666 (fields): Handle SVE_i2h field.
1667 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1668 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1670 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1672 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1673 sve_shift_tsz_bhsd iclass encode.
1674 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1675 sve_shift_tsz_bhsd iclass decode.
1677 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1679 * aarch64-asm-2.c: Regenerated.
1680 * aarch64-dis-2.c: Regenerated.
1681 * aarch64-opc-2.c: Regenerated.
1682 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1683 (aarch64_encode_variant_using_iclass): Handle
1684 sve_shift_tsz_hsd iclass encode.
1685 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1686 sve_shift_tsz_hsd iclass decode.
1687 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1688 for SVE_SHRIMM_UNPRED_22.
1689 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1690 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1693 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1695 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1696 sve_size_013 iclass encode.
1697 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1698 sve_size_013 iclass decode.
1700 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1702 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1703 sve_size_bh iclass encode.
1704 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1705 sve_size_bh iclass decode.
1707 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1709 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1710 sve_size_sd2 iclass encode.
1711 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1712 sve_size_sd2 iclass decode.
1713 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1714 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1716 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1718 * aarch64-asm-2.c: Regenerated.
1719 * aarch64-dis-2.c: Regenerated.
1720 * aarch64-opc-2.c: Regenerated.
1721 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1723 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1724 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1726 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1728 * aarch64-asm-2.c: Regenerated.
1729 * aarch64-dis-2.c: Regenerated.
1730 * aarch64-opc-2.c: Regenerated.
1731 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1732 for SVE_Zm3_11_INDEX.
1733 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1734 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1735 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1737 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1739 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1741 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1742 sve_size_hsd2 iclass encode.
1743 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1744 sve_size_hsd2 iclass decode.
1745 * aarch64-opc.c (fields): Handle SVE_size field.
1746 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1748 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1750 * aarch64-asm-2.c: Regenerated.
1751 * aarch64-dis-2.c: Regenerated.
1752 * aarch64-opc-2.c: Regenerated.
1753 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1755 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1756 (fields): Handle SVE_rot3 field.
1757 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1758 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1760 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1762 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1765 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1768 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1769 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1770 aarch64_feature_sve2bitperm): New feature sets.
1771 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1772 for feature set addresses.
1773 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1774 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1776 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1777 Faraz Shahbazker <fshahbazker@wavecomp.com>
1779 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1780 argument and set ASE_EVA_R6 appropriately.
1781 (set_default_mips_dis_options): Pass ISA to above.
1782 (parse_mips_dis_option): Likewise.
1783 * mips-opc.c (EVAR6): New macro.
1784 (mips_builtin_opcodes): Add llwpe, scwpe.
1786 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1788 * aarch64-asm-2.c: Regenerated.
1789 * aarch64-dis-2.c: Regenerated.
1790 * aarch64-opc-2.c: Regenerated.
1791 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1792 AARCH64_OPND_TME_UIMM16.
1793 (aarch64_print_operand): Likewise.
1794 * aarch64-tbl.h (QL_IMM_NIL): New.
1797 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1799 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1801 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1803 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1804 Faraz Shahbazker <fshahbazker@wavecomp.com>
1806 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1808 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1810 * s12z-opc.h: Add extern "C" bracketing to help
1811 users who wish to use this interface in c++ code.
1813 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1815 * s12z-opc.c (bm_decode): Handle bit map operations with the
1818 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1820 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1821 specifier. Add entries for VLDR and VSTR of system registers.
1822 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1823 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1824 of %J and %K format specifier.
1826 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1828 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1829 Add new entries for VSCCLRM instruction.
1830 (print_insn_coprocessor): Handle new %C format control code.
1832 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1834 * arm-dis.c (enum isa): New enum.
1835 (struct sopcode32): New structure.
1836 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1837 set isa field of all current entries to ANY.
1838 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1839 Only match an entry if its isa field allows the current mode.
1841 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1843 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1845 (print_insn_thumb32): Add logic to print %n CLRM register list.
1847 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1849 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1852 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1854 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1855 (print_insn_thumb32): Edit the switch case for %Z.
1857 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1859 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1861 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1863 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1865 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1867 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1869 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1871 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1872 Arm register with r13 and r15 unpredictable.
1873 (thumb32_opcodes): New instructions for bfx and bflx.
1875 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1877 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1879 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1881 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1883 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1885 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1887 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1889 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1891 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1893 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1894 "optr". ("operator" is a reserved word in c++).
1896 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1898 * aarch64-opc.c (aarch64_print_operand): Add case for
1900 (verify_constraints): Likewise.
1901 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1902 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1903 to accept Rt|SP as first operand.
1904 (AARCH64_OPERANDS): Add new Rt_SP.
1905 * aarch64-asm-2.c: Regenerated.
1906 * aarch64-dis-2.c: Regenerated.
1907 * aarch64-opc-2.c: Regenerated.
1909 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1911 * aarch64-asm-2.c: Regenerated.
1912 * aarch64-dis-2.c: Likewise.
1913 * aarch64-opc-2.c: Likewise.
1914 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1916 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1918 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1920 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1922 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1923 * i386-init.h: Regenerated.
1925 2019-04-07 Alan Modra <amodra@gmail.com>
1927 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1928 op_separator to control printing of spaces, comma and parens
1929 rather than need_comma, need_paren and spaces vars.
1931 2019-04-07 Alan Modra <amodra@gmail.com>
1934 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1935 (print_insn_neon, print_insn_arm): Likewise.
1937 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1939 * i386-dis-evex.h (evex_table): Updated to support BF16
1941 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1942 and EVEX_W_0F3872_P_3.
1943 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1944 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1945 * i386-opc.h (enum): Add CpuAVX512_BF16.
1946 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1947 * i386-opc.tbl: Add AVX512 BF16 instructions.
1948 * i386-init.h: Regenerated.
1949 * i386-tbl.h: Likewise.
1951 2019-04-05 Alan Modra <amodra@gmail.com>
1953 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1954 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1955 to favour printing of "-" branch hint when using the "y" bit.
1956 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1958 2019-04-05 Alan Modra <amodra@gmail.com>
1960 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1961 opcode until first operand is output.
1963 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1966 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1967 (valid_bo_post_v2): Add support for 'at' branch hints.
1968 (insert_bo): Only error on branch on ctr.
1969 (get_bo_hint_mask): New function.
1970 (insert_boe): Add new 'branch_taken' formal argument. Add support
1971 for inserting 'at' branch hints.
1972 (extract_boe): Add new 'branch_taken' formal argument. Add support
1973 for extracting 'at' branch hints.
1974 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1975 (BOE): Delete operand.
1976 (BOM, BOP): New operands.
1978 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1979 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1980 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1981 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1982 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1983 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1984 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1985 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1986 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1987 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1988 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1989 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1990 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1991 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1992 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1993 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1994 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1995 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1996 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1997 bttarl+>: New extended mnemonics.
1999 2019-03-28 Alan Modra <amodra@gmail.com>
2002 * ppc-opc.c (BTF): Define.
2003 (powerpc_opcodes): Use for mtfsb*.
2004 * ppc-dis.c (print_insn_powerpc): Print fields with both
2005 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2007 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2009 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2010 (mapping_symbol_for_insn): Implement new algorithm.
2011 (print_insn): Remove duplicate code.
2013 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2015 * aarch64-dis.c (print_insn_aarch64):
2018 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2020 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2023 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2025 * aarch64-dis.c (last_stop_offset): New.
2026 (print_insn_aarch64): Use stop_offset.
2028 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2031 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2033 * i386-init.h: Regenerated.
2035 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2038 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2039 vmovdqu16, vmovdqu32 and vmovdqu64.
2040 * i386-tbl.h: Regenerated.
2042 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2044 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2045 from vstrszb, vstrszh, and vstrszf.
2047 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2049 * s390-opc.txt: Add instruction descriptions.
2051 2019-02-08 Jim Wilson <jimw@sifive.com>
2053 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2056 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2058 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2060 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2063 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2064 * aarch64-opc.c (verify_elem_sd): New.
2065 (fields): Add FLD_sz entr.
2066 * aarch64-tbl.h (_SIMD_INSN): New.
2067 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2068 fmulx scalar and vector by element isns.
2070 2019-02-07 Nick Clifton <nickc@redhat.com>
2072 * po/sv.po: Updated Swedish translation.
2074 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2076 * s390-mkopc.c (main): Accept arch13 as cpu string.
2077 * s390-opc.c: Add new instruction formats and instruction opcode
2079 * s390-opc.txt: Add new arch13 instructions.
2081 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2083 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2084 (aarch64_opcode): Change encoding for stg, stzg
2086 * aarch64-asm-2.c: Regenerated.
2087 * aarch64-dis-2.c: Regenerated.
2088 * aarch64-opc-2.c: Regenerated.
2090 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2092 * aarch64-asm-2.c: Regenerated.
2093 * aarch64-dis-2.c: Likewise.
2094 * aarch64-opc-2.c: Likewise.
2095 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2097 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2098 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2100 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2101 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2102 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2103 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2104 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2105 case for ldstgv_indexed.
2106 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2107 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2108 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2109 * aarch64-asm-2.c: Regenerated.
2110 * aarch64-dis-2.c: Regenerated.
2111 * aarch64-opc-2.c: Regenerated.
2113 2019-01-23 Nick Clifton <nickc@redhat.com>
2115 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2117 2019-01-21 Nick Clifton <nickc@redhat.com>
2119 * po/de.po: Updated German translation.
2120 * po/uk.po: Updated Ukranian translation.
2122 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2123 * mips-dis.c (mips_arch_choices): Fix typo in
2124 gs464, gs464e and gs264e descriptors.
2126 2019-01-19 Nick Clifton <nickc@redhat.com>
2128 * configure: Regenerate.
2129 * po/opcodes.pot: Regenerate.
2131 2018-06-24 Nick Clifton <nickc@redhat.com>
2133 2.32 branch created.
2135 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2137 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2139 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2142 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2144 * configure: Regenerate.
2146 2019-01-07 Alan Modra <amodra@gmail.com>
2148 * configure: Regenerate.
2149 * po/POTFILES.in: Regenerate.
2151 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2153 * s12z-opc.c: New file.
2154 * s12z-opc.h: New file.
2155 * s12z-dis.c: Removed all code not directly related to display
2156 of instructions. Used the interface provided by the new files
2158 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2159 * Makefile.in: Regenerate.
2160 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2161 * configure: Regenerate.
2163 2019-01-01 Alan Modra <amodra@gmail.com>
2165 Update year range in copyright notice of all files.
2167 For older changes see ChangeLog-2018
2169 Copyright (C) 2019 Free Software Foundation, Inc.
2171 Copying and distribution of this file, with or without modification,
2172 are permitted in any medium without royalty provided the copyright
2173 notice and this notice are preserved.
2179 version-control: never