opcodes/ChangeLog

   1 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/24633
   4         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
   5         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
   6         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
   7         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
   8         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
   9         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
  10         EVEX_LEN_0F3A1B_P_2_W_1.
  11         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
  12         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
  13         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
  14         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
  15         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
  16         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
  17         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
  18         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
  19
  20 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
  21
  22         PR binutils/24626
  23         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
  24         EVEX.vvvv when disassembling VEX and EVEX instructions.
  25         (OP_VEX): Set vex.register_specifier to 0 after readding
  26         vex.register_specifier.
  27         (OP_Vex_2src_1): Likewise.
  28         (OP_Vex_2src_2): Likewise.
  29         (OP_LWP_E): Likewise.
  30         (OP_EX_Vex): Don't check vex.register_specifier.
  31         (OP_XMM_Vex): Likewise.
  32
  33 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  34             Lili Cui  <lili.cui@intel.com>
  35
  36         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
  37         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
  38         instructions.
  39         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
  40         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
  41         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
  42         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
  43         (i386_cpu_flags): Add cpuavx512_vp2intersect.
  44         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
  45         * i386-init.h: Regenerated.
  46         * i386-tbl.h: Likewise.
  47
  48 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
  49             Lili Cui  <lili.cui@intel.com>
  50
  51         * doc/c-i386.texi: Document enqcmd.
  52         * testsuite/gas/i386/enqcmd-intel.d: New file.
  53         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
  54         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
  55         * testsuite/gas/i386/enqcmd.d: Likewise.
  56         * testsuite/gas/i386/enqcmd.s: Likewise.
  57         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
  58         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
  59         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
  60         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
  61         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
  62         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
  63         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
  64         and x86-64-enqcmd.
  65
  66 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
  67
  68         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
  69
  70 2019-06-03  Alan Modra  <amodra@gmail.com>
  71
  72         * ppc-dis.c (prefix_opcd_indices): Correct size.
  73
  74 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
  75
  76         PR gas/24625
  77         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
  78         Disp8ShiftVL.
  79         * i386-tbl.h: Regenerated.
  80
  81 2019-05-24  Alan Modra  <amodra@gmail.com>
  82
  83         * po/POTFILES.in: Regenerate.
  84
  85 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  86             Alan Modra  <amodra@gmail.com>
  87
  88         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
  89         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
  90         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
  91         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
  92         XTOP>): Define and add entries.
  93         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
  94         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
  95         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
  96         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
  97
  98 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  99             Alan Modra  <amodra@gmail.com>
 100
 101         * ppc-dis.c (ppc_opts): Add "future" entry.
 102         (PREFIX_OPCD_SEGS): Define.
 103         (prefix_opcd_indices): New array.
 104         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 105         (lookup_prefix): New function.
 106         (print_insn_powerpc): Handle 64-bit prefix instructions.
 107         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 108         (PMRR, POWERXX): Define.
 109         (prefix_opcodes): New instruction table.
 110         (prefix_num_opcodes): New constant.
 111
 112 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 113
 114         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 115         * configure: Regenerated.
 116         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 117         and cpu/bpf.opc.
 118         (HFILES): Add bpf-desc.h and bpf-opc.h.
 119         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 120         bpf-ibld.c and bpf-opc.c.
 121         (BPF_DEPS): Define.
 122         * Makefile.in: Regenerated.
 123         * disassemble.c (ARCH_bpf): Define.
 124         (disassembler): Add case for bfd_arch_bpf.
 125         (disassemble_init_for_target): Likewise.
 126         (enum epbf_isa_attr): Define.
 127         * disassemble.h: extern print_insn_bpf.
 128         * bpf-asm.c: Generated.
 129         * bpf-opc.h: Likewise.
 130         * bpf-opc.c: Likewise.
 131         * bpf-ibld.c: Likewise.
 132         * bpf-dis.c: Likewise.
 133         * bpf-desc.h: Likewise.
 134         * bpf-desc.c: Likewise.
 135
 136 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 137
 138         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 139         and VMSR with the new operands.
 140
 141 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 142
 143         * arm-dis.c (enum mve_instructions): New enum
 144         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 145         and cneg.
 146         (mve_opcodes): New instructions as above.
 147         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 148         csneg and csel.
 149         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 150
 151 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 152
 153         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 154         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 155         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 156         uqshl, urshrl and urshr.
 157         (is_mve_okay_in_it): Add new instructions to TRUE list.
 158         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 159         (print_insn_mve): Updated to accept new %j,
 160         %<bitfield>m and %<bitfield>n patterns.
 161
 162 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 163
 164         * mips-opc.c (mips_builtin_opcodes): Change source register
 165         constraint for DAUI.
 166
 167 2019-05-20  Nick Clifton  <nickc@redhat.com>
 168
 169         * po/fr.po: Updated French translation.
 170
 171 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 172             Michael Collison <michael.collison@arm.com>
 173
 174         * arm-dis.c (thumb32_opcodes): Add new instructions.
 175         (enum mve_instructions): Likewise.
 176         (enum mve_undefined): Add new reasons.
 177         (is_mve_encoding_conflict): Handle new instructions.
 178         (is_mve_undefined): Likewise.
 179         (is_mve_unpredictable): Likewise.
 180         (print_mve_undefined): Likewise.
 181         (print_mve_size): Likewise.
 182
 183 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 184             Michael Collison <michael.collison@arm.com>
 185
 186         * arm-dis.c (thumb32_opcodes): Add new instructions.
 187         (enum mve_instructions): Likewise.
 188         (is_mve_encoding_conflict): Handle new instructions.
 189         (is_mve_undefined): Likewise.
 190         (is_mve_unpredictable): Likewise.
 191         (print_mve_size): Likewise.
 192
 193 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 194             Michael Collison <michael.collison@arm.com>
 195
 196         * arm-dis.c (thumb32_opcodes): Add new instructions.
 197         (enum mve_instructions): Likewise.
 198         (is_mve_encoding_conflict): Likewise.
 199         (is_mve_unpredictable): Likewise.
 200         (print_mve_size): Likewise.
 201
 202 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 203             Michael Collison <michael.collison@arm.com>
 204
 205         * arm-dis.c (thumb32_opcodes): Add new instructions.
 206         (enum mve_instructions): Likewise.
 207         (is_mve_encoding_conflict): Handle new instructions.
 208         (is_mve_undefined): Likewise.
 209         (is_mve_unpredictable): Likewise.
 210         (print_mve_size): Likewise.
 211
 212 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 213             Michael Collison <michael.collison@arm.com>
 214
 215         * arm-dis.c (thumb32_opcodes): Add new instructions.
 216         (enum mve_instructions): Likewise.
 217         (is_mve_encoding_conflict): Handle new instructions.
 218         (is_mve_undefined): Likewise.
 219         (is_mve_unpredictable): Likewise.
 220         (print_mve_size): Likewise.
 221         (print_insn_mve): Likewise.
 222
 223 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 224             Michael Collison <michael.collison@arm.com>
 225
 226         * arm-dis.c (thumb32_opcodes): Add new instructions.
 227         (print_insn_thumb32): Handle new instructions.
 228
 229 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 230             Michael Collison <michael.collison@arm.com>
 231
 232         * arm-dis.c (enum mve_instructions): Add new instructions.
 233         (enum mve_undefined): Add new reasons.
 234         (is_mve_encoding_conflict): Handle new instructions.
 235         (is_mve_undefined): Likewise.
 236         (is_mve_unpredictable): Likewise.
 237         (print_mve_undefined): Likewise.
 238         (print_mve_size): Likewise.
 239         (print_mve_shift_n): Likewise.
 240         (print_insn_mve): Likewise.
 241
 242 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 243             Michael Collison <michael.collison@arm.com>
 244
 245         * arm-dis.c (enum mve_instructions): Add new instructions.
 246         (is_mve_encoding_conflict): Handle new instructions.
 247         (is_mve_unpredictable): Likewise.
 248         (print_mve_rotate): Likewise.
 249         (print_mve_size): Likewise.
 250         (print_insn_mve): Likewise.
 251
 252 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 253             Michael Collison <michael.collison@arm.com>
 254
 255         * arm-dis.c (enum mve_instructions): Add new instructions.
 256         (is_mve_encoding_conflict): Handle new instructions.
 257         (is_mve_unpredictable): Likewise.
 258         (print_mve_size): Likewise.
 259         (print_insn_mve): Likewise.
 260
 261 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 262             Michael Collison <michael.collison@arm.com>
 263
 264         * arm-dis.c (enum mve_instructions): Add new instructions.
 265         (enum mve_undefined): Add new reasons.
 266         (is_mve_encoding_conflict): Handle new instructions.
 267         (is_mve_undefined): Likewise.
 268         (is_mve_unpredictable): Likewise.
 269         (print_mve_undefined): Likewise.
 270         (print_mve_size): Likewise.
 271         (print_insn_mve): Likewise.
 272
 273 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 274             Michael Collison <michael.collison@arm.com>
 275
 276         * arm-dis.c (enum mve_instructions): Add new instructions.
 277         (is_mve_encoding_conflict): Handle new instructions.
 278         (is_mve_undefined): Likewise.
 279         (is_mve_unpredictable): Likewise.
 280         (print_mve_size): Likewise.
 281         (print_insn_mve): Likewise.
 282
 283 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 284             Michael Collison <michael.collison@arm.com>
 285
 286         * arm-dis.c (enum mve_instructions): Add new instructions.
 287         (enum mve_unpredictable): Add new reasons.
 288         (enum mve_undefined): Likewise.
 289         (is_mve_okay_in_it): Handle new isntructions.
 290         (is_mve_encoding_conflict): Likewise.
 291         (is_mve_undefined): Likewise.
 292         (is_mve_unpredictable): Likewise.
 293         (print_mve_vmov_index): Likewise.
 294         (print_simd_imm8): Likewise.
 295         (print_mve_undefined): Likewise.
 296         (print_mve_unpredictable): Likewise.
 297         (print_mve_size): Likewise.
 298         (print_insn_mve): Likewise.
 299
 300 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 301             Michael Collison <michael.collison@arm.com>
 302
 303         * arm-dis.c (enum mve_instructions): Add new instructions.
 304         (enum mve_unpredictable): Add new reasons.
 305         (enum mve_undefined): Likewise.
 306         (is_mve_encoding_conflict): Handle new instructions.
 307         (is_mve_undefined): Likewise.
 308         (is_mve_unpredictable): Likewise.
 309         (print_mve_undefined): Likewise.
 310         (print_mve_unpredictable): Likewise.
 311         (print_mve_rounding_mode): Likewise.
 312         (print_mve_vcvt_size): Likewise.
 313         (print_mve_size): Likewise.
 314         (print_insn_mve): Likewise.
 315
 316 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 317             Michael Collison <michael.collison@arm.com>
 318
 319         * arm-dis.c (enum mve_instructions): Add new instructions.
 320         (enum mve_unpredictable): Add new reasons.
 321         (enum mve_undefined): Likewise.
 322         (is_mve_undefined): Handle new instructions.
 323         (is_mve_unpredictable): Likewise.
 324         (print_mve_undefined): Likewise.
 325         (print_mve_unpredictable): Likewise.
 326         (print_mve_size): Likewise.
 327         (print_insn_mve): Likewise.
 328
 329 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 330             Michael Collison <michael.collison@arm.com>
 331
 332         * arm-dis.c (enum mve_instructions): Add new instructions.
 333         (enum mve_undefined): Add new reasons.
 334         (insns): Add new instructions.
 335         (is_mve_encoding_conflict):
 336         (print_mve_vld_str_addr): New print function.
 337         (is_mve_undefined): Handle new instructions.
 338         (is_mve_unpredictable): Likewise.
 339         (print_mve_undefined): Likewise.
 340         (print_mve_size): Likewise.
 341         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 342         (print_insn_mve):  Handle new operands.
 343
 344 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 345             Michael Collison <michael.collison@arm.com>
 346
 347         * arm-dis.c (enum mve_instructions): Add new instructions.
 348         (enum mve_unpredictable): Add new reasons.
 349         (is_mve_encoding_conflict): Handle new instructions.
 350         (is_mve_unpredictable): Likewise.
 351         (mve_opcodes): Add new instructions.
 352         (print_mve_unpredictable): Handle new reasons.
 353         (print_mve_register_blocks): New print function.
 354         (print_mve_size): Handle new instructions.
 355         (print_insn_mve): Likewise.
 356
 357 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 358             Michael Collison <michael.collison@arm.com>
 359
 360         * arm-dis.c (enum mve_instructions): Add new instructions.
 361         (enum mve_unpredictable): Add new reasons.
 362         (enum mve_undefined): Likewise.
 363         (is_mve_encoding_conflict): Handle new instructions.
 364         (is_mve_undefined): Likewise.
 365         (is_mve_unpredictable): Likewise.
 366         (coprocessor_opcodes): Move NEON VDUP from here...
 367         (neon_opcodes): ... to here.
 368         (mve_opcodes): Add new instructions.
 369         (print_mve_undefined):  Handle new reasons.
 370         (print_mve_unpredictable): Likewise.
 371         (print_mve_size): Handle new instructions.
 372         (print_insn_neon): Handle vdup.
 373         (print_insn_mve): Handle new operands.
 374
 375 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 376             Michael Collison <michael.collison@arm.com>
 377
 378         * arm-dis.c (enum mve_instructions): Add new instructions.
 379         (enum mve_unpredictable): Add new values.
 380         (mve_opcodes): Add new instructions.
 381         (vec_condnames): New array with vector conditions.
 382         (mve_predicatenames): New array with predicate suffixes.
 383         (mve_vec_sizename): New array with vector sizes.
 384         (enum vpt_pred_state): New enum with vector predication states.
 385         (struct vpt_block): New struct type for vpt blocks.
 386         (vpt_block_state): Global struct to keep track of state.
 387         (mve_extract_pred_mask): New helper function.
 388         (num_instructions_vpt_block): Likewise.
 389         (mark_outside_vpt_block): Likewise.
 390         (mark_inside_vpt_block): Likewise.
 391         (invert_next_predicate_state): Likewise.
 392         (update_next_predicate_state): Likewise.
 393         (update_vpt_block_state): Likewise.
 394         (is_vpt_instruction): Likewise.
 395         (is_mve_encoding_conflict): Add entries for new instructions.
 396         (is_mve_unpredictable): Likewise.
 397         (print_mve_unpredictable): Handle new cases.
 398         (print_instruction_predicate): Likewise.
 399         (print_mve_size): New function.
 400         (print_vec_condition): New function.
 401         (print_insn_mve): Handle vpt blocks and new print operands.
 402
 403 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 404
 405         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 406         8, 14 and 15 for Armv8.1-M Mainline.
 407
 408 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 409             Michael Collison <michael.collison@arm.com>
 410
 411         * arm-dis.c (enum mve_instructions): New enum.
 412         (enum mve_unpredictable): Likewise.
 413         (enum mve_undefined): Likewise.
 414         (struct mopcode32): New struct.
 415         (is_mve_okay_in_it): New function.
 416         (is_mve_architecture): Likewise.
 417         (arm_decode_field): Likewise.
 418         (arm_decode_field_multiple): Likewise.
 419         (is_mve_encoding_conflict): Likewise.
 420         (is_mve_undefined): Likewise.
 421         (is_mve_unpredictable): Likewise.
 422         (print_mve_undefined): Likewise.
 423         (print_mve_unpredictable): Likewise.
 424         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 425         (print_insn_mve): New function.
 426         (print_insn_thumb32): Handle MVE architecture.
 427         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 428
 429 2019-05-10  Nick Clifton  <nickc@redhat.com>
 430
 431         PR 24538
 432         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 433         end of the table prematurely.
 434
 435 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 436
 437         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 438         macros for R6.
 439
 440 2019-05-11  Alan Modra  <amodra@gmail.com>
 441
 442         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 443         when -Mraw is in effect.
 444
 445 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 446
 447         * aarch64-dis-2.c: Regenerate.
 448         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 449         (OP_SVE_BBB): New variant set.
 450         (OP_SVE_DDDD): New variant set.
 451         (OP_SVE_HHH): New variant set.
 452         (OP_SVE_HHHU): New variant set.
 453         (OP_SVE_SSS): New variant set.
 454         (OP_SVE_SSSU): New variant set.
 455         (OP_SVE_SHH): New variant set.
 456         (OP_SVE_SBBU): New variant set.
 457         (OP_SVE_DSS): New variant set.
 458         (OP_SVE_DHHU): New variant set.
 459         (OP_SVE_VMV_HSD_BHS): New variant set.
 460         (OP_SVE_VVU_HSD_BHS): New variant set.
 461         (OP_SVE_VVVU_SD_BH): New variant set.
 462         (OP_SVE_VVVU_BHSD): New variant set.
 463         (OP_SVE_VVV_QHD_DBS): New variant set.
 464         (OP_SVE_VVV_HSD_BHS): New variant set.
 465         (OP_SVE_VVV_HSD_BHS2): New variant set.
 466         (OP_SVE_VVV_BHS_HSD): New variant set.
 467         (OP_SVE_VV_BHS_HSD): New variant set.
 468         (OP_SVE_VVV_SD): New variant set.
 469         (OP_SVE_VVU_BHS_HSD): New variant set.
 470         (OP_SVE_VZVV_SD): New variant set.
 471         (OP_SVE_VZVV_BH): New variant set.
 472         (OP_SVE_VZV_SD): New variant set.
 473         (aarch64_opcode_table): Add sve2 instructions.
 474
 475 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 476
 477         * aarch64-asm-2.c: Regenerated.
 478         * aarch64-dis-2.c: Regenerated.
 479         * aarch64-opc-2.c: Regenerated.
 480         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 481         for SVE_SHLIMM_UNPRED_22.
 482         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 483         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 484         operand.
 485
 486 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 487
 488         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 489         sve_size_tsz_bhs iclass encode.
 490         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 491         sve_size_tsz_bhs iclass decode.
 492
 493 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 494
 495         * aarch64-asm-2.c: Regenerated.
 496         * aarch64-dis-2.c: Regenerated.
 497         * aarch64-opc-2.c: Regenerated.
 498         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 499         for SVE_Zm4_11_INDEX.
 500         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 501         (fields): Handle SVE_i2h field.
 502         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 503         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 504
 505 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 506
 507         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 508         sve_shift_tsz_bhsd iclass encode.
 509         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 510         sve_shift_tsz_bhsd iclass decode.
 511
 512 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 513
 514         * aarch64-asm-2.c: Regenerated.
 515         * aarch64-dis-2.c: Regenerated.
 516         * aarch64-opc-2.c: Regenerated.
 517         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 518         (aarch64_encode_variant_using_iclass): Handle
 519         sve_shift_tsz_hsd iclass encode.
 520         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 521         sve_shift_tsz_hsd iclass decode.
 522         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 523         for SVE_SHRIMM_UNPRED_22.
 524         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 525         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 526         operand.
 527
 528 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 529
 530         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 531         sve_size_013 iclass encode.
 532         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 533         sve_size_013 iclass decode.
 534
 535 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 536
 537         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 538         sve_size_bh iclass encode.
 539         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 540         sve_size_bh iclass decode.
 541
 542 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 543
 544         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 545         sve_size_sd2 iclass encode.
 546         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 547         sve_size_sd2 iclass decode.
 548         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 549         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 550
 551 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 552
 553         * aarch64-asm-2.c: Regenerated.
 554         * aarch64-dis-2.c: Regenerated.
 555         * aarch64-opc-2.c: Regenerated.
 556         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 557         for SVE_ADDR_ZX.
 558         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 559         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 560
 561 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 562
 563         * aarch64-asm-2.c: Regenerated.
 564         * aarch64-dis-2.c: Regenerated.
 565         * aarch64-opc-2.c: Regenerated.
 566         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 567         for SVE_Zm3_11_INDEX.
 568         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 569         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 570         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 571         fields.
 572         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 573
 574 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 575
 576         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 577         sve_size_hsd2 iclass encode.
 578         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 579         sve_size_hsd2 iclass decode.
 580         * aarch64-opc.c (fields): Handle SVE_size field.
 581         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 582
 583 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 584
 585         * aarch64-asm-2.c: Regenerated.
 586         * aarch64-dis-2.c: Regenerated.
 587         * aarch64-opc-2.c: Regenerated.
 588         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 589         for SVE_IMM_ROT3.
 590         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 591         (fields): Handle SVE_rot3 field.
 592         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 593         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 594
 595 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 596
 597         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 598         instructions.
 599
 600 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 601
 602         * aarch64-tbl.h
 603         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 604         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 605         aarch64_feature_sve2bitperm): New feature sets.
 606         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 607         for feature set addresses.
 608         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 609         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 610
 611 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 612             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 613
 614         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 615         argument and set ASE_EVA_R6 appropriately.
 616         (set_default_mips_dis_options): Pass ISA to above.
 617         (parse_mips_dis_option): Likewise.
 618         * mips-opc.c (EVAR6): New macro.
 619         (mips_builtin_opcodes): Add llwpe, scwpe.
 620
 621 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 622
 623         * aarch64-asm-2.c: Regenerated.
 624         * aarch64-dis-2.c: Regenerated.
 625         * aarch64-opc-2.c: Regenerated.
 626         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 627         AARCH64_OPND_TME_UIMM16.
 628         (aarch64_print_operand): Likewise.
 629         * aarch64-tbl.h (QL_IMM_NIL): New.
 630         (TME): New.
 631         (_TME_INSN): New.
 632         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 633
 634 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 635
 636         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 637
 638 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 639             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 640
 641         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 642
 643 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 644
 645         * s12z-opc.h: Add extern "C" bracketing to help
 646         users who wish to use this interface in c++ code.
 647
 648 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 649
 650         * s12z-opc.c (bm_decode): Handle bit map operations with the
 651         "reserved0" mode.
 652
 653 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 654
 655         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 656         specifier.  Add entries for VLDR and VSTR of system registers.
 657         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 658         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 659         of %J and %K format specifier.
 660
 661 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 662
 663         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 664         Add new entries for VSCCLRM instruction.
 665         (print_insn_coprocessor): Handle new %C format control code.
 666
 667 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 668
 669         * arm-dis.c (enum isa): New enum.
 670         (struct sopcode32): New structure.
 671         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 672         set isa field of all current entries to ANY.
 673         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 674         Only match an entry if its isa field allows the current mode.
 675
 676 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 677
 678         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 679         CLRM.
 680         (print_insn_thumb32): Add logic to print %n CLRM register list.
 681
 682 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 683
 684         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 685         and %Q patterns.
 686
 687 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 688
 689         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 690         (print_insn_thumb32): Edit the switch case for %Z.
 691
 692 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 693
 694         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 695
 696 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 697
 698         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 699
 700 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 701
 702         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 703
 704 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 705
 706         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 707         Arm register with r13 and r15 unpredictable.
 708         (thumb32_opcodes): New instructions for bfx and bflx.
 709
 710 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 711
 712         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 713
 714 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 715
 716         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 717
 718 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 719
 720         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 721
 722 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 723
 724         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 725
 726 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 727
 728         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 729         "optr". ("operator" is a reserved word in c++).
 730
 731 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 732
 733         * aarch64-opc.c (aarch64_print_operand): Add case for
 734         AARCH64_OPND_Rt_SP.
 735         (verify_constraints): Likewise.
 736         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 737         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 738         to accept Rt|SP as first operand.
 739         (AARCH64_OPERANDS): Add new Rt_SP.
 740         * aarch64-asm-2.c: Regenerated.
 741         * aarch64-dis-2.c: Regenerated.
 742         * aarch64-opc-2.c: Regenerated.
 743
 744 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 745
 746         * aarch64-asm-2.c: Regenerated.
 747         * aarch64-dis-2.c: Likewise.
 748         * aarch64-opc-2.c: Likewise.
 749         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 750
 751 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 752
 753         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 754
 755 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 756
 757         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 758         * i386-init.h: Regenerated.
 759
 760 2019-04-07  Alan Modra  <amodra@gmail.com>
 761
 762         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 763         op_separator to control printing of spaces, comma and parens
 764         rather than need_comma, need_paren and spaces vars.
 765
 766 2019-04-07  Alan Modra  <amodra@gmail.com>
 767
 768         PR 24421
 769         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 770         (print_insn_neon, print_insn_arm): Likewise.
 771
 772 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 773
 774         * i386-dis-evex.h (evex_table): Updated to support BF16
 775         instructions.
 776         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 777         and EVEX_W_0F3872_P_3.
 778         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 779         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 780         * i386-opc.h (enum): Add CpuAVX512_BF16.
 781         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 782         * i386-opc.tbl: Add AVX512 BF16 instructions.
 783         * i386-init.h: Regenerated.
 784         * i386-tbl.h: Likewise.
 785
 786 2019-04-05  Alan Modra  <amodra@gmail.com>
 787
 788         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 789         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 790         to favour printing of "-" branch hint when using the "y" bit.
 791         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 792
 793 2019-04-05  Alan Modra  <amodra@gmail.com>
 794
 795         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 796         opcode until first operand is output.
 797
 798 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 799
 800         PR gas/24349
 801         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 802         (valid_bo_post_v2): Add support for 'at' branch hints.
 803         (insert_bo): Only error on branch on ctr.
 804         (get_bo_hint_mask): New function.
 805         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 806         for inserting 'at' branch hints.
 807         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 808         for extracting 'at' branch hints.
 809         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 810         (BOE): Delete operand.
 811         (BOM, BOP): New operands.
 812         (RM): Update value.
 813         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 814         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 815         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 816         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 817         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 818         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 819         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 820         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 821         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 822         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 823         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 824         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 825         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 826         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 827         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 828         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 829         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 830         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 831         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 832         bttarl+>: New extended mnemonics.
 833
 834 2019-03-28  Alan Modra  <amodra@gmail.com>
 835
 836         PR 24390
 837         * ppc-opc.c (BTF): Define.
 838         (powerpc_opcodes): Use for mtfsb*.
 839         * ppc-dis.c (print_insn_powerpc): Print fields with both
 840         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 841
 842 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 843
 844         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 845         (mapping_symbol_for_insn): Implement new algorithm.
 846         (print_insn): Remove duplicate code.
 847
 848 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 849
 850         * aarch64-dis.c (print_insn_aarch64):
 851         Implement override.
 852
 853 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 854
 855         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 856         order.
 857
 858 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 859
 860         * aarch64-dis.c (last_stop_offset): New.
 861         (print_insn_aarch64): Use stop_offset.
 862
 863 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         PR gas/24359
 866         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 867         CPU_ANY_AVX2_FLAGS.
 868         * i386-init.h: Regenerated.
 869
 870 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         PR gas/24348
 873         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 874         vmovdqu16, vmovdqu32 and vmovdqu64.
 875         * i386-tbl.h: Regenerated.
 876
 877 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 878
 879         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 880         from vstrszb, vstrszh, and vstrszf.
 881
 882 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 883
 884         * s390-opc.txt: Add instruction descriptions.
 885
 886 2019-02-08  Jim Wilson  <jimw@sifive.com>
 887
 888         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 889         <bne>: Likewise.
 890
 891 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 892
 893         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 894
 895 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 896
 897         PR binutils/23212
 898         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 899         * aarch64-opc.c (verify_elem_sd): New.
 900         (fields): Add FLD_sz entr.
 901         * aarch64-tbl.h (_SIMD_INSN): New.
 902         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 903         fmulx scalar and vector by element isns.
 904
 905 2019-02-07  Nick Clifton  <nickc@redhat.com>
 906
 907         * po/sv.po: Updated Swedish translation.
 908
 909 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 910
 911         * s390-mkopc.c (main): Accept arch13 as cpu string.
 912         * s390-opc.c: Add new instruction formats and instruction opcode
 913         masks.
 914         * s390-opc.txt: Add new arch13 instructions.
 915
 916 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 917
 918         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 919         (aarch64_opcode): Change encoding for stg, stzg
 920         st2g and st2zg.
 921         * aarch64-asm-2.c: Regenerated.
 922         * aarch64-dis-2.c: Regenerated.
 923         * aarch64-opc-2.c: Regenerated.
 924
 925 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 926
 927         * aarch64-asm-2.c: Regenerated.
 928         * aarch64-dis-2.c: Likewise.
 929         * aarch64-opc-2.c: Likewise.
 930         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 931
 932 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 933             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 934
 935         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 936         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 937         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 938         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 939         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 940         case for ldstgv_indexed.
 941         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 942         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 943         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 944         * aarch64-asm-2.c: Regenerated.
 945         * aarch64-dis-2.c: Regenerated.
 946         * aarch64-opc-2.c: Regenerated.
 947
 948 2019-01-23  Nick Clifton  <nickc@redhat.com>
 949
 950         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 951
 952 2019-01-21  Nick Clifton  <nickc@redhat.com>
 953
 954         * po/de.po: Updated German translation.
 955         * po/uk.po: Updated Ukranian translation.
 956
 957 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 958         * mips-dis.c (mips_arch_choices): Fix typo in
 959         gs464, gs464e and gs264e descriptors.
 960
 961 2019-01-19  Nick Clifton  <nickc@redhat.com>
 962
 963         * configure: Regenerate.
 964         * po/opcodes.pot: Regenerate.
 965
 966 2018-06-24  Nick Clifton  <nickc@redhat.com>
 967
 968         2.32 branch created.
 969
 970 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 971
 972         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 973         if it is null.
 974         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 975         zero.
 976
 977 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 978
 979         * configure: Regenerate.
 980
 981 2019-01-07  Alan Modra  <amodra@gmail.com>
 982
 983         * configure: Regenerate.
 984         * po/POTFILES.in: Regenerate.
 985
 986 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 987
 988         * s12z-opc.c: New file.
 989         * s12z-opc.h: New file.
 990         * s12z-dis.c: Removed all code not directly related to display
 991         of instructions.  Used the interface provided by the new files
 992         instead.
 993         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 994         * Makefile.in: Regenerate.
 995         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 996         * configure: Regenerate.
 997
 998 2019-01-01  Alan Modra  <amodra@gmail.com>
 999
1000         Update year range in copyright notice of all files.
1001
1002 For older changes see ChangeLog-2018
1003 \f
1004 Copyright (C) 2019 Free Software Foundation, Inc.
1005
1006 Copying and distribution of this file, with or without modification,
1007 are permitted in any medium without royalty provided the copyright
1008 notice and this notice are preserved.
1009
1010 Local Variables:
1011 mode: change-log
1012 left-margin: 8
1013 fill-column: 74
1014 version-control: never
1015 End: