opcodes/ChangeLog

   1 2021-06-17  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
   4         in table.
   5
   6 2021-06-03  Alan Modra  <amodra@gmail.com>
   7
   8         PR 1202
   9         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
  10         Use unsigned int for inst.
  11
  12 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
  13
  14         * arc-dis.c (arc_option_arg_t): New enumeration.
  15         (arc_options): New variable.
  16         (disassembler_options_arc): New function.
  17         (print_arc_disassembler_options): Reimplement in terms of
  18         "disassembler_options_arc".
  19
  20 2021-05-29  Alan Modra  <amodra@gmail.com>
  21
  22         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
  23         Don't special case PPC_OPCODE_RAW.
  24         (lookup_prefix): Likewise.
  25         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
  26         (print_insn_powerpc): ..update caller.
  27         * ppc-opc.c (EXT): Define.
  28         (powerpc_opcodes): Mark extended mnemonics with EXT.
  29         (prefix_opcodes, vle_opcodes): Likewise.
  30         (XISEL, XISEL_MASK): Add cr field and simplify.
  31         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
  32         all isel variants to where the base mnemonic belongs.  Sort dstt,
  33         dststt and dssall.
  34
  35 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  36
  37         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
  38         COP3 opcode instructions.
  39
  40 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  41
  42         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
  43         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
  44         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
  45         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
  46         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
  47         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
  48         "cop2", and "cop3" entries.
  49
  50 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  51
  52         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
  53         entries and associated comments.
  54
  55 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  56
  57         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
  58         of "c0".
  59
  60 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  61
  62         * mips-dis.c (mips_cp1_names_mips): New variable.
  63         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
  64         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
  65         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
  66         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
  67         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
  68         "loongson2f".
  69
  70 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  71
  72         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
  73         handling code over to...
  74         <OP_REG_CONTROL>: ... this new case.
  75         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
  76         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
  77         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
  78         replacing the `G' operand code with `g'.  Update "cftc1" and
  79         "cftc2" entries replacing the `E' operand code with `y'.
  80         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
  81         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
  82         entries replacing the `G' operand code with `g'.
  83
  84 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  85
  86         * mips-dis.c (mips_cp0_names_r3900): New variable.
  87         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
  88         for "r3900".
  89
  90 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  91
  92         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
  93         and "mtthc2" to using the `G' rather than `g' operand code for
  94         the coprocessor control register referred.
  95
  96 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  97
  98         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
  99         entries with each other.
 100
 101 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 102
 103         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 104
 105 2021-05-25  Alan Modra  <amodra@gmail.com>
 106
 107         * cris-desc.c: Regenerate.
 108         * cris-desc.h: Regenerate.
 109         * cris-opc.h: Regenerate.
 110         * po/POTFILES.in: Regenerate.
 111
 112 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 113
 114         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 115         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 116         (CGEN_CPUS): Add cris.
 117         (CRIS_DEPS): Define.
 118         (stamp-cris): New rule.
 119         * cgen.sh: Handle desc action.
 120         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 121         * Makefile.in, configure: Regenerate.
 122
 123 2021-05-18  Job Noorman  <mtvec@pm.me>
 124
 125         PR 27814
 126         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 127         the elf objects.
 128
 129 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 130
 131         * arm-dis.c (mve_opcodes): Fix disassembly of
 132         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 133         (is_mve_encoding_conflict): MVE vector loads should not match
 134         when P = W = 0.
 135         (is_mve_unpredictable): It's not unpredictable to use the same
 136         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 137
 138 2021-05-11  Nick Clifton  <nickc@redhat.com>
 139
 140         PR 27840
 141         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 142         the end of the code buffer.
 143
 144 2021-05-06  Stafford Horne  <shorne@gmail.com>
 145
 146         PR 21464
 147         * or1k-asm.c: Regenerate.
 148
 149 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 150
 151         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 152         info->insn_info_valid.
 153
 154 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl (lea): Add Optimize.
 157         * opcodes/i386-tbl.h: Re-generate.
 158
 159 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 160
 161         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 162         of l32r fetch and display referenced literal value.
 163
 164 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 165
 166         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 167         to 4 for literal disassembly.
 168
 169 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 170
 171         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 172         for TLBI instruction.
 173
 174 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 175
 176         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 177         DC instruction.
 178
 179 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 180
 181         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 182         "qualifier".
 183         (convert_mov_to_movewide): Add initializer for "value".
 184
 185 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 186
 187         * aarch64-opc.c: Add RME system registers.
 188
 189 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 190
 191         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 192         "addi d,CV,z" to "c.mv d,CV".
 193
 194 2021-04-12  Alan Modra  <amodra@gmail.com>
 195
 196         * configure.ac (--enable-checking): Add support.
 197         * config.in: Regenerate.
 198         * configure: Regenerate.
 199
 200 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 201
 202         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 203         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 204
 205 2021-04-09  Alan Modra  <amodra@gmail.com>
 206
 207         * ppc-dis.c (struct dis_private): Add "special".
 208         (POWERPC_DIALECT): Delete.  Replace uses with..
 209         (private_data): ..this.  New inline function.
 210         (disassemble_init_powerpc): Init "special" names.
 211         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 212         field of prefix instructions.
 213         (bsearch_reloc, print_got_plt): New functions.
 214         (print_insn_powerpc): For pcrel instructions, print target address
 215         and symbol if known, and decode plt and got loads too.
 216
 217 2021-04-08  Alan Modra  <amodra@gmail.com>
 218
 219         PR 27684
 220         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 221
 222 2021-04-08  Alan Modra  <amodra@gmail.com>
 223
 224         PR 27676
 225         * ppc-opc.c (DCBT_EO): Move earlier.
 226         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 227         (powerpc_operands): Add THCT and THDS entries.
 228         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 229
 230 2021-04-06  Alan Modra  <amodra@gmail.com>
 231
 232         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 233         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 234         symbol_at_address_func.
 235
 236 2021-04-05  Alan Modra  <amodra@gmail.com>
 237
 238         * configure.ac: Don't check for limits.h, string.h, strings.h or
 239         stdlib.h.
 240         (AC_ISC_POSIX): Don't invoke.
 241         * sysdep.h: Include stdlib.h and string.h unconditionally.
 242         * i386-opc.h: Include limits.h unconditionally.
 243         * wasm32-dis.c: Likewise.
 244         * cgen-opc.c: Don't include alloca-conf.h.
 245         * config.in: Regenerate.
 246         * configure: Regenerate.
 247
 248 2021-04-01  Martin Liska  <mliska@suse.cz>
 249
 250         * arm-dis.c (strneq): Remove strneq and use startswith.
 251         * cr16-dis.c (print_insn_cr16): Likewise.
 252         * score-dis.c (streq): Likewise.
 253         (strneq): Likewise.
 254         * score7-dis.c (strneq): Likewise.
 255
 256 2021-04-01  Alan Modra  <amodra@gmail.com>
 257
 258         PR 27675
 259         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 260
 261 2021-03-31  Alan Modra  <amodra@gmail.com>
 262
 263         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 264         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 265         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 266         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 267         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 268         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 269         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 270         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 271         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 272         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 273         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 274         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 275         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 276         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 277         and TRUE with true throughout.
 278
 279 2021-03-31  Alan Modra  <amodra@gmail.com>
 280
 281         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 282         * aarch64-dis.h: Likewise.
 283         * aarch64-opc.c: Likewise.
 284         * avr-dis.c: Likewise.
 285         * csky-dis.c: Likewise.
 286         * nds32-asm.c: Likewise.
 287         * nds32-dis.c: Likewise.
 288         * nfp-dis.c: Likewise.
 289         * riscv-dis.c: Likewise.
 290         * s12z-dis.c: Likewise.
 291         * wasm32-dis.c: Likewise.
 292
 293 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 294
 295         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 296         (i386_seg_prefixes): New.
 297         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 298         (i386_seg_prefixes): Declare.
 299
 300 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 303
 304 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 305
 306         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 307         * i386-reg.tbl (st): Move down.
 308         (st(0)): Delete. Extend comment.
 309         * i386-tbl.h: Re-generate.
 310
 311 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 312
 313         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 314         (cmpsd): Move next to cmps.
 315         (movsd): Move next to movs.
 316         (cmpxchg16b): Move to separate section.
 317         (fisttp, fisttpll): Likewise.
 318         (monitor, mwait): Likewise.
 319         * i386-tbl.h: Re-generate.
 320
 321 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 324         (vpsadbw): Add C.
 325         * i386-tbl.h: Re-generate.
 326
 327 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 328
 329         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 330         pclmul, gfni): New templates. Use them wherever possible. Move
 331         SSE4.1 pextrw into respective section.
 332         * i386-tbl.h: Re-generate.
 333
 334 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 337         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 338         "length".
 339         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 340         Convert all of their uses to representation in opcode.
 341
 342 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 343
 344         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 345         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 346         value of None. Shrink operands to 3 bits.
 347
 348 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-gen.c (process_i386_opcode_modifier): New parameter
 351         "space".
 352         (output_i386_opcode): New local variable "space". Adjust
 353         process_i386_opcode_modifier() invocation.
 354         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 355         invocation.
 356         * i386-tbl.h: Re-generate.
 357
 358 2021-03-29  Alan Modra  <amodra@gmail.com>
 359
 360         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 361         (fp_qualifier_p, get_data_pattern): Likewise.
 362         (aarch64_get_operand_modifier_from_value): Likewise.
 363         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 364         (operand_variant_qualifier_p): Likewise.
 365         (qualifier_value_in_range_constraint_p): Likewise.
 366         (aarch64_get_qualifier_esize): Likewise.
 367         (aarch64_get_qualifier_nelem): Likewise.
 368         (aarch64_get_qualifier_standard_value): Likewise.
 369         (get_lower_bound, get_upper_bound): Likewise.
 370         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 371         (aarch64_print_operand): Likewise.
 372         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 373         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 374         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 375         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 376         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 377         (print_insn_tic6x): Likewise.
 378
 379 2021-03-29  Alan Modra  <amodra@gmail.com>
 380
 381         * arc-dis.c (extract_operand_value): Correct NULL cast.
 382         * frv-opc.h: Regenerate.
 383
 384 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 387         MMX form.
 388         * i386-tbl.h: Re-generate.
 389
 390 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 391
 392         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 393         immediate in br.n instruction.
 394
 395 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-dis.c (XMGatherD, VexGatherD): New.
 398         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 399         (print_insn): Check masking for S/G insns.
 400         (OP_E_memory): New local variable check_gather. Extend mandatory
 401         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 402         Extend check for disallowed 16-bit addressing.
 403         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 404         if()s to switch(). Check register conflicts for (VEX-encoded)
 405         gathers. Drop no longer reachable cases.
 406         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 407         vgatherdp*.
 408
 409 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 410
 411         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 412         zeroing-masking without masking.
 413
 414 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 417         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 418         single-operand forms as deprecated.
 419         * i386-tbl.h: Re-generate.
 420
 421 2021-03-25  Alan Modra  <amodra@gmail.com>
 422
 423         PR 27647
 424         * ppc-opc.c (XLOCB_MASK): Delete.
 425         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 426         XLBH_MASK.
 427         (powerpc_opcodes): Accept a BH field on all extended forms of
 428         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 429
 430 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-gen.c (output_i386_opcode): Drop processing of
 433         opcode_length. Calculate length from base_opcode. Adjust prefix
 434         encoding determination.
 435         (process_i386_opcodes): Drop output of fake opcode_length.
 436         * i386-opc.h (struct insn_template): Drop opcode_length field.
 437         * i386-opc.tbl: Drop opcode length field from all templates.
 438         * i386-tbl.h: Re-generate.
 439
 440 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 443         parameter "prefix". Drop local variable "regular_encoding".
 444         Record prefix setting / check for consistency.
 445         (output_i386_opcode): Parse opcode_length and base_opcode
 446         earlier. Derive prefix encoding. Drop no longer applicable
 447         consistency checking. Adjust process_i386_opcode_modifier()
 448         invocation.
 449         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 450         invocation.
 451         * i386-tbl.h: Re-generate.
 452
 453 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 456         check.
 457         * i386-opc.h (Prefix_*): Move #define-s.
 458         * i386-opc.tbl: Move pseudo prefix enumerator values to
 459         extension opcode field. Introduce pseudopfx template.
 460         * i386-tbl.h: Re-generate.
 461
 462 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 463
 464         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 465         comment.
 466         * i386-tbl.h: Re-generate.
 467
 468 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-opc.h (struct insn_template): Move cpu_flags field past
 471         opcode_modifier one.
 472         * i386-tbl.h: Re-generate.
 473
 474 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 477         * i386-opc.h (OpcodeSpace): New enumerator.
 478         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 479         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 480         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 481         (struct i386_opcode_modifier): New field opcodespace. Shrink
 482         opcodeprefix field.
 483         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 484         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 485         OpcodePrefix uses.
 486         * i386-tbl.h: Re-generate.
 487
 488 2021-03-22  Martin Liska  <mliska@suse.cz>
 489
 490         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 491         * arc-dis.c (parse_option): Likewise.
 492         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 493         * cris-dis.c (print_with_operands): Likewise.
 494         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 495         * i386-dis.c (print_insn): Likewise.
 496         * ia64-gen.c (fetch_insn_class): Likewise.
 497         (parse_resource_users): Likewise.
 498         (in_iclass): Likewise.
 499         (lookup_specifier): Likewise.
 500         (insert_opcode_dependencies): Likewise.
 501         * mips-dis.c (parse_mips_ase_option): Likewise.
 502         (parse_mips_dis_option): Likewise.
 503         * s390-dis.c (disassemble_init_s390): Likewise.
 504         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 505
 506 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 507
 508         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 509
 510 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 511
 512         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 513         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 514
 515 2021-03-12  Alan Modra  <amodra@gmail.com>
 516
 517         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 518
 519 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 520
 521         * i386-dis.c (OP_XMM): Re-order checks.
 522
 523 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 524
 525         * i386-dis.c (putop): Drop need_vex check when also checking
 526         vex.evex.
 527         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 528         checking vex.b.
 529
 530 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 533         checks. Move case label past broadcast check.
 534
 535 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 536
 537         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 538         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 539         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 540         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 541         EVEX_W_0F38C7_M_0_L_2): Delete.
 542         (REG_EVEX_0F38C7_M_0_L_2): New.
 543         (intel_operand_size): Handle VEX and EVEX the same for
 544         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 545         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 546         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 547         vex_vsib_q_w_d_mode uses.
 548         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 549         0F38A1, and 0F38A3 entries.
 550         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 551         entry.
 552         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 553         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 554         0F38A3 entries.
 555
 556 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 557
 558         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 559         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 560         MOD_VEX_0FXOP_09_12): Rename to ...
 561         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 562         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 563         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 564         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 565         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 566         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 567         (reg_table): Adjust comments.
 568         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 569         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 570         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 571         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 572         (vex_len_table): Adjust opcode 0A_12 entry.
 573         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 574         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 575         (rm_table): Move hreset entry.
 576
 577 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 578
 579         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 580         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 581         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 582         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 583         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 584         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 585         (get_valid_dis386): Also handle 512-bit vector length when
 586         vectoring into vex_len_table[].
 587         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 588         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 589         entries.
 590         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 591         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 592         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 593         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 594         entries.
 595
 596 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 597
 598         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 599         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 600         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 601         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 602         entries.
 603         * i386-dis-evex-len.h (evex_len_table): Likewise.
 604         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 605
 606 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 607
 608         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 609         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 610         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 611         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 612         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 613         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 614         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 615         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 616         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 617         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 618         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 619         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 620         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 621         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 622         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 623         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 624         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 625         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 626         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 627         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 628         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 629         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 630         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 631         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 632         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 633         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 634         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 635         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 636         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 637         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 638         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 639         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 640         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 641         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 642         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 643         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 644         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 645         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 646         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 647         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 648         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 649         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 650         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 651         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 652         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 653         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 654         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 655         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 656         EVEX_W_0F3A43_L_n): New.
 657         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 658         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 659         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 660         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 661         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 662         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 663         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 664         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 665         0F385B, 0F38C6, and 0F38C7 entries.
 666         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 667         0F38C6 and 0F38C7.
 668         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 669         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 670         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 671         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 672
 673 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 674
 675         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 676         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 677         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 678         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 679         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 680         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 681         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 682         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 683         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 684         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 685         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 686         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 687         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 688         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 689         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 690         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 691         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 692         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 693         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 694         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 695         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 696         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 697         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 698         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 699         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 700         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 701         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 702         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 703         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 704         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 705         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 706         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 707         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 708         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 709         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 710         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 711         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 712         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 713         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 714         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 715         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 716         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 717         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 718         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 719         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 720         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 721         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 722         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 723         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 724         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 725         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 726         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 727         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 728         VEX_W_0F99_P_2_LEN_0): Delete.
 729         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 730         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 731         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 732         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 733         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 734         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 735         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 736         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 737         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 738         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 739         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 740         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 741         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 742         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 743         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 744         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 745         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 746         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 747         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 748         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 749         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 750         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 751         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 752         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 753         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 754         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 755         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 756         (prefix_table): No longer link to vex_len_table[] for opcodes
 757         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 758         0F92, 0F93, 0F98, and 0F99.
 759         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 760         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 761         0F98, and 0F99.
 762         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 763         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 764         0F98, and 0F99.
 765         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 766         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 767         0F98, and 0F99.
 768         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 769         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 770         0F98, and 0F99.
 771
 772 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 773
 774         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 775         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 776         REG_VEX_0F73_M_0 respectively.
 777         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 778         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 779         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 780         MOD_VEX_0F73_REG_7): Delete.
 781         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 782         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 783         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 784         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 785         PREFIX_VEX_0F3AF0_L_0 respectively.
 786         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 787         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 788         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 789         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 790         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 791         VEX_LEN_0F38F7): New.
 792         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 793         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 794         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 795         0F38F3.
 796         (prefix_table): No longer link to vex_len_table[] for opcodes
 797         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 798         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 799         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 800         0F38F6, 0F38F7, and 0F3AF0.
 801         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 802         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 803         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 804         0F73.
 805
 806 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 807
 808         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 809         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 810         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 811         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 812         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 813         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 814         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 815         73.
 816         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 817         0F72, and 0F73.
 818         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 819         0F73.
 820
 821 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 822
 823         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 824         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 825         (reg_table): Don't link to mod_table[] where not needed. Add
 826         PREFIX_IGNORED to nop entries.
 827         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 828         (mod_table): Add nop entries next to prefetch ones. Drop
 829         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 830         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 831         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 832         PREFIX_OPCODE from endbr* entries.
 833         (get_valid_dis386): Also consider entry's name when zapping
 834         vindex.
 835         (print_insn): Handle PREFIX_IGNORED.
 836
 837 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 838
 839         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 840         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 841         element.
 842         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 843         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 844         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 845         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 846         (struct i386_opcode_modifier): Delete notrackprefixok,
 847         islockable, hleprefixok, and repprefixok fields. Add prefixok
 848         field.
 849         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 850         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 851         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 852         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 853         Replace HLEPrefixOk.
 854         * opcodes/i386-tbl.h: Re-generate.
 855
 856 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 857
 858         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 859         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 860         64-bit form.
 861         * opcodes/i386-tbl.h: Re-generate.
 862
 863 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 864
 865         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 866         for {} instead of {0}. Don't look for '0'.
 867         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 868         size specifiers.
 869
 870 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 871
 872         PR 27158
 873         * riscv-dis.c (print_insn_args): Updated encoding macros.
 874         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 875         (match_c_addi16sp): Updated encoding macros.
 876         (match_c_lui): Likewise.
 877         (match_c_lui_with_hint): Likewise.
 878         (match_c_addi4spn): Likewise.
 879         (match_c_slli): Likewise.
 880         (match_slli_as_c_slli): Likewise.
 881         (match_c_slli64): Likewise.
 882         (match_srxi_as_c_srxi): Likewise.
 883         (riscv_insn_types): Added .insn css/cl/cs.
 884
 885 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 886
 887         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 888         (default_priv_spec): Updated type to riscv_spec_class.
 889         (parse_riscv_dis_option): Updated.
 890         * riscv-opc.c: Moved stuff and make the file tidy.
 891
 892 2021-02-17  Alan Modra  <amodra@gmail.com>
 893
 894         * wasm32-dis.c: Include limits.h.
 895         (CHAR_BIT): Provide backup define.
 896         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 897         Correct signed overflow checking.
 898
 899 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 900
 901         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 902         * i386-tbl.h: Re-generate.
 903
 904 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 905
 906         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 907         Oword.
 908         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 909
 910 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 911
 912         * s390-mkopc.c (main): Accept arch14 as cpu string.
 913         * s390-opc.txt: Add new arch14 instructions.
 914
 915 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 916
 917         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 918         favour of LIBINTL.
 919         * configure: Regenerated.
 920
 921 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 922
 923         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 924         * tic54x-opc.c (regs): Rename to ...
 925         (tic54x_regs): ... this.
 926         (mmregs): Rename to ...
 927         (tic54x_mmregs): ... this.
 928         (condition_codes): Rename to ...
 929         (tic54x_condition_codes): ... this.
 930         (cc2_codes): Rename to ...
 931         (tic54x_cc2_codes): ... this.
 932         (cc3_codes): Rename to ...
 933         (tic54x_cc3_codes): ... this.
 934         (status_bits): Rename to ...
 935         (tic54x_status_bits): ... this.
 936         (misc_symbols): Rename to ...
 937         (tic54x_misc_symbols): ... this.
 938
 939 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 940
 941         * riscv-opc.c (MASK_RVB_IMM): Removed.
 942         (riscv_opcodes): Removed zb* instructions.
 943         (riscv_ext_version_table): Removed versions for zb*.
 944
 945 2021-01-26  Alan Modra  <amodra@gmail.com>
 946
 947         * i386-gen.c (parse_template): Ensure entire template_instance
 948         is initialised.
 949
 950 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 951
 952         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 953         (riscv_fpr_names_abi): Likewise.
 954         (riscv_opcodes): Likewise.
 955         (riscv_insn_types): Likewise.
 956
 957 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 958
 959         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 960
 961 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 962
 963         * riscv-dis.c: Comments tidy and improvement.
 964         * riscv-opc.c: Likewise.
 965
 966 2021-01-13  Alan Modra  <amodra@gmail.com>
 967
 968         * Makefile.in: Regenerate.
 969
 970 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 971
 972         PR binutils/26792
 973         * configure.ac: Use GNU_MAKE_JOBSERVER.
 974         * aclocal.m4: Regenerated.
 975         * configure: Likewise.
 976
 977 2021-01-12  Nick Clifton  <nickc@redhat.com>
 978
 979         * po/sr.po: Updated Serbian translation.
 980
 981 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 982
 983         PR ld/27173
 984         * configure: Regenerated.
 985
 986 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 987
 988         * aarch64-asm-2.c: Regenerate.
 989         * aarch64-dis-2.c: Likewise.
 990         * aarch64-opc-2.c: Likewise.
 991         * aarch64-opc.c (aarch64_print_operand):
 992         Delete handling of AARCH64_OPND_CSRE_CSR.
 993         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 994         (CSRE): Likewise.
 995         (_CSRE_INSN): Likewise.
 996         (aarch64_opcode_table): Delete csr.
 997
 998 2021-01-11  Nick Clifton  <nickc@redhat.com>
 999
1000         * po/de.po: Updated German translation.
1001         * po/fr.po: Updated French translation.
1002         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1003         * po/sv.po: Updated Swedish translation.
1004         * po/uk.po: Updated Ukranian translation.
1005
1006 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1007
1008         * configure: Regenerated.
1009
1010 2021-01-09  Nick Clifton  <nickc@redhat.com>
1011
1012         * configure: Regenerate.
1013         * po/opcodes.pot: Regenerate.
1014
1015 2021-01-09  Nick Clifton  <nickc@redhat.com>
1016
1017         * 2.36 release branch crated.
1018
1019 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1020
1021         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1022         (DW, (XRC_MASK): Define.
1023         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1024
1025 2021-01-09  Alan Modra  <amodra@gmail.com>
1026
1027         * configure: Regenerate.
1028
1029 2021-01-08  Nick Clifton  <nickc@redhat.com>
1030
1031         * po/sv.po: Updated Swedish translation.
1032
1033 2021-01-08  Nick Clifton  <nickc@redhat.com>
1034
1035         PR 27129
1036         * aarch64-dis.c (determine_disassembling_preference): Move call to
1037         aarch64_match_operands_constraint outside of the assertion.
1038         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1039         Replace with a return of FALSE.
1040
1041         PR 27139
1042         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1043         core system register.
1044
1045 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1046
1047         * configure: Regenerate.
1048
1049 2021-01-07  Nick Clifton  <nickc@redhat.com>
1050
1051         * po/fr.po: Updated French translation.
1052
1053 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1054
1055         * m68k-opc.c (chkl): Change minimum architecture requirement to
1056         m68020.
1057
1058 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1059
1060         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1061
1062 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1063             Jim Wilson  <jimw@sifive.com>
1064             Andrew Waterman  <andrew@sifive.com>
1065             Maxim Blinov  <maxim.blinov@embecosm.com>
1066             Kito Cheng  <kito.cheng@sifive.com>
1067             Nelson Chu  <nelson.chu@sifive.com>
1068
1069         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1070         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1071
1072 2021-01-01  Alan Modra  <amodra@gmail.com>
1073
1074         Update year range in copyright notice of all files.
1075
1076 For older changes see ChangeLog-2020
1077 \f
1078 Copyright (C) 2021 Free Software Foundation, Inc.
1079
1080 Copying and distribution of this file, with or without modification,
1081 are permitted in any medium without royalty provided the copyright
1082 notice and this notice are preserved.
1083
1084 Local Variables:
1085 mode: change-log
1086 left-margin: 8
1087 fill-column: 74
1088 version-control: never
1089 End: