opcodes/ChangeLog

   1 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
   2
   3         * s390-mkopc.c (main): Remove vx2 check.
   4         * s390-opc.txt: Remove vx2 instruction flags.
   5
   6 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
   7
   8         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
   9         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
  10         (insert_nps_imm_offset): New function.
  11         (extract_nps_imm_offset): New function.
  12         (insert_nps_imm_entry): New function.
  13         (extract_nps_imm_entry): New function.
  14
  15 2017-03-17  Alan Modra  <amodra@gmail.com>
  16
  17         PR 21248
  18         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
  19         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
  20         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
  21
  22 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
  23
  24         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
  25         <c.andi>: Likewise.
  26         <c.addiw> Likewise.
  27
  28 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
  29
  30         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
  31
  32 2017-03-13  Andrew Waterman  <andrew@sifive.com>
  33
  34         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
  35         <srl> Likewise.
  36         <srai> Likewise.
  37         <sra> Likewise.
  38
  39 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  40
  41         * i386-gen.c (opcode_modifiers): Replace S with Load.
  42         * i386-opc.h (S): Removed.
  43         (Load): New.
  44         (i386_opcode_modifier): Replace s with load.
  45         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
  46         and {evex}.  Replace S with Load.
  47         * i386-tbl.h: Regenerated.
  48
  49 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         * i386-opc.tbl: Use CpuCET on rdsspq.
  52         * i386-tbl.h: Regenerated.
  53
  54 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  55
  56         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
  57         <vsx>: Do not use PPC_OPCODE_VSX3;
  58
  59 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  60
  61         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
  62
  63 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
  64
  65         * i386-dis.c (REG_0F1E_MOD_3): New enum.
  66         (MOD_0F1E_PREFIX_1): Likewise.
  67         (MOD_0F38F5_PREFIX_2): Likewise.
  68         (MOD_0F38F6_PREFIX_0): Likewise.
  69         (RM_0F1E_MOD_3_REG_7): Likewise.
  70         (PREFIX_MOD_0_0F01_REG_5): Likewise.
  71         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  72         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
  73         (PREFIX_0F1E): Likewise.
  74         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
  75         (PREFIX_0F38F5): Likewise.
  76         (dis386_twobyte): Use PREFIX_0F1E.
  77         (reg_table): Add REG_0F1E_MOD_3.
  78         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
  79         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
  80         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
  81         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
  82         (three_byte_table): Use PREFIX_0F38F5.
  83         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
  84         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
  85         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
  86         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
  87         PREFIX_MOD_3_0F01_REG_5_RM_2.
  88         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
  89         (cpu_flags): Add CpuCET.
  90         * i386-opc.h (CpuCET): New enum.
  91         (CpuUnused): Commented out.
  92         (i386_cpu_flags): Add cpucet.
  93         * i386-opc.tbl: Add Intel CET instructions.
  94         * i386-init.h: Regenerated.
  95         * i386-tbl.h: Likewise.
  96
  97 2017-03-06  Alan Modra  <amodra@gmail.com>
  98
  99         PR 21124
 100         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 101         (extract_raq, extract_ras, extract_rbx): New functions.
 102         (powerpc_operands): Use opposite corresponding insert function.
 103         (Q_MASK): Define.
 104         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 105         register restriction.
 106
 107 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 108
 109         * disassemble.c Include "safe-ctype.h".
 110         (disassemble_init_for_target): Handle s390 init.
 111         (remove_whitespace_and_extra_commas): New function.
 112         (disassembler_options_cmp): Likewise.
 113         * arm-dis.c: Include "libiberty.h".
 114         (NUM_ELEM): Delete.
 115         (regnames): Use long disassembler style names.
 116         Add force-thumb and no-force-thumb options.
 117         (NUM_ARM_REGNAMES): Rename from this...
 118         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 119         (get_arm_regname_num_options): Delete.
 120         (set_arm_regname_option): Likewise.
 121         (get_arm_regnames): Likewise.
 122         (parse_disassembler_options): Likewise.
 123         (parse_arm_disassembler_option): Rename from this...
 124         (parse_arm_disassembler_options): ...to this.  Make static.
 125         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 126         (print_insn): Use parse_arm_disassembler_options.
 127         (disassembler_options_arm): New function.
 128         (print_arm_disassembler_options): Handle updated regnames.
 129         * ppc-dis.c: Include "libiberty.h".
 130         (ppc_opts): Add "32" and "64" entries.
 131         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 132         (powerpc_init_dialect): Add break to switch statement.
 133         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 134         (disassembler_options_powerpc): New function.
 135         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 136         Remove printing of "32" and "64".
 137         * s390-dis.c: Include "libiberty.h".
 138         (init_flag): Remove unneeded variable.
 139         (struct s390_options_t): New structure type.
 140         (options): New structure.
 141         (init_disasm): Rename from this...
 142         (disassemble_init_s390): ...to this.  Add initializations for
 143         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 144         (print_insn_s390): Delete call to init_disasm.
 145         (disassembler_options_s390): New function.
 146         (print_s390_disassembler_options): Print using information from
 147         struct 'options'.
 148         * po/opcodes.pot: Regenerate.
 149
 150 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-dis.c (PCMPESTR_Fixup): New.
 153         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 154         (prefix_table): Use PCMPESTR_Fixup.
 155         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 156         PCMPESTR_Fixup.
 157         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 158         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 159         Split 64-bit and non-64-bit variants.
 160         * opcodes/i386-tbl.h: Re-generate.
 161
 162 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 163
 164         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 165         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 166         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 167         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 168         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 169         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 170         (OP_SVE_V_HSD): New macros.
 171         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 172         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 173         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 174         (aarch64_opcode_table): Add new SVE instructions.
 175         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 176         for rotation operands.  Add new SVE operands.
 177         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 178         (ins_sve_quad_index): Likewise.
 179         (ins_imm_rotate): Split into...
 180         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 181         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 182         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 183         functions.
 184         (aarch64_ins_sve_addr_ri_s4): New function.
 185         (aarch64_ins_sve_quad_index): Likewise.
 186         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 187         * aarch64-asm-2.c: Regenerate.
 188         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 189         (ext_sve_quad_index): Likewise.
 190         (ext_imm_rotate): Split into...
 191         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 192         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 193         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 194         functions.
 195         (aarch64_ext_sve_addr_ri_s4): New function.
 196         (aarch64_ext_sve_quad_index): Likewise.
 197         (aarch64_ext_sve_index): Allow quad indices.
 198         (do_misc_decoding): Likewise.
 199         * aarch64-dis-2.c: Regenerate.
 200         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 201         aarch64_field_kinds.
 202         (OPD_F_OD_MASK): Widen by one bit.
 203         (OPD_F_NO_ZR): Bump accordingly.
 204         (get_operand_field_width): New function.
 205         * aarch64-opc.c (fields): Add new SVE fields.
 206         (operand_general_constraint_met_p): Handle new SVE operands.
 207         (aarch64_print_operand): Likewise.
 208         * aarch64-opc-2.c: Regenerate.
 209
 210 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 211
 212         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 213         (aarch64_feature_compnum): ...this.
 214         (SIMD_V8_3): Replace with...
 215         (COMPNUM): ...this.
 216         (CNUM_INSN): New macro.
 217         (aarch64_opcode_table): Use it for the complex number instructions.
 218
 219 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 222
 223 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 224
 225         Add support for associating SPARC ASIs with an architecture level.
 226         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 227         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 228         decoding of SPARC ASIs.
 229
 230 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 231
 232         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 233         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 234
 235 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 236
 237         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 238         1 (instead of to itself). Correct typo.
 239
 240 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 241
 242         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 243         pseudoinstructions.
 244
 245 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 246
 247         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 248         (aarch64_sys_reg_supported_p): Handle them.
 249
 250 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 251
 252         * arc-opc.c (UIMM6_20R): Define.
 253         (SIMM12_20): Use above.
 254         (SIMM12_20R): Define.
 255         (SIMM3_5_S): Use above.
 256         (UIMM7_A32_11R_S): Define.
 257         (UIMM7_9_S): Use above.
 258         (UIMM3_13R_S): Define.
 259         (SIMM11_A32_7_S): Use above.
 260         (SIMM9_8R): Define.
 261         (UIMM10_A32_8_S): Use above.
 262         (UIMM8_8R_S): Define.
 263         (W6): Use above.
 264         (arc_relax_opcodes): Use all above defines.
 265
 266 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 267
 268         * arc-regs.h: Distinguish some of the registers different on
 269         ARC700 and HS38 cpus.
 270
 271 2017-02-14  Alan Modra  <amodra@gmail.com>
 272
 273         PR 21118
 274         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 275         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 276
 277 2017-02-11  Stafford Horne  <shorne@gmail.com>
 278             Alan Modra  <amodra@gmail.com>
 279
 280         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 281         Use insn_bytes_value and insn_int_value directly instead.  Don't
 282         free allocated memory until function exit.
 283
 284 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 285
 286         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 287
 288 2017-02-03  Nick Clifton  <nickc@redhat.com>
 289
 290         PR 21096
 291         * aarch64-opc.c (print_register_list): Ensure that the register
 292         list index will fir into the tb buffer.
 293         (print_register_offset_address): Likewise.
 294         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 295
 296 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 297
 298         PR 21056
 299         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 300         instructions when the previous fetch packet ends with a 32-bit
 301         instruction.
 302
 303 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 304
 305         * pru-opc.c: Remove vague reference to a future GDB port.
 306
 307 2017-01-20  Nick Clifton  <nickc@redhat.com>
 308
 309         * po/ga.po: Updated Irish translation.
 310
 311 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 312
 313         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 314
 315 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 316
 317         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 318         if FETCH_DATA returns 0.
 319         (m68k_scan_mask): Likewise.
 320         (print_insn_m68k): Update code to handle -1 return value.
 321
 322 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 323
 324         * m68k-dis.c (enum print_insn_arg_error): New.
 325         (NEXTBYTE): Replace -3 with
 326         PRINT_INSN_ARG_MEMORY_ERROR.
 327         (NEXTULONG): Likewise.
 328         (NEXTSINGLE): Likewise.
 329         (NEXTDOUBLE): Likewise.
 330         (NEXTDOUBLE): Likewise.
 331         (NEXTPACKED): Likewise.
 332         (FETCH_ARG): Likewise.
 333         (FETCH_DATA): Update comments.
 334         (print_insn_arg): Update comments. Replace magic numbers with
 335         enum.
 336         (match_insn_m68k): Likewise.
 337
 338 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 339
 340         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 341         * i386-dis-evex.h (evex_table): Updated.
 342         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 343         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 344         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 345         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 346         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 347         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 348         * i386-init.h: Regenerate.
 349         * i386-tbl.h: Ditto.
 350
 351 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 352
 353         * msp430-dis.c (msp430_singleoperand): Return -1 if
 354         msp430dis_opcode_signed returns false.
 355         (msp430_doubleoperand): Likewise.
 356         (msp430_branchinstr): Return -1 if
 357         msp430dis_opcode_unsigned returns false.
 358         (msp430x_calla_instr): Likewise.
 359         (print_insn_msp430): Likewise.
 360
 361 2017-01-05  Nick Clifton  <nickc@redhat.com>
 362
 363         PR 20946
 364         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 365         could not be matched.
 366         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 367         NULL.
 368
 369 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 370
 371         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 372         (aarch64_opcode_table): Use RCPC_INSN.
 373
 374 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 375
 376         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 377         extension.
 378         * riscv-opcodes/all-opcodes: Likewise.
 379
 380 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 381
 382         * riscv-dis.c (print_insn_args): Add fall through comment.
 383
 384 2017-01-03  Nick Clifton  <nickc@redhat.com>
 385
 386         * po/sr.po: New Serbian translation.
 387         * configure.ac (ALL_LINGUAS): Add sr.
 388         * configure: Regenerate.
 389
 390 2017-01-02  Alan Modra  <amodra@gmail.com>
 391
 392         * epiphany-desc.h: Regenerate.
 393         * epiphany-opc.h: Regenerate.
 394         * fr30-desc.h: Regenerate.
 395         * fr30-opc.h: Regenerate.
 396         * frv-desc.h: Regenerate.
 397         * frv-opc.h: Regenerate.
 398         * ip2k-desc.h: Regenerate.
 399         * ip2k-opc.h: Regenerate.
 400         * iq2000-desc.h: Regenerate.
 401         * iq2000-opc.h: Regenerate.
 402         * lm32-desc.h: Regenerate.
 403         * lm32-opc.h: Regenerate.
 404         * m32c-desc.h: Regenerate.
 405         * m32c-opc.h: Regenerate.
 406         * m32r-desc.h: Regenerate.
 407         * m32r-opc.h: Regenerate.
 408         * mep-desc.h: Regenerate.
 409         * mep-opc.h: Regenerate.
 410         * mt-desc.h: Regenerate.
 411         * mt-opc.h: Regenerate.
 412         * or1k-desc.h: Regenerate.
 413         * or1k-opc.h: Regenerate.
 414         * xc16x-desc.h: Regenerate.
 415         * xc16x-opc.h: Regenerate.
 416         * xstormy16-desc.h: Regenerate.
 417         * xstormy16-opc.h: Regenerate.
 418
 419 2017-01-02  Alan Modra  <amodra@gmail.com>
 420
 421         Update year range in copyright notice of all files.
 422
 423 For older changes see ChangeLog-2016
 424 \f
 425 Copyright (C) 2017 Free Software Foundation, Inc.
 426
 427 Copying and distribution of this file, with or without modification,
 428 are permitted in any medium without royalty provided the copyright
 429 notice and this notice are preserved.
 430
 431 Local Variables:
 432 mode: change-log
 433 left-margin: 8
 434 fill-column: 74
 435 version-control: never
 436 End: