1 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
4 with aarch64_sys_ins_reg_has_xt.
5 (aarch64_ext_sysins_op): Likewise.
6 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
8 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
9 (aarch64_sys_regs_dc): Likewise.
10 (aarch64_sys_regs_at): Likewise.
11 (aarch64_sys_regs_tlbi): Likewise.
12 (aarch64_sys_ins_reg_has_xt): New.
14 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
16 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
17 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
18 (aarch64_pstatefields): Add "uao".
19 (aarch64_pstatefield_supported_p): Add checks for "uao".
21 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
23 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
24 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
25 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
26 (aarch64_sys_reg_supported_p): Add architecture feature tests for
29 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
31 * aarch64-asm-2.c: Regenerate.
32 * aarch64-dis-2.c: Regenerate.
33 * aarch64-tbl.h (aarch64_feature_ras): New.
35 (aarch64_opcode_table): Add "esb".
37 2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
39 * i386-dis.c (MOD_0F01_REG_5): New.
40 (RM_0F01_REG_5): Likewise.
41 (reg_table): Use MOD_0F01_REG_5.
42 (mod_table): Add MOD_0F01_REG_5.
43 (rm_table): Add RM_0F01_REG_5.
44 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
45 (cpu_flags): Add CpuOSPKE.
46 * i386-opc.h (CpuOSPKE): New.
47 (i386_cpu_flags): Add cpuospke.
48 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
49 * i386-init.h: Regenerated.
50 * i386-tbl.h: Likewise.
52 2015-12-07 DJ Delorie <dj@redhat.com>
54 * rl78-decode.opc: Enable MULU for all ISAs.
55 * rl78-decode.c: Regenerate.
57 2015-12-07 Alan Modra <amodra@gmail.com>
59 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
62 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
64 * arc-dis.c (special_flag_p): Match full mnemonic.
65 * arc-opc.c (print_insn_arc): Check section size to read
66 appropriate number of bytes. Fix printing.
67 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
70 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
72 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
75 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
77 * aarch64-asm-2.c: Regenerate.
78 * aarch64-dis-2.c: Regenerate.
79 * aarch64-opc-2.c: Regenerate.
80 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
81 (QL_INT2FP_H, QL_FP2INT_H): New.
82 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
85 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
86 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
87 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
88 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
89 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
90 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
93 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
95 * aarch64-opc.c (half_conv_t): New.
96 (expand_fp_imm): Replace is_dp flag with the parameter size to
97 specify the number of bytes for the required expansion. Treat
98 a 16-bit expansion like a 32-bit expansion. Add check for an
99 unsupported size request. Update comment.
100 (aarch64_print_operand): Update to support 16-bit floating point
101 values. Update for changes to expand_fp_imm.
103 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
105 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
108 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
110 * aarch64-asm-2.c: Regenerate.
111 * aarch64-dis-2.c: Regenerate.
112 * aarch64-opc-2.c: Regenerate.
113 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
116 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
118 * aarch64-asm-2.c: Regenerate.
119 * aarch64-asm.c (convert_bfc_to_bfm): New.
120 (convert_to_real): Add case for OP_BFC.
121 * aarch64-dis-2.c: Regenerate.
122 * aarch64-dis.c: (convert_bfm_to_bfc): New.
123 (convert_to_alias): Add case for OP_BFC.
124 * aarch64-opc-2.c: Regenerate.
125 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
126 to allow width operand in three-operand instructions.
127 * aarch64-tbl.h (QL_BF1): New.
128 (aarch64_feature_v8_2): New.
130 (aarch64_opcode_table): Add "bfc".
132 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
134 * aarch64-asm-2.c: Regenerate.
135 * aarch64-dis-2.c: Regenerate.
136 * aarch64-dis.c: Weaken assert.
137 * aarch64-gen.c: Include the instruction in the list of its
140 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
142 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
143 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
146 2015-11-23 Tristan Gingold <gingold@adacore.com>
148 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
150 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
152 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
153 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
154 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
155 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
156 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
157 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
158 cnthv_ctl_el2, cnthv_cval_el2.
159 (aarch64_sys_reg_supported_p): Update for the new system
162 2015-11-20 Nick Clifton <nickc@redhat.com>
165 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
167 2015-11-20 Nick Clifton <nickc@redhat.com>
169 * po/zh_CN.po: Updated simplified Chinese translation.
171 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
173 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
174 of MSR PAN immediate operand.
176 2015-11-16 Nick Clifton <nickc@redhat.com>
178 * rx-dis.c (condition_names): Replace always and never with
179 invalid, since the always/never conditions can never be legal.
181 2015-11-13 Tristan Gingold <gingold@adacore.com>
183 * configure: Regenerate.
185 2015-11-11 Alan Modra <amodra@gmail.com>
186 Peter Bergner <bergner@vnet.ibm.com>
188 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
189 Add PPC_OPCODE_VSX3 to the vsx entry.
190 (powerpc_init_dialect): Set default dialect to power9.
191 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
192 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
193 extract_l1 insert_xtq6, extract_xtq6): New static functions.
194 (insert_esync): Test for illegal L operand value.
195 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
196 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
197 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
198 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
199 PPCVSX3): New defines.
200 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
201 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
202 <mcrxr>: Use XBFRARB_MASK.
203 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
204 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
205 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
206 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
207 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
208 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
209 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
210 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
211 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
212 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
213 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
214 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
215 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
216 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
217 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
218 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
219 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
220 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
221 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
222 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
223 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
224 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
225 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
226 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
227 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
228 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
229 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
230 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
231 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
232 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
233 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
234 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
236 2015-11-02 Nick Clifton <nickc@redhat.com>
238 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
240 * rx-decode.c: Regenerate.
242 2015-11-02 Nick Clifton <nickc@redhat.com>
244 * rx-decode.opc (rx_disp): If the displacement is zero, set the
245 type to RX_Operand_Zero_Indirect.
246 * rx-decode.c: Regenerate.
247 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
249 2015-10-28 Yao Qi <yao.qi@linaro.org>
251 * aarch64-dis.c (aarch64_decode_insn): Add one argument
252 noaliases_p. Update comments. Pass noaliases_p rather than
253 no_aliases to aarch64_opcode_decode.
254 (print_insn_aarch64_word): Pass no_aliases to
257 2015-10-27 Vinay <Vinay.G@kpit.com>
260 * rl78-decode.opc (MOV): Added offset to DE register in index
262 * rl78-decode.c: Regenerate.
264 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
267 * rl78-decode.opc: Add 's' print operator to instructions that
268 access system registers.
269 * rl78-decode.c: Regenerate.
270 * rl78-dis.c (print_insn_rl78_common): Decode all system
273 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
276 * rl78-decode.opc: Add 'a' print operator to mov instructions
277 using stack pointer plus index addressing.
278 * rl78-decode.c: Regenerate.
280 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
282 * s390-opc.c: Fix comment.
283 * s390-opc.txt: Change instruction type for troo, trot, trto, and
284 trtt to RRF_U0RER since the second parameter does not need to be a
287 2015-10-08 Nick Clifton <nickc@redhat.com>
289 * arc-dis.c (print_insn_arc): Initiallise insn array.
291 2015-10-07 Yao Qi <yao.qi@linaro.org>
293 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
294 'name' rather than 'template'.
295 * aarch64-opc.c (aarch64_print_operand): Likewise.
297 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
299 * arc-dis.c: Revamped file for ARC support
300 * arc-dis.h: Likewise.
301 * arc-ext.c: Likewise.
302 * arc-ext.h: Likewise.
303 * arc-opc.c: Likewise.
304 * arc-fxi.h: New file.
305 * arc-regs.h: Likewise.
306 * arc-tbl.h: Likewise.
308 2015-10-02 Yao Qi <yao.qi@linaro.org>
310 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
311 argument insn type to aarch64_insn. Rename to ...
312 (aarch64_decode_insn): ... it.
313 (print_insn_aarch64_word): Caller updated.
315 2015-10-02 Yao Qi <yao.qi@linaro.org>
317 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
318 (print_insn_aarch64_word): Caller updated.
320 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
322 * s390-mkopc.c (main): Parse htm and vx flag.
323 * s390-opc.txt: Mark instructions from the hardware transactional
324 memory and vector facilities with the "htm"/"vx" flag.
326 2015-09-28 Nick Clifton <nickc@redhat.com>
328 * po/de.po: Updated German translation.
330 2015-09-28 Tom Rix <tom@bumblecow.com>
332 * ppc-opc.c (PPC500): Mark some opcodes as invalid
334 2015-09-23 Nick Clifton <nickc@redhat.com>
336 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
338 * tic30-dis.c (print_branch): Likewise.
339 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
340 value before left shifting.
341 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
342 * hppa-dis.c (print_insn_hppa): Likewise.
343 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
345 * msp430-dis.c (msp430_singleoperand): Likewise.
346 (msp430_doubleoperand): Likewise.
347 (print_insn_msp430): Likewise.
348 * nds32-asm.c (parse_operand): Likewise.
349 * sh-opc.h (MASK): Likewise.
350 * v850-dis.c (get_operand_value): Likewise.
352 2015-09-22 Nick Clifton <nickc@redhat.com>
354 * rx-decode.opc (bwl): Use RX_Bad_Size.
356 (ubwl): Likewise. Rename to ubw.
357 (uBWL): Rename to uBW.
358 Replace all references to uBWL with uBW.
359 * rx-decode.c: Regenerate.
360 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
361 (opsize_names): Likewise.
362 (print_insn_rx): Detect and report RX_Bad_Size.
364 2015-09-22 Anton Blanchard <anton@samba.org>
366 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
368 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
370 * sparc-dis.c (print_insn_sparc): Handle the privileged register
373 2015-08-24 Jan Stancek <jstancek@redhat.com>
375 * i386-dis.c (print_insn): Fix decoding of three byte operands.
377 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
380 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
381 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
382 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
383 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
384 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
385 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
386 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
387 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
388 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
389 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
390 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
391 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
392 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
393 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
394 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
395 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
396 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
397 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
398 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
399 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
400 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
401 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
402 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
403 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
404 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
405 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
406 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
407 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
408 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
409 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
410 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
411 (vex_w_table): Replace terminals with MOD_TABLE entries for
412 most of mask instructions.
414 2015-08-17 Alan Modra <amodra@gmail.com>
416 * cgen.sh: Trim trailing space from cgen output.
417 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
418 (print_dis_table): Likewise.
419 * opc2c.c (dump_lines): Likewise.
420 (orig_filename): Warning fix.
421 * ia64-asmtab.c: Regenerate.
423 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
425 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
426 and higher with ARM instruction set will now mark the 26-bit
427 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
428 (arm_opcodes): Fix for unpredictable nop being recognized as a
431 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
433 * micromips-opc.c (micromips_opcodes): Re-order table so that move
434 based on 'or' is first.
435 * mips-opc.c (mips_builtin_opcodes): Ditto.
437 2015-08-11 Nick Clifton <nickc@redhat.com>
440 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
443 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
445 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
447 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
449 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
450 * i386-init.h: Regenerated.
452 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
455 * i386-dis.c (MOD_0FC3): New.
456 (PREFIX_0FC3): Renamed to ...
457 (PREFIX_MOD_0_0FC3): This.
458 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
459 (prefix_table): Replace Ma with Ev on movntiS.
460 (mod_table): Add MOD_0FC3.
462 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
464 * configure: Regenerated.
466 2015-07-23 Alan Modra <amodra@gmail.com>
469 * i386-dis.c (get64): Avoid signed integer overflow.
471 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
474 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
475 "EXEvexHalfBcstXmmq" for the second operand.
476 (EVEX_W_0F79_P_2): Likewise.
477 (EVEX_W_0F7A_P_2): Likewise.
478 (EVEX_W_0F7B_P_2): Likewise.
480 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
482 * arm-dis.c (print_insn_coprocessor): Added support for quarter
483 float bitfield format.
484 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
485 quarter float bitfield format.
487 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
489 * configure: Regenerated.
491 2015-07-03 Alan Modra <amodra@gmail.com>
493 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
494 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
495 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
497 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
498 Cesar Philippidis <cesar@codesourcery.com>
500 * nios2-dis.c (nios2_extract_opcode): New.
501 (nios2_disassembler_state): New.
502 (nios2_find_opcode_hash): Use mach parameter to select correct
504 (nios2_print_insn_arg): Extend to support new R2 argument letters
506 (print_insn_nios2): Check for 16-bit instruction at end of memory.
507 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
508 (NIOS2_NUM_OPCODES): Rename to...
509 (NIOS2_NUM_R1_OPCODES): This.
510 (nios2_r2_opcodes): New.
511 (NIOS2_NUM_R2_OPCODES): New.
512 (nios2_num_r2_opcodes): New.
513 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
514 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
515 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
516 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
517 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
519 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
521 * i386-dis.c (OP_Mwaitx): New.
522 (rm_table): Add monitorx/mwaitx.
523 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
524 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
525 (operand_type_init): Add CpuMWAITX.
526 * i386-opc.h (CpuMWAITX): New.
527 (i386_cpu_flags): Add cpumwaitx.
528 * i386-opc.tbl: Add monitorx and mwaitx.
529 * i386-init.h: Regenerated.
530 * i386-tbl.h: Likewise.
532 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
534 * ppc-opc.c (insert_ls): Test for invalid LS operands.
535 (insert_esync): New function.
536 (LS, WC): Use insert_ls.
537 (ESYNC): Use insert_esync.
539 2015-06-22 Nick Clifton <nickc@redhat.com>
541 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
542 requested region lies beyond it.
543 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
544 looking for 32-bit insns.
545 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
547 * sh-dis.c (print_insn_sh): Likewise.
548 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
549 blocks of instructions.
550 * vax-dis.c (print_insn_vax): Check that the requested address
551 does not clash with the stop_vma.
553 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
555 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
556 * ppc-opc.c (FXM4): Add non-zero optional value.
559 (insert_fxm): Handle new default operand value.
560 (extract_fxm): Likewise.
561 (insert_tbr): Likewise.
562 (extract_tbr): Likewise.
564 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
566 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
568 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
570 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
572 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
574 * ppc-opc.c: Add comment accidentally removed by old commit.
577 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
579 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
581 2015-06-04 Nick Clifton <nickc@redhat.com>
584 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
586 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
588 * arm-dis.c (arm_opcodes): Add "setpan".
589 (thumb_opcodes): Add "setpan".
591 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
593 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
596 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
598 * aarch64-tbl.h (aarch64_feature_rdma): New.
600 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
601 * aarch64-asm-2.c: Regenerate.
602 * aarch64-dis-2.c: Regenerate.
603 * aarch64-opc-2.c: Regenerate.
605 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
607 * aarch64-tbl.h (aarch64_feature_lor): New.
609 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
611 * aarch64-asm-2.c: Regenerate.
612 * aarch64-dis-2.c: Regenerate.
613 * aarch64-opc-2.c: Regenerate.
615 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
617 * aarch64-opc.c (F_ARCHEXT): New.
618 (aarch64_sys_regs): Add "pan".
619 (aarch64_sys_reg_supported_p): New.
620 (aarch64_pstatefields): Add "pan".
621 (aarch64_pstatefield_supported_p): New.
623 2015-06-01 Jan Beulich <jbeulich@suse.com>
625 * i386-tbl.h: Regenerate.
627 2015-06-01 Jan Beulich <jbeulich@suse.com>
629 * i386-dis.c (print_insn): Swap rounding mode specifier and
630 general purpose register in Intel mode.
632 2015-06-01 Jan Beulich <jbeulich@suse.com>
634 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
635 * i386-tbl.h: Regenerate.
637 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
639 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
640 * i386-init.h: Regenerated.
642 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
645 * i386-dis.c: Add comments for '@'.
646 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
647 (enum x86_64_isa): New.
649 (print_i386_disassembler_options): Add amd64 and intel64.
650 (print_insn): Handle amd64 and intel64.
652 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
653 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
654 * i386-opc.h (AMD64): New.
655 (CpuIntel64): Likewise.
656 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
657 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
658 Mark direct call/jmp without Disp16|Disp32 as Intel64.
659 * i386-init.h: Regenerated.
660 * i386-tbl.h: Likewise.
662 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
664 * ppc-opc.c (IH) New define.
665 (powerpc_opcodes) <wait>: Do not enable for POWER7.
666 <tlbie>: Add RS operand for POWER7.
667 <slbia>: Add IH operand for POWER6.
669 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
671 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
674 * i386-tbl.h: Regenerated.
676 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
678 * configure.ac: Support bfd_iamcu_arch.
679 * disassemble.c (disassembler): Support bfd_iamcu_arch.
680 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
681 CPU_IAMCU_COMPAT_FLAGS.
682 (cpu_flags): Add CpuIAMCU.
683 * i386-opc.h (CpuIAMCU): New.
684 (i386_cpu_flags): Add cpuiamcu.
685 * configure: Regenerated.
686 * i386-init.h: Likewise.
687 * i386-tbl.h: Likewise.
689 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
692 * i386-dis.c (X86_64_E8): New.
693 (X86_64_E9): Likewise.
694 Update comments on 'T', 'U', 'V'. Add comments for '^'.
695 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
696 (x86_64_table): Add X86_64_E8 and X86_64_E9.
697 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
699 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
702 2015-04-30 DJ Delorie <dj@redhat.com>
704 * disassemble.c (disassembler): Choose suitable disassembler based
706 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
707 it to decode mul/div insns.
708 * rl78-decode.c: Regenerate.
709 * rl78-dis.c (print_insn_rl78): Rename to...
710 (print_insn_rl78_common): ...this, take ISA parameter.
711 (print_insn_rl78): New.
712 (print_insn_rl78_g10): New.
713 (print_insn_rl78_g13): New.
714 (print_insn_rl78_g14): New.
715 (rl78_get_disassembler): New.
717 2015-04-29 Nick Clifton <nickc@redhat.com>
719 * po/fr.po: Updated French translation.
721 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
723 * ppc-opc.c (DCBT_EO): New define.
724 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
728 <waitrsv>: Do not enable for POWER7 and later.
729 <waitimpl>: Likewise.
730 <dcbt>: Default to the two operand form of the instruction for all
731 "old" cpus. For "new" cpus, use the operand ordering that matches
732 whether the cpu is server or embedded.
735 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
737 * s390-opc.c: New instruction type VV0UU2.
738 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
741 2015-04-23 Jan Beulich <jbeulich@suse.com>
743 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
744 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
745 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
746 (vfpclasspd, vfpclassps): Add %XZ.
748 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
750 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
751 (PREFIX_UD_REPZ): Likewise.
752 (PREFIX_UD_REPNZ): Likewise.
753 (PREFIX_UD_DATA): Likewise.
754 (PREFIX_UD_ADDR): Likewise.
755 (PREFIX_UD_LOCK): Likewise.
757 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
759 * i386-dis.c (prefix_requirement): Removed.
760 (print_insn): Don't set prefix_requirement. Check
761 dp->prefix_requirement instead of prefix_requirement.
763 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
766 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
767 (PREFIX_MOD_0_0FC7_REG_6): This.
768 (PREFIX_MOD_3_0FC7_REG_6): New.
769 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
770 (prefix_table): Replace PREFIX_0FC7_REG_6 with
771 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
772 PREFIX_MOD_3_0FC7_REG_7.
773 (mod_table): Replace PREFIX_0FC7_REG_6 with
774 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
775 PREFIX_MOD_3_0FC7_REG_7.
777 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
779 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
780 (PREFIX_MANDATORY_REPNZ): Likewise.
781 (PREFIX_MANDATORY_DATA): Likewise.
782 (PREFIX_MANDATORY_ADDR): Likewise.
783 (PREFIX_MANDATORY_LOCK): Likewise.
784 (PREFIX_MANDATORY): Likewise.
785 (PREFIX_UD_SHIFT): Set to 8
786 (PREFIX_UD_REPZ): Updated.
787 (PREFIX_UD_REPNZ): Likewise.
788 (PREFIX_UD_DATA): Likewise.
789 (PREFIX_UD_ADDR): Likewise.
790 (PREFIX_UD_LOCK): Likewise.
791 (PREFIX_IGNORED_SHIFT): New.
792 (PREFIX_IGNORED_REPZ): Likewise.
793 (PREFIX_IGNORED_REPNZ): Likewise.
794 (PREFIX_IGNORED_DATA): Likewise.
795 (PREFIX_IGNORED_ADDR): Likewise.
796 (PREFIX_IGNORED_LOCK): Likewise.
797 (PREFIX_OPCODE): Likewise.
798 (PREFIX_IGNORED): Likewise.
799 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
800 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
801 (three_byte_table): Likewise.
802 (mod_table): Likewise.
803 (mandatory_prefix): Renamed to ...
804 (prefix_requirement): This.
805 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
806 Update PREFIX_90 entry.
807 (get_valid_dis386): Check prefix_requirement to see if a prefix
809 (print_insn): Replace mandatory_prefix with prefix_requirement.
811 2015-04-15 Renlin Li <renlin.li@arm.com>
813 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
814 use it for ssat and ssat16.
815 (print_insn_thumb32): Add handle case for 'D' control code.
817 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
818 H.J. Lu <hongjiu.lu@intel.com>
820 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
821 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
822 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
823 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
824 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
825 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
826 Fill prefix_requirement field.
827 (struct dis386): Add prefix_requirement field.
828 (dis386): Fill prefix_requirement field.
829 (dis386_twobyte): Ditto.
830 (twobyte_has_mandatory_prefix_: Remove.
831 (reg_table): Fill prefix_requirement field.
832 (prefix_table): Ditto.
833 (x86_64_table): Ditto.
834 (three_byte_table): Ditto.
837 (vex_len_table): Ditto.
838 (vex_w_table): Ditto.
841 (print_insn): Use prefix_requirement.
842 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
843 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
846 2015-03-30 Mike Frysinger <vapier@gentoo.org>
848 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
850 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
852 * Makefile.in: Regenerated.
854 2015-03-25 Anton Blanchard <anton@samba.org>
856 * ppc-dis.c (disassemble_init_powerpc): Only initialise
857 powerpc_opcd_indices and vle_opcd_indices once.
859 2015-03-25 Anton Blanchard <anton@samba.org>
861 * ppc-opc.c (powerpc_opcodes): Add slbfee.
863 2015-03-24 Terry Guo <terry.guo@arm.com>
865 * arm-dis.c (opcode32): Updated to use new arm feature struct.
866 (opcode16): Likewise.
867 (coprocessor_opcodes): Replace bit with feature struct.
868 (neon_opcodes): Likewise.
869 (arm_opcodes): Likewise.
870 (thumb_opcodes): Likewise.
871 (thumb32_opcodes): Likewise.
872 (print_insn_coprocessor): Likewise.
873 (print_insn_arm): Likewise.
874 (select_arm_features): Follow new feature struct.
876 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
878 * i386-dis.c (rm_table): Add clzero.
879 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
880 Add CPU_CLZERO_FLAGS.
881 (cpu_flags): Add CpuCLZERO.
882 * i386-opc.h: Add CpuCLZERO.
883 * i386-opc.tbl: Add clzero.
884 * i386-init.h: Re-generated.
885 * i386-tbl.h: Re-generated.
887 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
889 * mips-opc.c (decode_mips_operand): Fix constraint issues
890 with u and y operands.
892 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
894 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
896 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
898 * s390-opc.c: Add new IBM z13 instructions.
899 * s390-opc.txt: Likewise.
901 2015-03-10 Renlin Li <renlin.li@arm.com>
903 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
904 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
906 * aarch64-asm-2.c: Regenerate.
907 * aarch64-dis-2.c: Likewise.
908 * aarch64-opc-2.c: Likewise.
910 2015-03-03 Jiong Wang <jiong.wang@arm.com>
912 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
914 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
916 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
918 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
919 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
921 2015-02-23 Vinay <Vinay.G@kpit.com>
923 * rl78-decode.opc (MOV): Added space between two operands for
924 'mov' instruction in index addressing mode.
925 * rl78-decode.c: Regenerate.
927 2015-02-19 Pedro Alves <palves@redhat.com>
929 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
931 2015-02-10 Pedro Alves <palves@redhat.com>
932 Tom Tromey <tromey@redhat.com>
934 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
935 microblaze_and, microblaze_xor.
936 * microblaze-opc.h (opcodes): Adjust.
938 2015-01-28 James Bowman <james.bowman@ftdichip.com>
940 * Makefile.am: Add FT32 files.
941 * configure.ac: Handle FT32.
942 * disassemble.c (disassembler): Call print_insn_ft32.
943 * ft32-dis.c: New file.
944 * ft32-opc.c: New file.
945 * Makefile.in: Regenerate.
946 * configure: Regenerate.
947 * po/POTFILES.in: Regenerate.
949 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
951 * nds32-asm.c (keyword_sr): Add new system registers.
953 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
955 * s390-dis.c (s390_extract_operand): Support vector register
957 (s390_print_insn_with_opcode): Support new operands types and add
958 new handling of optional operands.
959 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
960 and include opcode/s390.h instead.
961 (struct op_struct): New field `flags'.
962 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
963 (dumpTable): Dump flags.
964 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
966 * s390-opc.c: Add new operands types, instruction formats, and
968 (s390_opformats): Add new formats for .insn.
969 * s390-opc.txt: Add new instructions.
971 2015-01-01 Alan Modra <amodra@gmail.com>
973 Update year range in copyright notice of all files.
975 For older changes see ChangeLog-2014
977 Copyright (C) 2015 Free Software Foundation, Inc.
979 Copying and distribution of this file, with or without modification,
980 are permitted in any medium without royalty provided the copyright
981 notice and this notice are preserved.
987 version-control: never