opcodes/ChangeLog

   1 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
   2             Alan Modra  <amodra@gmail.com>
   3
   4         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
   5         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
   6         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
   7         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
   8         XTOP>): Define and add entries.
   9         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
  10         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
  11         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
  12         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
  13
  14 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  15             Alan Modra  <amodra@gmail.com>
  16
  17         * ppc-dis.c (ppc_opts): Add "future" entry.
  18         (PREFIX_OPCD_SEGS): Define.
  19         (prefix_opcd_indices): New array.
  20         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
  21         (lookup_prefix): New function.
  22         (print_insn_powerpc): Handle 64-bit prefix instructions.
  23         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
  24         (PMRR, POWERXX): Define.
  25         (prefix_opcodes): New instruction table.
  26         (prefix_num_opcodes): New constant.
  27
  28 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  29
  30         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
  31         * configure: Regenerated.
  32         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
  33         and cpu/bpf.opc.
  34         (HFILES): Add bpf-desc.h and bpf-opc.h.
  35         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
  36         bpf-ibld.c and bpf-opc.c.
  37         (BPF_DEPS): Define.
  38         * Makefile.in: Regenerated.
  39         * disassemble.c (ARCH_bpf): Define.
  40         (disassembler): Add case for bfd_arch_bpf.
  41         (disassemble_init_for_target): Likewise.
  42         (enum epbf_isa_attr): Define.
  43         * disassemble.h: extern print_insn_bpf.
  44         * bpf-asm.c: Generated.
  45         * bpf-opc.h: Likewise.
  46         * bpf-opc.c: Likewise.
  47         * bpf-ibld.c: Likewise.
  48         * bpf-dis.c: Likewise.
  49         * bpf-desc.h: Likewise.
  50         * bpf-desc.c: Likewise.
  51
  52 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  53
  54         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
  55         and VMSR with the new operands.
  56
  57 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  58
  59         * arm-dis.c (enum mve_instructions): New enum
  60         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
  61         and cneg.
  62         (mve_opcodes): New instructions as above.
  63         (is_mve_encoding_conflict): Add cases for csinc, csinv,
  64         csneg and csel.
  65         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
  66
  67 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  68
  69         * arm-dis.c (emun mve_instructions): Updated for new instructions.
  70         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
  71         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
  72         uqshl, urshrl and urshr.
  73         (is_mve_okay_in_it): Add new instructions to TRUE list.
  74         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
  75         (print_insn_mve): Updated to accept new %j,
  76         %<bitfield>m and %<bitfield>n patterns.
  77
  78 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
  79
  80         * mips-opc.c (mips_builtin_opcodes): Change source register
  81         constraint for DAUI.
  82
  83 2019-05-20  Nick Clifton  <nickc@redhat.com>
  84
  85         * po/fr.po: Updated French translation.
  86
  87 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  88             Michael Collison <michael.collison@arm.com>
  89
  90         * arm-dis.c (thumb32_opcodes): Add new instructions.
  91         (enum mve_instructions): Likewise.
  92         (enum mve_undefined): Add new reasons.
  93         (is_mve_encoding_conflict): Handle new instructions.
  94         (is_mve_undefined): Likewise.
  95         (is_mve_unpredictable): Likewise.
  96         (print_mve_undefined): Likewise.
  97         (print_mve_size): Likewise.
  98
  99 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 100             Michael Collison <michael.collison@arm.com>
 101
 102         * arm-dis.c (thumb32_opcodes): Add new instructions.
 103         (enum mve_instructions): Likewise.
 104         (is_mve_encoding_conflict): Handle new instructions.
 105         (is_mve_undefined): Likewise.
 106         (is_mve_unpredictable): Likewise.
 107         (print_mve_size): Likewise.
 108
 109 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 110             Michael Collison <michael.collison@arm.com>
 111
 112         * arm-dis.c (thumb32_opcodes): Add new instructions.
 113         (enum mve_instructions): Likewise.
 114         (is_mve_encoding_conflict): Likewise.
 115         (is_mve_unpredictable): Likewise.
 116         (print_mve_size): Likewise.
 117
 118 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 119             Michael Collison <michael.collison@arm.com>
 120
 121         * arm-dis.c (thumb32_opcodes): Add new instructions.
 122         (enum mve_instructions): Likewise.
 123         (is_mve_encoding_conflict): Handle new instructions.
 124         (is_mve_undefined): Likewise.
 125         (is_mve_unpredictable): Likewise.
 126         (print_mve_size): Likewise.
 127
 128 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 129             Michael Collison <michael.collison@arm.com>
 130
 131         * arm-dis.c (thumb32_opcodes): Add new instructions.
 132         (enum mve_instructions): Likewise.
 133         (is_mve_encoding_conflict): Handle new instructions.
 134         (is_mve_undefined): Likewise.
 135         (is_mve_unpredictable): Likewise.
 136         (print_mve_size): Likewise.
 137         (print_insn_mve): Likewise.
 138
 139 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 140             Michael Collison <michael.collison@arm.com>
 141
 142         * arm-dis.c (thumb32_opcodes): Add new instructions.
 143         (print_insn_thumb32): Handle new instructions.
 144
 145 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 146             Michael Collison <michael.collison@arm.com>
 147
 148         * arm-dis.c (enum mve_instructions): Add new instructions.
 149         (enum mve_undefined): Add new reasons.
 150         (is_mve_encoding_conflict): Handle new instructions.
 151         (is_mve_undefined): Likewise.
 152         (is_mve_unpredictable): Likewise.
 153         (print_mve_undefined): Likewise.
 154         (print_mve_size): Likewise.
 155         (print_mve_shift_n): Likewise.
 156         (print_insn_mve): Likewise.
 157
 158 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 159             Michael Collison <michael.collison@arm.com>
 160
 161         * arm-dis.c (enum mve_instructions): Add new instructions.
 162         (is_mve_encoding_conflict): Handle new instructions.
 163         (is_mve_unpredictable): Likewise.
 164         (print_mve_rotate): Likewise.
 165         (print_mve_size): Likewise.
 166         (print_insn_mve): Likewise.
 167
 168 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 169             Michael Collison <michael.collison@arm.com>
 170
 171         * arm-dis.c (enum mve_instructions): Add new instructions.
 172         (is_mve_encoding_conflict): Handle new instructions.
 173         (is_mve_unpredictable): Likewise.
 174         (print_mve_size): Likewise.
 175         (print_insn_mve): Likewise.
 176
 177 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 178             Michael Collison <michael.collison@arm.com>
 179
 180         * arm-dis.c (enum mve_instructions): Add new instructions.
 181         (enum mve_undefined): Add new reasons.
 182         (is_mve_encoding_conflict): Handle new instructions.
 183         (is_mve_undefined): Likewise.
 184         (is_mve_unpredictable): Likewise.
 185         (print_mve_undefined): Likewise.
 186         (print_mve_size): Likewise.
 187         (print_insn_mve): Likewise.
 188
 189 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 190             Michael Collison <michael.collison@arm.com>
 191
 192         * arm-dis.c (enum mve_instructions): Add new instructions.
 193         (is_mve_encoding_conflict): Handle new instructions.
 194         (is_mve_undefined): Likewise.
 195         (is_mve_unpredictable): Likewise.
 196         (print_mve_size): Likewise.
 197         (print_insn_mve): Likewise.
 198
 199 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 200             Michael Collison <michael.collison@arm.com>
 201
 202         * arm-dis.c (enum mve_instructions): Add new instructions.
 203         (enum mve_unpredictable): Add new reasons.
 204         (enum mve_undefined): Likewise.
 205         (is_mve_okay_in_it): Handle new isntructions.
 206         (is_mve_encoding_conflict): Likewise.
 207         (is_mve_undefined): Likewise.
 208         (is_mve_unpredictable): Likewise.
 209         (print_mve_vmov_index): Likewise.
 210         (print_simd_imm8): Likewise.
 211         (print_mve_undefined): Likewise.
 212         (print_mve_unpredictable): Likewise.
 213         (print_mve_size): Likewise.
 214         (print_insn_mve): Likewise.
 215
 216 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 217             Michael Collison <michael.collison@arm.com>
 218
 219         * arm-dis.c (enum mve_instructions): Add new instructions.
 220         (enum mve_unpredictable): Add new reasons.
 221         (enum mve_undefined): Likewise.
 222         (is_mve_encoding_conflict): Handle new instructions.
 223         (is_mve_undefined): Likewise.
 224         (is_mve_unpredictable): Likewise.
 225         (print_mve_undefined): Likewise.
 226         (print_mve_unpredictable): Likewise.
 227         (print_mve_rounding_mode): Likewise.
 228         (print_mve_vcvt_size): Likewise.
 229         (print_mve_size): Likewise.
 230         (print_insn_mve): Likewise.
 231
 232 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 233             Michael Collison <michael.collison@arm.com>
 234
 235         * arm-dis.c (enum mve_instructions): Add new instructions.
 236         (enum mve_unpredictable): Add new reasons.
 237         (enum mve_undefined): Likewise.
 238         (is_mve_undefined): Handle new instructions.
 239         (is_mve_unpredictable): Likewise.
 240         (print_mve_undefined): Likewise.
 241         (print_mve_unpredictable): Likewise.
 242         (print_mve_size): Likewise.
 243         (print_insn_mve): Likewise.
 244
 245 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 246             Michael Collison <michael.collison@arm.com>
 247
 248         * arm-dis.c (enum mve_instructions): Add new instructions.
 249         (enum mve_undefined): Add new reasons.
 250         (insns): Add new instructions.
 251         (is_mve_encoding_conflict):
 252         (print_mve_vld_str_addr): New print function.
 253         (is_mve_undefined): Handle new instructions.
 254         (is_mve_unpredictable): Likewise.
 255         (print_mve_undefined): Likewise.
 256         (print_mve_size): Likewise.
 257         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 258         (print_insn_mve):  Handle new operands.
 259
 260 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 261             Michael Collison <michael.collison@arm.com>
 262
 263         * arm-dis.c (enum mve_instructions): Add new instructions.
 264         (enum mve_unpredictable): Add new reasons.
 265         (is_mve_encoding_conflict): Handle new instructions.
 266         (is_mve_unpredictable): Likewise.
 267         (mve_opcodes): Add new instructions.
 268         (print_mve_unpredictable): Handle new reasons.
 269         (print_mve_register_blocks): New print function.
 270         (print_mve_size): Handle new instructions.
 271         (print_insn_mve): Likewise.
 272
 273 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 274             Michael Collison <michael.collison@arm.com>
 275
 276         * arm-dis.c (enum mve_instructions): Add new instructions.
 277         (enum mve_unpredictable): Add new reasons.
 278         (enum mve_undefined): Likewise.
 279         (is_mve_encoding_conflict): Handle new instructions.
 280         (is_mve_undefined): Likewise.
 281         (is_mve_unpredictable): Likewise.
 282         (coprocessor_opcodes): Move NEON VDUP from here...
 283         (neon_opcodes): ... to here.
 284         (mve_opcodes): Add new instructions.
 285         (print_mve_undefined):  Handle new reasons.
 286         (print_mve_unpredictable): Likewise.
 287         (print_mve_size): Handle new instructions.
 288         (print_insn_neon): Handle vdup.
 289         (print_insn_mve): Handle new operands.
 290
 291 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 292             Michael Collison <michael.collison@arm.com>
 293
 294         * arm-dis.c (enum mve_instructions): Add new instructions.
 295         (enum mve_unpredictable): Add new values.
 296         (mve_opcodes): Add new instructions.
 297         (vec_condnames): New array with vector conditions.
 298         (mve_predicatenames): New array with predicate suffixes.
 299         (mve_vec_sizename): New array with vector sizes.
 300         (enum vpt_pred_state): New enum with vector predication states.
 301         (struct vpt_block): New struct type for vpt blocks.
 302         (vpt_block_state): Global struct to keep track of state.
 303         (mve_extract_pred_mask): New helper function.
 304         (num_instructions_vpt_block): Likewise.
 305         (mark_outside_vpt_block): Likewise.
 306         (mark_inside_vpt_block): Likewise.
 307         (invert_next_predicate_state): Likewise.
 308         (update_next_predicate_state): Likewise.
 309         (update_vpt_block_state): Likewise.
 310         (is_vpt_instruction): Likewise.
 311         (is_mve_encoding_conflict): Add entries for new instructions.
 312         (is_mve_unpredictable): Likewise.
 313         (print_mve_unpredictable): Handle new cases.
 314         (print_instruction_predicate): Likewise.
 315         (print_mve_size): New function.
 316         (print_vec_condition): New function.
 317         (print_insn_mve): Handle vpt blocks and new print operands.
 318
 319 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 320
 321         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 322         8, 14 and 15 for Armv8.1-M Mainline.
 323
 324 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 325             Michael Collison <michael.collison@arm.com>
 326
 327         * arm-dis.c (enum mve_instructions): New enum.
 328         (enum mve_unpredictable): Likewise.
 329         (enum mve_undefined): Likewise.
 330         (struct mopcode32): New struct.
 331         (is_mve_okay_in_it): New function.
 332         (is_mve_architecture): Likewise.
 333         (arm_decode_field): Likewise.
 334         (arm_decode_field_multiple): Likewise.
 335         (is_mve_encoding_conflict): Likewise.
 336         (is_mve_undefined): Likewise.
 337         (is_mve_unpredictable): Likewise.
 338         (print_mve_undefined): Likewise.
 339         (print_mve_unpredictable): Likewise.
 340         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 341         (print_insn_mve): New function.
 342         (print_insn_thumb32): Handle MVE architecture.
 343         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 344
 345 2019-05-10  Nick Clifton  <nickc@redhat.com>
 346
 347         PR 24538
 348         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 349         end of the table prematurely.
 350
 351 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 352
 353         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 354         macros for R6.
 355
 356 2019-05-11  Alan Modra  <amodra@gmail.com>
 357
 358         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 359         when -Mraw is in effect.
 360
 361 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 362
 363         * aarch64-dis-2.c: Regenerate.
 364         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 365         (OP_SVE_BBB): New variant set.
 366         (OP_SVE_DDDD): New variant set.
 367         (OP_SVE_HHH): New variant set.
 368         (OP_SVE_HHHU): New variant set.
 369         (OP_SVE_SSS): New variant set.
 370         (OP_SVE_SSSU): New variant set.
 371         (OP_SVE_SHH): New variant set.
 372         (OP_SVE_SBBU): New variant set.
 373         (OP_SVE_DSS): New variant set.
 374         (OP_SVE_DHHU): New variant set.
 375         (OP_SVE_VMV_HSD_BHS): New variant set.
 376         (OP_SVE_VVU_HSD_BHS): New variant set.
 377         (OP_SVE_VVVU_SD_BH): New variant set.
 378         (OP_SVE_VVVU_BHSD): New variant set.
 379         (OP_SVE_VVV_QHD_DBS): New variant set.
 380         (OP_SVE_VVV_HSD_BHS): New variant set.
 381         (OP_SVE_VVV_HSD_BHS2): New variant set.
 382         (OP_SVE_VVV_BHS_HSD): New variant set.
 383         (OP_SVE_VV_BHS_HSD): New variant set.
 384         (OP_SVE_VVV_SD): New variant set.
 385         (OP_SVE_VVU_BHS_HSD): New variant set.
 386         (OP_SVE_VZVV_SD): New variant set.
 387         (OP_SVE_VZVV_BH): New variant set.
 388         (OP_SVE_VZV_SD): New variant set.
 389         (aarch64_opcode_table): Add sve2 instructions.
 390
 391 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 392
 393         * aarch64-asm-2.c: Regenerated.
 394         * aarch64-dis-2.c: Regenerated.
 395         * aarch64-opc-2.c: Regenerated.
 396         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 397         for SVE_SHLIMM_UNPRED_22.
 398         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 399         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 400         operand.
 401
 402 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 403
 404         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 405         sve_size_tsz_bhs iclass encode.
 406         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 407         sve_size_tsz_bhs iclass decode.
 408
 409 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 410
 411         * aarch64-asm-2.c: Regenerated.
 412         * aarch64-dis-2.c: Regenerated.
 413         * aarch64-opc-2.c: Regenerated.
 414         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 415         for SVE_Zm4_11_INDEX.
 416         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 417         (fields): Handle SVE_i2h field.
 418         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 419         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 420
 421 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 422
 423         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 424         sve_shift_tsz_bhsd iclass encode.
 425         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 426         sve_shift_tsz_bhsd iclass decode.
 427
 428 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 429
 430         * aarch64-asm-2.c: Regenerated.
 431         * aarch64-dis-2.c: Regenerated.
 432         * aarch64-opc-2.c: Regenerated.
 433         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 434         (aarch64_encode_variant_using_iclass): Handle
 435         sve_shift_tsz_hsd iclass encode.
 436         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 437         sve_shift_tsz_hsd iclass decode.
 438         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 439         for SVE_SHRIMM_UNPRED_22.
 440         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 441         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 442         operand.
 443
 444 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 445
 446         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 447         sve_size_013 iclass encode.
 448         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 449         sve_size_013 iclass decode.
 450
 451 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 452
 453         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 454         sve_size_bh iclass encode.
 455         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 456         sve_size_bh iclass decode.
 457
 458 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 459
 460         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 461         sve_size_sd2 iclass encode.
 462         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 463         sve_size_sd2 iclass decode.
 464         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 465         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 466
 467 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 468
 469         * aarch64-asm-2.c: Regenerated.
 470         * aarch64-dis-2.c: Regenerated.
 471         * aarch64-opc-2.c: Regenerated.
 472         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 473         for SVE_ADDR_ZX.
 474         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 475         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 476
 477 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 478
 479         * aarch64-asm-2.c: Regenerated.
 480         * aarch64-dis-2.c: Regenerated.
 481         * aarch64-opc-2.c: Regenerated.
 482         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 483         for SVE_Zm3_11_INDEX.
 484         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 485         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 486         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 487         fields.
 488         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 489
 490 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 491
 492         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 493         sve_size_hsd2 iclass encode.
 494         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 495         sve_size_hsd2 iclass decode.
 496         * aarch64-opc.c (fields): Handle SVE_size field.
 497         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 498
 499 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 500
 501         * aarch64-asm-2.c: Regenerated.
 502         * aarch64-dis-2.c: Regenerated.
 503         * aarch64-opc-2.c: Regenerated.
 504         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 505         for SVE_IMM_ROT3.
 506         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 507         (fields): Handle SVE_rot3 field.
 508         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 509         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 510
 511 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 512
 513         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 514         instructions.
 515
 516 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 517
 518         * aarch64-tbl.h
 519         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 520         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 521         aarch64_feature_sve2bitperm): New feature sets.
 522         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 523         for feature set addresses.
 524         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 525         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 526
 527 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 528             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 529
 530         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 531         argument and set ASE_EVA_R6 appropriately.
 532         (set_default_mips_dis_options): Pass ISA to above.
 533         (parse_mips_dis_option): Likewise.
 534         * mips-opc.c (EVAR6): New macro.
 535         (mips_builtin_opcodes): Add llwpe, scwpe.
 536
 537 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 538
 539         * aarch64-asm-2.c: Regenerated.
 540         * aarch64-dis-2.c: Regenerated.
 541         * aarch64-opc-2.c: Regenerated.
 542         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 543         AARCH64_OPND_TME_UIMM16.
 544         (aarch64_print_operand): Likewise.
 545         * aarch64-tbl.h (QL_IMM_NIL): New.
 546         (TME): New.
 547         (_TME_INSN): New.
 548         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 549
 550 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 551
 552         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 553
 554 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 555             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 556
 557         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 558
 559 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 560
 561         * s12z-opc.h: Add extern "C" bracketing to help
 562         users who wish to use this interface in c++ code.
 563
 564 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 565
 566         * s12z-opc.c (bm_decode): Handle bit map operations with the
 567         "reserved0" mode.
 568
 569 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 570
 571         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 572         specifier.  Add entries for VLDR and VSTR of system registers.
 573         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 574         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 575         of %J and %K format specifier.
 576
 577 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 578
 579         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 580         Add new entries for VSCCLRM instruction.
 581         (print_insn_coprocessor): Handle new %C format control code.
 582
 583 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 584
 585         * arm-dis.c (enum isa): New enum.
 586         (struct sopcode32): New structure.
 587         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 588         set isa field of all current entries to ANY.
 589         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 590         Only match an entry if its isa field allows the current mode.
 591
 592 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 593
 594         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 595         CLRM.
 596         (print_insn_thumb32): Add logic to print %n CLRM register list.
 597
 598 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 599
 600         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 601         and %Q patterns.
 602
 603 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 604
 605         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 606         (print_insn_thumb32): Edit the switch case for %Z.
 607
 608 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 609
 610         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 611
 612 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 613
 614         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 615
 616 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 617
 618         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 619
 620 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 621
 622         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 623         Arm register with r13 and r15 unpredictable.
 624         (thumb32_opcodes): New instructions for bfx and bflx.
 625
 626 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 627
 628         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 629
 630 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 631
 632         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 633
 634 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 635
 636         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 637
 638 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 639
 640         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 641
 642 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 643
 644         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 645         "optr". ("operator" is a reserved word in c++).
 646
 647 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 648
 649         * aarch64-opc.c (aarch64_print_operand): Add case for
 650         AARCH64_OPND_Rt_SP.
 651         (verify_constraints): Likewise.
 652         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 653         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 654         to accept Rt|SP as first operand.
 655         (AARCH64_OPERANDS): Add new Rt_SP.
 656         * aarch64-asm-2.c: Regenerated.
 657         * aarch64-dis-2.c: Regenerated.
 658         * aarch64-opc-2.c: Regenerated.
 659
 660 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 661
 662         * aarch64-asm-2.c: Regenerated.
 663         * aarch64-dis-2.c: Likewise.
 664         * aarch64-opc-2.c: Likewise.
 665         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 666
 667 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 668
 669         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 670
 671 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 672
 673         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 674         * i386-init.h: Regenerated.
 675
 676 2019-04-07  Alan Modra  <amodra@gmail.com>
 677
 678         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 679         op_separator to control printing of spaces, comma and parens
 680         rather than need_comma, need_paren and spaces vars.
 681
 682 2019-04-07  Alan Modra  <amodra@gmail.com>
 683
 684         PR 24421
 685         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 686         (print_insn_neon, print_insn_arm): Likewise.
 687
 688 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 689
 690         * i386-dis-evex.h (evex_table): Updated to support BF16
 691         instructions.
 692         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 693         and EVEX_W_0F3872_P_3.
 694         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 695         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 696         * i386-opc.h (enum): Add CpuAVX512_BF16.
 697         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 698         * i386-opc.tbl: Add AVX512 BF16 instructions.
 699         * i386-init.h: Regenerated.
 700         * i386-tbl.h: Likewise.
 701
 702 2019-04-05  Alan Modra  <amodra@gmail.com>
 703
 704         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 705         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 706         to favour printing of "-" branch hint when using the "y" bit.
 707         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 708
 709 2019-04-05  Alan Modra  <amodra@gmail.com>
 710
 711         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 712         opcode until first operand is output.
 713
 714 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 715
 716         PR gas/24349
 717         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 718         (valid_bo_post_v2): Add support for 'at' branch hints.
 719         (insert_bo): Only error on branch on ctr.
 720         (get_bo_hint_mask): New function.
 721         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 722         for inserting 'at' branch hints.
 723         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 724         for extracting 'at' branch hints.
 725         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 726         (BOE): Delete operand.
 727         (BOM, BOP): New operands.
 728         (RM): Update value.
 729         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 730         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 731         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 732         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 733         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 734         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 735         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 736         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 737         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 738         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 739         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 740         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 741         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 742         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 743         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 744         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 745         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 746         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 747         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 748         bttarl+>: New extended mnemonics.
 749
 750 2019-03-28  Alan Modra  <amodra@gmail.com>
 751
 752         PR 24390
 753         * ppc-opc.c (BTF): Define.
 754         (powerpc_opcodes): Use for mtfsb*.
 755         * ppc-dis.c (print_insn_powerpc): Print fields with both
 756         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 757
 758 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 759
 760         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 761         (mapping_symbol_for_insn): Implement new algorithm.
 762         (print_insn): Remove duplicate code.
 763
 764 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 765
 766         * aarch64-dis.c (print_insn_aarch64):
 767         Implement override.
 768
 769 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 770
 771         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 772         order.
 773
 774 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 775
 776         * aarch64-dis.c (last_stop_offset): New.
 777         (print_insn_aarch64): Use stop_offset.
 778
 779 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 780
 781         PR gas/24359
 782         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 783         CPU_ANY_AVX2_FLAGS.
 784         * i386-init.h: Regenerated.
 785
 786 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 787
 788         PR gas/24348
 789         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 790         vmovdqu16, vmovdqu32 and vmovdqu64.
 791         * i386-tbl.h: Regenerated.
 792
 793 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 794
 795         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 796         from vstrszb, vstrszh, and vstrszf.
 797
 798 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 799
 800         * s390-opc.txt: Add instruction descriptions.
 801
 802 2019-02-08  Jim Wilson  <jimw@sifive.com>
 803
 804         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 805         <bne>: Likewise.
 806
 807 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 808
 809         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 810
 811 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 812
 813         PR binutils/23212
 814         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 815         * aarch64-opc.c (verify_elem_sd): New.
 816         (fields): Add FLD_sz entr.
 817         * aarch64-tbl.h (_SIMD_INSN): New.
 818         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 819         fmulx scalar and vector by element isns.
 820
 821 2019-02-07  Nick Clifton  <nickc@redhat.com>
 822
 823         * po/sv.po: Updated Swedish translation.
 824
 825 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 826
 827         * s390-mkopc.c (main): Accept arch13 as cpu string.
 828         * s390-opc.c: Add new instruction formats and instruction opcode
 829         masks.
 830         * s390-opc.txt: Add new arch13 instructions.
 831
 832 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 833
 834         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 835         (aarch64_opcode): Change encoding for stg, stzg
 836         st2g and st2zg.
 837         * aarch64-asm-2.c: Regenerated.
 838         * aarch64-dis-2.c: Regenerated.
 839         * aarch64-opc-2.c: Regenerated.
 840
 841 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 842
 843         * aarch64-asm-2.c: Regenerated.
 844         * aarch64-dis-2.c: Likewise.
 845         * aarch64-opc-2.c: Likewise.
 846         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 847
 848 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 849             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 850
 851         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 852         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 853         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 854         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 855         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 856         case for ldstgv_indexed.
 857         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 858         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 859         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 860         * aarch64-asm-2.c: Regenerated.
 861         * aarch64-dis-2.c: Regenerated.
 862         * aarch64-opc-2.c: Regenerated.
 863
 864 2019-01-23  Nick Clifton  <nickc@redhat.com>
 865
 866         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 867
 868 2019-01-21  Nick Clifton  <nickc@redhat.com>
 869
 870         * po/de.po: Updated German translation.
 871         * po/uk.po: Updated Ukranian translation.
 872
 873 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 874         * mips-dis.c (mips_arch_choices): Fix typo in
 875         gs464, gs464e and gs264e descriptors.
 876
 877 2019-01-19  Nick Clifton  <nickc@redhat.com>
 878
 879         * configure: Regenerate.
 880         * po/opcodes.pot: Regenerate.
 881
 882 2018-06-24  Nick Clifton  <nickc@redhat.com>
 883
 884         2.32 branch created.
 885
 886 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 887
 888         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 889         if it is null.
 890         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 891         zero.
 892
 893 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 894
 895         * configure: Regenerate.
 896
 897 2019-01-07  Alan Modra  <amodra@gmail.com>
 898
 899         * configure: Regenerate.
 900         * po/POTFILES.in: Regenerate.
 901
 902 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 903
 904         * s12z-opc.c: New file.
 905         * s12z-opc.h: New file.
 906         * s12z-dis.c: Removed all code not directly related to display
 907         of instructions.  Used the interface provided by the new files
 908         instead.
 909         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 910         * Makefile.in: Regenerate.
 911         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 912         * configure: Regenerate.
 913
 914 2019-01-01  Alan Modra  <amodra@gmail.com>
 915
 916         Update year range in copyright notice of all files.
 917
 918 For older changes see ChangeLog-2018
 919 \f
 920 Copyright (C) 2019 Free Software Foundation, Inc.
 921
 922 Copying and distribution of this file, with or without modification,
 923 are permitted in any medium without royalty provided the copyright
 924 notice and this notice are preserved.
 925
 926 Local Variables:
 927 mode: change-log
 928 left-margin: 8
 929 fill-column: 74
 930 version-control: never
 931 End: