opcodes/ChangeLog

   1 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
   2
   3         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
   4         entries and associated comments.
   5
   6 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
   7
   8         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
   9         of "c0".
  10
  11 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  12
  13         * mips-dis.c (mips_cp1_names_mips): New variable.
  14         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
  15         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
  16         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
  17         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
  18         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
  19         "loongson2f".
  20
  21 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  22
  23         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
  24         handling code over to...
  25         <OP_REG_CONTROL>: ... this new case.
  26         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
  27         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
  28         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
  29         replacing the `G' operand code with `g'.  Update "cftc1" and
  30         "cftc2" entries replacing the `E' operand code with `y'.
  31         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
  32         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
  33         entries replacing the `G' operand code with `g'.
  34
  35 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  36
  37         * mips-dis.c (mips_cp0_names_r3900): New variable.
  38         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
  39         for "r3900".
  40
  41 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  42
  43         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
  44         and "mtthc2" to using the `G' rather than `g' operand code for
  45         the coprocessor control register referred.
  46
  47 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  48
  49         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
  50         entries with each other.
  51
  52 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
  53
  54         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
  55
  56 2021-05-25  Alan Modra  <amodra@gmail.com>
  57
  58         * cris-desc.c: Regenerate.
  59         * cris-desc.h: Regenerate.
  60         * cris-opc.h: Regenerate.
  61         * po/POTFILES.in: Regenerate.
  62
  63 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
  64
  65         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
  66         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
  67         (CGEN_CPUS): Add cris.
  68         (CRIS_DEPS): Define.
  69         (stamp-cris): New rule.
  70         * cgen.sh: Handle desc action.
  71         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
  72         * Makefile.in, configure: Regenerate.
  73
  74 2021-05-18  Job Noorman  <mtvec@pm.me>
  75
  76         PR 27814
  77         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
  78         the elf objects.
  79
  80 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
  81
  82         * arm-dis.c (mve_opcodes): Fix disassembly of
  83         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
  84         (is_mve_encoding_conflict): MVE vector loads should not match
  85         when P = W = 0.
  86         (is_mve_unpredictable): It's not unpredictable to use the same
  87         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
  88
  89 2021-05-11  Nick Clifton  <nickc@redhat.com>
  90
  91         PR 27840
  92         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
  93         the end of the code buffer.
  94
  95 2021-05-06  Stafford Horne  <shorne@gmail.com>
  96
  97         PR 21464
  98         * or1k-asm.c: Regenerate.
  99
 100 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 101
 102         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 103         info->insn_info_valid.
 104
 105 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-opc.tbl (lea): Add Optimize.
 108         * opcodes/i386-tbl.h: Re-generate.
 109
 110 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 111
 112         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 113         of l32r fetch and display referenced literal value.
 114
 115 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 116
 117         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 118         to 4 for literal disassembly.
 119
 120 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 121
 122         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 123         for TLBI instruction.
 124
 125 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 126
 127         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 128         DC instruction.
 129
 130 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 131
 132         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 133         "qualifier".
 134         (convert_mov_to_movewide): Add initializer for "value".
 135
 136 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 137
 138         * aarch64-opc.c: Add RME system registers.
 139
 140 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 141
 142         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 143         "addi d,CV,z" to "c.mv d,CV".
 144
 145 2021-04-12  Alan Modra  <amodra@gmail.com>
 146
 147         * configure.ac (--enable-checking): Add support.
 148         * config.in: Regenerate.
 149         * configure: Regenerate.
 150
 151 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 152
 153         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 154         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 155
 156 2021-04-09  Alan Modra  <amodra@gmail.com>
 157
 158         * ppc-dis.c (struct dis_private): Add "special".
 159         (POWERPC_DIALECT): Delete.  Replace uses with..
 160         (private_data): ..this.  New inline function.
 161         (disassemble_init_powerpc): Init "special" names.
 162         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 163         field of prefix instructions.
 164         (bsearch_reloc, print_got_plt): New functions.
 165         (print_insn_powerpc): For pcrel instructions, print target address
 166         and symbol if known, and decode plt and got loads too.
 167
 168 2021-04-08  Alan Modra  <amodra@gmail.com>
 169
 170         PR 27684
 171         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 172
 173 2021-04-08  Alan Modra  <amodra@gmail.com>
 174
 175         PR 27676
 176         * ppc-opc.c (DCBT_EO): Move earlier.
 177         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 178         (powerpc_operands): Add THCT and THDS entries.
 179         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 180
 181 2021-04-06  Alan Modra  <amodra@gmail.com>
 182
 183         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 184         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 185         symbol_at_address_func.
 186
 187 2021-04-05  Alan Modra  <amodra@gmail.com>
 188
 189         * configure.ac: Don't check for limits.h, string.h, strings.h or
 190         stdlib.h.
 191         (AC_ISC_POSIX): Don't invoke.
 192         * sysdep.h: Include stdlib.h and string.h unconditionally.
 193         * i386-opc.h: Include limits.h unconditionally.
 194         * wasm32-dis.c: Likewise.
 195         * cgen-opc.c: Don't include alloca-conf.h.
 196         * config.in: Regenerate.
 197         * configure: Regenerate.
 198
 199 2021-04-01  Martin Liska  <mliska@suse.cz>
 200
 201         * arm-dis.c (strneq): Remove strneq and use startswith.
 202         * cr16-dis.c (print_insn_cr16): Likewise.
 203         * score-dis.c (streq): Likewise.
 204         (strneq): Likewise.
 205         * score7-dis.c (strneq): Likewise.
 206
 207 2021-04-01  Alan Modra  <amodra@gmail.com>
 208
 209         PR 27675
 210         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 211
 212 2021-03-31  Alan Modra  <amodra@gmail.com>
 213
 214         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 215         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 216         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 217         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 218         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 219         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 220         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 221         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 222         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 223         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 224         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 225         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 226         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 227         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 228         and TRUE with true throughout.
 229
 230 2021-03-31  Alan Modra  <amodra@gmail.com>
 231
 232         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 233         * aarch64-dis.h: Likewise.
 234         * aarch64-opc.c: Likewise.
 235         * avr-dis.c: Likewise.
 236         * csky-dis.c: Likewise.
 237         * nds32-asm.c: Likewise.
 238         * nds32-dis.c: Likewise.
 239         * nfp-dis.c: Likewise.
 240         * riscv-dis.c: Likewise.
 241         * s12z-dis.c: Likewise.
 242         * wasm32-dis.c: Likewise.
 243
 244 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 245
 246         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 247         (i386_seg_prefixes): New.
 248         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 249         (i386_seg_prefixes): Declare.
 250
 251 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 254
 255 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 256
 257         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 258         * i386-reg.tbl (st): Move down.
 259         (st(0)): Delete. Extend comment.
 260         * i386-tbl.h: Re-generate.
 261
 262 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 263
 264         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 265         (cmpsd): Move next to cmps.
 266         (movsd): Move next to movs.
 267         (cmpxchg16b): Move to separate section.
 268         (fisttp, fisttpll): Likewise.
 269         (monitor, mwait): Likewise.
 270         * i386-tbl.h: Re-generate.
 271
 272 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 273
 274         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 275         (vpsadbw): Add C.
 276         * i386-tbl.h: Re-generate.
 277
 278 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 279
 280         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 281         pclmul, gfni): New templates. Use them wherever possible. Move
 282         SSE4.1 pextrw into respective section.
 283         * i386-tbl.h: Re-generate.
 284
 285 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 288         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 289         "length".
 290         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 291         Convert all of their uses to representation in opcode.
 292
 293 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 294
 295         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 296         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 297         value of None. Shrink operands to 3 bits.
 298
 299 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 300
 301         * i386-gen.c (process_i386_opcode_modifier): New parameter
 302         "space".
 303         (output_i386_opcode): New local variable "space". Adjust
 304         process_i386_opcode_modifier() invocation.
 305         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 306         invocation.
 307         * i386-tbl.h: Re-generate.
 308
 309 2021-03-29  Alan Modra  <amodra@gmail.com>
 310
 311         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 312         (fp_qualifier_p, get_data_pattern): Likewise.
 313         (aarch64_get_operand_modifier_from_value): Likewise.
 314         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 315         (operand_variant_qualifier_p): Likewise.
 316         (qualifier_value_in_range_constraint_p): Likewise.
 317         (aarch64_get_qualifier_esize): Likewise.
 318         (aarch64_get_qualifier_nelem): Likewise.
 319         (aarch64_get_qualifier_standard_value): Likewise.
 320         (get_lower_bound, get_upper_bound): Likewise.
 321         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 322         (aarch64_print_operand): Likewise.
 323         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 324         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 325         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 326         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 327         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 328         (print_insn_tic6x): Likewise.
 329
 330 2021-03-29  Alan Modra  <amodra@gmail.com>
 331
 332         * arc-dis.c (extract_operand_value): Correct NULL cast.
 333         * frv-opc.h: Regenerate.
 334
 335 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 336
 337         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 338         MMX form.
 339         * i386-tbl.h: Re-generate.
 340
 341 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 342
 343         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 344         immediate in br.n instruction.
 345
 346 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 347
 348         * i386-dis.c (XMGatherD, VexGatherD): New.
 349         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 350         (print_insn): Check masking for S/G insns.
 351         (OP_E_memory): New local variable check_gather. Extend mandatory
 352         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 353         Extend check for disallowed 16-bit addressing.
 354         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 355         if()s to switch(). Check register conflicts for (VEX-encoded)
 356         gathers. Drop no longer reachable cases.
 357         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 358         vgatherdp*.
 359
 360 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 361
 362         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 363         zeroing-masking without masking.
 364
 365 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 368         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 369         single-operand forms as deprecated.
 370         * i386-tbl.h: Re-generate.
 371
 372 2021-03-25  Alan Modra  <amodra@gmail.com>
 373
 374         PR 27647
 375         * ppc-opc.c (XLOCB_MASK): Delete.
 376         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 377         XLBH_MASK.
 378         (powerpc_opcodes): Accept a BH field on all extended forms of
 379         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 380
 381 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 382
 383         * i386-gen.c (output_i386_opcode): Drop processing of
 384         opcode_length. Calculate length from base_opcode. Adjust prefix
 385         encoding determination.
 386         (process_i386_opcodes): Drop output of fake opcode_length.
 387         * i386-opc.h (struct insn_template): Drop opcode_length field.
 388         * i386-opc.tbl: Drop opcode length field from all templates.
 389         * i386-tbl.h: Re-generate.
 390
 391 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 392
 393         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 394         parameter "prefix". Drop local variable "regular_encoding".
 395         Record prefix setting / check for consistency.
 396         (output_i386_opcode): Parse opcode_length and base_opcode
 397         earlier. Derive prefix encoding. Drop no longer applicable
 398         consistency checking. Adjust process_i386_opcode_modifier()
 399         invocation.
 400         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 401         invocation.
 402         * i386-tbl.h: Re-generate.
 403
 404 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 405
 406         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 407         check.
 408         * i386-opc.h (Prefix_*): Move #define-s.
 409         * i386-opc.tbl: Move pseudo prefix enumerator values to
 410         extension opcode field. Introduce pseudopfx template.
 411         * i386-tbl.h: Re-generate.
 412
 413 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 414
 415         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 416         comment.
 417         * i386-tbl.h: Re-generate.
 418
 419 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-opc.h (struct insn_template): Move cpu_flags field past
 422         opcode_modifier one.
 423         * i386-tbl.h: Re-generate.
 424
 425 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 426
 427         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 428         * i386-opc.h (OpcodeSpace): New enumerator.
 429         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 430         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 431         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 432         (struct i386_opcode_modifier): New field opcodespace. Shrink
 433         opcodeprefix field.
 434         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 435         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 436         OpcodePrefix uses.
 437         * i386-tbl.h: Re-generate.
 438
 439 2021-03-22  Martin Liska  <mliska@suse.cz>
 440
 441         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 442         * arc-dis.c (parse_option): Likewise.
 443         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 444         * cris-dis.c (print_with_operands): Likewise.
 445         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 446         * i386-dis.c (print_insn): Likewise.
 447         * ia64-gen.c (fetch_insn_class): Likewise.
 448         (parse_resource_users): Likewise.
 449         (in_iclass): Likewise.
 450         (lookup_specifier): Likewise.
 451         (insert_opcode_dependencies): Likewise.
 452         * mips-dis.c (parse_mips_ase_option): Likewise.
 453         (parse_mips_dis_option): Likewise.
 454         * s390-dis.c (disassemble_init_s390): Likewise.
 455         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 456
 457 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 458
 459         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 460
 461 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 462
 463         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 464         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 465
 466 2021-03-12  Alan Modra  <amodra@gmail.com>
 467
 468         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 469
 470 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-dis.c (OP_XMM): Re-order checks.
 473
 474 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-dis.c (putop): Drop need_vex check when also checking
 477         vex.evex.
 478         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 479         checking vex.b.
 480
 481 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 484         checks. Move case label past broadcast check.
 485
 486 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 487
 488         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 489         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 490         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 491         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 492         EVEX_W_0F38C7_M_0_L_2): Delete.
 493         (REG_EVEX_0F38C7_M_0_L_2): New.
 494         (intel_operand_size): Handle VEX and EVEX the same for
 495         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 496         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 497         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 498         vex_vsib_q_w_d_mode uses.
 499         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 500         0F38A1, and 0F38A3 entries.
 501         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 502         entry.
 503         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 504         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 505         0F38A3 entries.
 506
 507 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 508
 509         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 510         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 511         MOD_VEX_0FXOP_09_12): Rename to ...
 512         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 513         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 514         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 515         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 516         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 517         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 518         (reg_table): Adjust comments.
 519         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 520         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 521         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 522         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 523         (vex_len_table): Adjust opcode 0A_12 entry.
 524         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 525         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 526         (rm_table): Move hreset entry.
 527
 528 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 529
 530         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 531         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 532         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 533         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 534         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 535         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 536         (get_valid_dis386): Also handle 512-bit vector length when
 537         vectoring into vex_len_table[].
 538         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 539         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 540         entries.
 541         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 542         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 543         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 544         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 545         entries.
 546
 547 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 548
 549         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 550         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 551         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 552         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 553         entries.
 554         * i386-dis-evex-len.h (evex_len_table): Likewise.
 555         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 556
 557 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 558
 559         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 560         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 561         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 562         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 563         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 564         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 565         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 566         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 567         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 568         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 569         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 570         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 571         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 572         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 573         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 574         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 575         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 576         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 577         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 578         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 579         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 580         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 581         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 582         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 583         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 584         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 585         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 586         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 587         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 588         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 589         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 590         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 591         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 592         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 593         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 594         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 595         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 596         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 597         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 598         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 599         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 600         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 601         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 602         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 603         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 604         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 605         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 606         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 607         EVEX_W_0F3A43_L_n): New.
 608         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 609         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 610         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 611         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 612         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 613         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 614         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 615         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 616         0F385B, 0F38C6, and 0F38C7 entries.
 617         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 618         0F38C6 and 0F38C7.
 619         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 620         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 621         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 622         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 623
 624 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 625
 626         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 627         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 628         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 629         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 630         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 631         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 632         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 633         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 634         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 635         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 636         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 637         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 638         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 639         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 640         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 641         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 642         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 643         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 644         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 645         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 646         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 647         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 648         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 649         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 650         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 651         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 652         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 653         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 654         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 655         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 656         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 657         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 658         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 659         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 660         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 661         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 662         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 663         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 664         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 665         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 666         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 667         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 668         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 669         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 670         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 671         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 672         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 673         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 674         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 675         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 676         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 677         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 678         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 679         VEX_W_0F99_P_2_LEN_0): Delete.
 680         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 681         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 682         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 683         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 684         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 685         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 686         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 687         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 688         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 689         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 690         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 691         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 692         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 693         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 694         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 695         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 696         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 697         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 698         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 699         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 700         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 701         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 702         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 703         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 704         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 705         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 706         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 707         (prefix_table): No longer link to vex_len_table[] for opcodes
 708         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 709         0F92, 0F93, 0F98, and 0F99.
 710         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 711         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 712         0F98, and 0F99.
 713         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 714         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 715         0F98, and 0F99.
 716         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 717         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 718         0F98, and 0F99.
 719         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 720         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 721         0F98, and 0F99.
 722
 723 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 724
 725         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 726         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 727         REG_VEX_0F73_M_0 respectively.
 728         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 729         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 730         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 731         MOD_VEX_0F73_REG_7): Delete.
 732         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 733         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 734         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 735         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 736         PREFIX_VEX_0F3AF0_L_0 respectively.
 737         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 738         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 739         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 740         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 741         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 742         VEX_LEN_0F38F7): New.
 743         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 744         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 745         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 746         0F38F3.
 747         (prefix_table): No longer link to vex_len_table[] for opcodes
 748         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 749         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 750         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 751         0F38F6, 0F38F7, and 0F3AF0.
 752         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 753         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 754         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 755         0F73.
 756
 757 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 758
 759         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 760         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 761         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 762         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 763         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 764         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 765         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 766         73.
 767         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 768         0F72, and 0F73.
 769         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 770         0F73.
 771
 772 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 773
 774         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 775         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 776         (reg_table): Don't link to mod_table[] where not needed. Add
 777         PREFIX_IGNORED to nop entries.
 778         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 779         (mod_table): Add nop entries next to prefetch ones. Drop
 780         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 781         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 782         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 783         PREFIX_OPCODE from endbr* entries.
 784         (get_valid_dis386): Also consider entry's name when zapping
 785         vindex.
 786         (print_insn): Handle PREFIX_IGNORED.
 787
 788 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 789
 790         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 791         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 792         element.
 793         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 794         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 795         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 796         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 797         (struct i386_opcode_modifier): Delete notrackprefixok,
 798         islockable, hleprefixok, and repprefixok fields. Add prefixok
 799         field.
 800         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 801         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 802         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 803         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 804         Replace HLEPrefixOk.
 805         * opcodes/i386-tbl.h: Re-generate.
 806
 807 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 808
 809         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 810         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 811         64-bit form.
 812         * opcodes/i386-tbl.h: Re-generate.
 813
 814 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 817         for {} instead of {0}. Don't look for '0'.
 818         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 819         size specifiers.
 820
 821 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 822
 823         PR 27158
 824         * riscv-dis.c (print_insn_args): Updated encoding macros.
 825         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 826         (match_c_addi16sp): Updated encoding macros.
 827         (match_c_lui): Likewise.
 828         (match_c_lui_with_hint): Likewise.
 829         (match_c_addi4spn): Likewise.
 830         (match_c_slli): Likewise.
 831         (match_slli_as_c_slli): Likewise.
 832         (match_c_slli64): Likewise.
 833         (match_srxi_as_c_srxi): Likewise.
 834         (riscv_insn_types): Added .insn css/cl/cs.
 835
 836 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 837
 838         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 839         (default_priv_spec): Updated type to riscv_spec_class.
 840         (parse_riscv_dis_option): Updated.
 841         * riscv-opc.c: Moved stuff and make the file tidy.
 842
 843 2021-02-17  Alan Modra  <amodra@gmail.com>
 844
 845         * wasm32-dis.c: Include limits.h.
 846         (CHAR_BIT): Provide backup define.
 847         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 848         Correct signed overflow checking.
 849
 850 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 853         * i386-tbl.h: Re-generate.
 854
 855 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 856
 857         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 858         Oword.
 859         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 860
 861 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 862
 863         * s390-mkopc.c (main): Accept arch14 as cpu string.
 864         * s390-opc.txt: Add new arch14 instructions.
 865
 866 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 867
 868         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 869         favour of LIBINTL.
 870         * configure: Regenerated.
 871
 872 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 873
 874         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 875         * tic54x-opc.c (regs): Rename to ...
 876         (tic54x_regs): ... this.
 877         (mmregs): Rename to ...
 878         (tic54x_mmregs): ... this.
 879         (condition_codes): Rename to ...
 880         (tic54x_condition_codes): ... this.
 881         (cc2_codes): Rename to ...
 882         (tic54x_cc2_codes): ... this.
 883         (cc3_codes): Rename to ...
 884         (tic54x_cc3_codes): ... this.
 885         (status_bits): Rename to ...
 886         (tic54x_status_bits): ... this.
 887         (misc_symbols): Rename to ...
 888         (tic54x_misc_symbols): ... this.
 889
 890 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 891
 892         * riscv-opc.c (MASK_RVB_IMM): Removed.
 893         (riscv_opcodes): Removed zb* instructions.
 894         (riscv_ext_version_table): Removed versions for zb*.
 895
 896 2021-01-26  Alan Modra  <amodra@gmail.com>
 897
 898         * i386-gen.c (parse_template): Ensure entire template_instance
 899         is initialised.
 900
 901 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 902
 903         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 904         (riscv_fpr_names_abi): Likewise.
 905         (riscv_opcodes): Likewise.
 906         (riscv_insn_types): Likewise.
 907
 908 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 909
 910         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 911
 912 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 913
 914         * riscv-dis.c: Comments tidy and improvement.
 915         * riscv-opc.c: Likewise.
 916
 917 2021-01-13  Alan Modra  <amodra@gmail.com>
 918
 919         * Makefile.in: Regenerate.
 920
 921 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         PR binutils/26792
 924         * configure.ac: Use GNU_MAKE_JOBSERVER.
 925         * aclocal.m4: Regenerated.
 926         * configure: Likewise.
 927
 928 2021-01-12  Nick Clifton  <nickc@redhat.com>
 929
 930         * po/sr.po: Updated Serbian translation.
 931
 932 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 933
 934         PR ld/27173
 935         * configure: Regenerated.
 936
 937 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 938
 939         * aarch64-asm-2.c: Regenerate.
 940         * aarch64-dis-2.c: Likewise.
 941         * aarch64-opc-2.c: Likewise.
 942         * aarch64-opc.c (aarch64_print_operand):
 943         Delete handling of AARCH64_OPND_CSRE_CSR.
 944         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 945         (CSRE): Likewise.
 946         (_CSRE_INSN): Likewise.
 947         (aarch64_opcode_table): Delete csr.
 948
 949 2021-01-11  Nick Clifton  <nickc@redhat.com>
 950
 951         * po/de.po: Updated German translation.
 952         * po/fr.po: Updated French translation.
 953         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 954         * po/sv.po: Updated Swedish translation.
 955         * po/uk.po: Updated Ukranian translation.
 956
 957 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 958
 959         * configure: Regenerated.
 960
 961 2021-01-09  Nick Clifton  <nickc@redhat.com>
 962
 963         * configure: Regenerate.
 964         * po/opcodes.pot: Regenerate.
 965
 966 2021-01-09  Nick Clifton  <nickc@redhat.com>
 967
 968         * 2.36 release branch crated.
 969
 970 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 971
 972         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 973         (DW, (XRC_MASK): Define.
 974         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 975
 976 2021-01-09  Alan Modra  <amodra@gmail.com>
 977
 978         * configure: Regenerate.
 979
 980 2021-01-08  Nick Clifton  <nickc@redhat.com>
 981
 982         * po/sv.po: Updated Swedish translation.
 983
 984 2021-01-08  Nick Clifton  <nickc@redhat.com>
 985
 986         PR 27129
 987         * aarch64-dis.c (determine_disassembling_preference): Move call to
 988         aarch64_match_operands_constraint outside of the assertion.
 989         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 990         Replace with a return of FALSE.
 991
 992         PR 27139
 993         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 994         core system register.
 995
 996 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 997
 998         * configure: Regenerate.
 999
1000 2021-01-07  Nick Clifton  <nickc@redhat.com>
1001
1002         * po/fr.po: Updated French translation.
1003
1004 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1005
1006         * m68k-opc.c (chkl): Change minimum architecture requirement to
1007         m68020.
1008
1009 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1010
1011         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1012
1013 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1014             Jim Wilson  <jimw@sifive.com>
1015             Andrew Waterman  <andrew@sifive.com>
1016             Maxim Blinov  <maxim.blinov@embecosm.com>
1017             Kito Cheng  <kito.cheng@sifive.com>
1018             Nelson Chu  <nelson.chu@sifive.com>
1019
1020         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1021         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1022
1023 2021-01-01  Alan Modra  <amodra@gmail.com>
1024
1025         Update year range in copyright notice of all files.
1026
1027 For older changes see ChangeLog-2020
1028 \f
1029 Copyright (C) 2021 Free Software Foundation, Inc.
1030
1031 Copying and distribution of this file, with or without modification,
1032 are permitted in any medium without royalty provided the copyright
1033 notice and this notice are preserved.
1034
1035 Local Variables:
1036 mode: change-log
1037 left-margin: 8
1038 fill-column: 74
1039 version-control: never
1040 End: