1 2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
3 * mips-dis.c (set_default_mips_dis_options): Use
4 HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the
5 call to `bfd_mips_elf_get_abiflags'.
6 * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD.
7 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'.
8 * aclocal.m4: Regenerate.
9 * configure: Regenerate.
10 * config.in: Regenerate.
11 * Makefile.in: Regenerate.
13 2016-12-23 Tristan Gingold <gingold@adacore.com>
15 * configure: Regenerate.
17 2016-12-23 Tristan Gingold <gingold@adacore.com>
19 * po/opcodes.pot: Regenerate.
21 2016-12-21 Andrew Waterman <andrew@sifive.com>
23 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
25 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
27 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
28 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
29 (print_insn_mips16): Check opcode entries for validity against
30 the ISA level and ASE set selected.
32 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
34 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
35 `insn' together, with `extend' as the high-order 16 bits.
36 (match_kind): New enum.
37 (print_insn_mips16): Rework for 32-bit instruction matching.
38 Do not dump EXTEND prefixes here.
39 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
40 Recode `match' and `mask' fields as 32-bit in absolute "jal" and
43 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
45 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
46 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
49 2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
51 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
52 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
55 2016-12-20 Andrew Waterman <andrew@sifive.com>
57 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
60 2016-12-20 Andrew Waterman <andrew@sifive.com>
62 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
65 2016-12-20 Andrew Waterman <andrew@sifive.com>
67 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
70 2016-12-20 Andrew Waterman <andrew@sifive.com>
72 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
73 XLEN when none is provided.
75 2016-12-20 Andrew Waterman <andrew@sifive.com>
77 * riscv-opc.c: Formatting fixes.
79 2016-12-20 Alan Modra <amodra@gmail.com>
81 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
82 * Makefile.in: Regenerate.
83 * po/POTFILES.in: Regenerate.
85 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
87 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
88 Only examine ELF file structures here.
90 2016-12-19 Maciej W. Rozycki <macro@imgtec.com>
92 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
93 `bfd_mips_elf_get_abiflags' here.
95 2016-12-16 Nick Clifton <nickc@redhat.com>
97 * arm-dis.c (print_insn_thumb32): Fix compile time warning
98 computing value_in_comment.
100 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
102 * mips-dis.c (mips_convert_abiflags_ases): New function.
103 (set_default_mips_dis_options): Also infer ASE flags from ELF
106 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
108 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file
109 header flag interpretation code.
111 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
113 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in
114 `pinfo2' with SP-relative "sd" entries.
116 2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
118 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
121 2016-12-13 Renlin Li <renlin.li@arm.com>
123 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
125 (operand_general_constraint_met_p): Remove case for CP_REG.
126 (aarch64_print_operand): Print CRn, CRm operand using imm field.
127 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
129 (aarch64_opcode_table): Change CRn, CRm operand class and type.
130 * aarch64-opc-2.c : Regenerate.
131 * aarch64-asm-2.c : Likewise.
132 * aarch64-dis-2.c : Likewise.
134 2016-12-12 Yao Qi <yao.qi@linaro.org>
136 * rx-dis.c: Include <setjmp.h>
137 (struct private): New.
138 (rx_get_byte): Check return value of read_memory_func, and
139 call memory_error_func and OPCODES_SIGLONGJMP on error.
140 (print_insn_rx): Call OPCODES_SIGSETJMP.
142 2016-12-12 Yao Qi <yao.qi@linaro.org>
144 * rl78-dis.c: Include <setjmp.h>.
145 (struct private): New.
146 (rl78_get_byte): Check return value of read_memory_func, and
147 call memory_error_func and OPCODES_SIGLONGJMP on error.
148 (print_insn_rl78_common): Call OPCODES_SIGJMP.
150 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
152 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
154 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
156 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
159 2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
161 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
162 to separate `extend' and its uninterpreted argument output.
163 Separate hexadecimal halves of undecoded extended instructions
166 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
168 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
169 indentation space across.
171 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
173 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
174 adjustment for PC-relative operations following MIPS16e compact
175 jumps or undefined RR/J(AL)R(C) encodings.
177 2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
179 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
180 variable to `reglane_index'.
182 2016-12-08 Luis Machado <lgustavo@codesourcery.com>
184 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
186 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
188 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
190 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
192 * mips16-opc.c (mips16_opcodes): Update comment naming structure
195 2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
197 * mips-dis.c (print_mips_disassembler_options): Reformat output.
199 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
201 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
202 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
204 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
206 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
208 2016-12-01 Nick Clifton <nickc@redhat.com>
211 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
214 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
216 * arc-opc.c (insert_ra_chk): New function.
217 (insert_rb_chk): Likewise.
218 (insert_rad): Update text error message.
219 (insert_rcd): Likewise.
220 (insert_rhv2): Likewise.
221 (insert_r0): Likewise.
222 (insert_r1): Likewise.
223 (insert_r2): Likewise.
224 (insert_r3): Likewise.
225 (insert_sp): Likewise.
226 (insert_gp): Likewise.
227 (insert_pcl): Likewise.
228 (insert_blink): Likewise.
229 (insert_ilink1): Likewise.
230 (insert_ilink2): Likewise.
231 (insert_ras): Likewise.
232 (insert_rbs): Likewise.
233 (insert_rcs): Likewise.
234 (insert_simm3s): Likewise.
235 (insert_rrange): Likewise.
236 (insert_fpel): Likewise.
237 (insert_blinkel): Likewise.
238 (insert_pcel): Likewise.
239 (insert_nps_3bit_dst): Likewise.
240 (insert_nps_3bit_dst_short): Likewise.
241 (insert_nps_3bit_src2_short): Likewise.
242 (insert_nps_bitop_size_2b): Likewise.
243 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
248 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
249 * arc-tbl.h (div, divu): All instructions are DIVREM class.
250 Change first insn argument to check for LP_COUNT usage.
252 (ld, ldd): All instructions are LOAD class. Change first insn
253 argument to check for LP_COUNT usage.
254 (st, std): All instructions are STORE class.
255 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
256 Change first insn argument to check for LP_COUNT usage.
257 (mov): All instructions are MOVE class. Change first insn
258 argument to check for LP_COUNT usage.
260 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
262 * arc-dis.c (is_compatible_p): Remove function.
263 (skip_this_opcode): Don't add any decoding class to decode list.
265 (find_format_from_table): Go through all opcodes, and warn if we
266 use a guessed mnemonic.
268 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
269 Amit Pawar <amit.pawar@amd.com>
272 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
275 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
277 * configure: Regenerate.
279 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
281 * sparc-opc.c (HWS_V8): Definition moved from
282 gas/config/tc-sparc.c.
292 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
295 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
297 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
300 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
302 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
303 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
304 (aarch64_opcode_table): Add fcmla and fcadd.
305 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
306 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
307 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
308 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
309 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
310 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
311 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
312 (operand_general_constraint_met_p): Rotate and index range check.
313 (aarch64_print_operand): Handle rotate operand.
314 * aarch64-asm-2.c: Regenerate.
315 * aarch64-dis-2.c: Likewise.
316 * aarch64-opc-2.c: Likewise.
318 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
320 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
321 * aarch64-asm-2.c: Regenerate.
322 * aarch64-dis-2.c: Regenerate.
323 * aarch64-opc-2.c: Regenerate.
325 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
327 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
328 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
329 * aarch64-asm-2.c: Regenerate.
330 * aarch64-dis-2.c: Regenerate.
331 * aarch64-opc-2.c: Regenerate.
333 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
335 * aarch64-tbl.h (QL_X1NIL): New.
336 (arch64_opcode_table): Add ldraa, ldrab.
337 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
338 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
339 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
340 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
341 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
342 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
343 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
344 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
345 (aarch64_print_operand): Likewise.
346 * aarch64-asm-2.c: Regenerate.
347 * aarch64-dis-2.c: Regenerate.
348 * aarch64-opc-2.c: Regenerate.
350 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
352 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
353 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
354 * aarch64-asm-2.c: Regenerate.
355 * aarch64-dis-2.c: Regenerate.
356 * aarch64-opc-2.c: Regenerate.
358 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
360 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
361 (AARCH64_OPERANDS): Add Rm_SP.
362 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
363 * aarch64-asm-2.c: Regenerate.
364 * aarch64-dis-2.c: Regenerate.
365 * aarch64-opc-2.c: Regenerate.
367 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
369 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
370 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
371 autdzb, xpaci, xpacd.
372 * aarch64-asm-2.c: Regenerate.
373 * aarch64-dis-2.c: Regenerate.
374 * aarch64-opc-2.c: Regenerate.
376 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
378 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
379 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
380 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
381 (aarch64_sys_reg_supported_p): Add feature test for new registers.
383 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
385 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
386 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
387 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
389 * aarch64-asm-2.c: Regenerate.
390 * aarch64-dis-2.c: Regenerate.
392 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
394 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
396 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
399 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
400 * i386-dis.c (EdqwS): Removed.
401 (dqw_swap_mode): Likewise.
402 (intel_operand_size): Don't check dqw_swap_mode.
403 (OP_E_register): Likewise.
404 (OP_E_memory): Likewise.
407 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
408 * i386-tbl.h: Regerated.
410 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
412 * i386-opc.tbl: Merge AVX512F vmovq.
413 * i386-tbl.h: Regerated.
415 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
418 * i386-dis.c (THREE_BYTE_0F7A): Removed.
419 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
420 (three_byte_table): Remove THREE_BYTE_0F7A.
422 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
425 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
426 (FGRPd9_4): Replace 1 with 2.
427 (FGRPd9_5): Replace 2 with 3.
428 (FGRPd9_6): Replace 3 with 4.
429 (FGRPd9_7): Replace 4 with 5.
430 (FGRPda_5): Replace 5 with 6.
431 (FGRPdb_4): Replace 6 with 7.
432 (FGRPde_3): Replace 7 with 8.
433 (FGRPdf_4): Replace 8 with 9.
434 (fgrps): Add an entry for Bad_Opcode.
436 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
438 * arc-opc.c (arc_flag_operands): Add F_DI14.
439 (arc_flag_classes): Add C_DI14.
440 * arc-nps400-tbl.h: Add new exc instructions.
442 2016-11-03 Graham Markall <graham.markall@embecosm.com>
444 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
446 * arc-nps-400-tbl.h: Add dcmac instruction.
447 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
448 (insert_nps_rbdouble_64): Added.
449 (extract_nps_rbdouble_64): Added.
450 (insert_nps_proto_size): Added.
451 (extract_nps_proto_size): Added.
453 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
455 * arc-dis.c (struct arc_operand_iterator): Remove all fields
456 relating to long instruction processing, add new limm field.
457 (OPCODE): Rename to...
458 (OPCODE_32BIT_INSN): ...this.
460 (skip_this_opcode): Handle different instruction lengths, update
462 (special_flag_p): Update parameter type.
463 (find_format_from_table): Update for more instruction lengths.
464 (find_format_long_instructions): Delete.
465 (find_format): Update for more instruction lengths.
466 (arc_insn_length): Likewise.
467 (extract_operand_value): Update for more instruction lengths.
468 (operand_iterator_next): Remove code relating to long
470 (arc_opcode_to_insn_type): New function.
471 (print_insn_arc):Update for more instructions lengths.
472 * arc-ext.c (extInstruction_t): Change argument type.
473 * arc-ext.h (extInstruction_t): Change argument type.
474 * arc-fxi.h: Change type unsigned to unsigned long long
475 extensively throughout.
476 * arc-nps400-tbl.h: Add long instructions taken from
477 arc_long_opcodes table in arc-opc.c.
478 * arc-opc.c: Update parameter types on insert/extract handlers.
479 (arc_long_opcodes): Delete.
480 (arc_num_long_opcodes): Delete.
481 (arc_opcode_len): Update for more instruction lengths.
483 2016-11-03 Graham Markall <graham.markall@embecosm.com>
485 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
487 2016-11-03 Graham Markall <graham.markall@embecosm.com>
489 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
491 (find_format_long_instructions): Likewise.
492 * arc-opc.c (arc_opcode_len): New function.
494 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
496 * arc-nps400-tbl.h: Fix some instruction masks.
498 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
500 * i386-dis.c (REG_82): Removed.
501 (X86_64_82_REG_0): Likewise.
502 (X86_64_82_REG_1): Likewise.
503 (X86_64_82_REG_2): Likewise.
504 (X86_64_82_REG_3): Likewise.
505 (X86_64_82_REG_4): Likewise.
506 (X86_64_82_REG_5): Likewise.
507 (X86_64_82_REG_6): Likewise.
508 (X86_64_82_REG_7): Likewise.
510 (dis386): Use X86_64_82 instead of REG_82.
511 (reg_table): Remove REG_82.
512 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
513 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
514 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
517 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
520 * i386-dis.c (REG_82): New.
521 (X86_64_82_REG_0): Likewise.
522 (X86_64_82_REG_1): Likewise.
523 (X86_64_82_REG_2): Likewise.
524 (X86_64_82_REG_3): Likewise.
525 (X86_64_82_REG_4): Likewise.
526 (X86_64_82_REG_5): Likewise.
527 (X86_64_82_REG_6): Likewise.
528 (X86_64_82_REG_7): Likewise.
529 (dis386): Use REG_82.
530 (reg_table): Add REG_82.
531 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
532 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
533 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
535 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
537 * i386-dis.c (REG_82): Renamed to ...
540 (reg_table): Likewise.
542 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
544 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
545 * i386-dis-evex.h (evex_table): Updated.
546 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
547 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
548 (cpu_flags): Add CpuAVX512_4VNNIW.
549 * i386-opc.h (enum): (AVX512_4VNNIW): New.
550 (i386_cpu_flags): Add cpuavx512_4vnniw.
551 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
552 * i386-init.h: Regenerate.
555 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
557 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
558 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
559 * i386-dis-evex.h (evex_table): Updated.
560 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
561 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
562 (cpu_flags): Add CpuAVX512_4FMAPS.
563 (opcode_modifiers): Add ImplicitQuadGroup modifier.
564 * i386-opc.h (AVX512_4FMAP): New.
565 (i386_cpu_flags): Add cpuavx512_4fmaps.
566 (ImplicitQuadGroup): New.
567 (i386_opcode_modifier): Add implicitquadgroup.
568 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
569 * i386-init.h: Regenerate.
572 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
573 Andrew Waterman <andrew@sifive.com>
575 Add support for RISC-V architecture.
576 * configure.ac: Add entry for bfd_riscv_arch.
577 * configure: Regenerate.
578 * disassemble.c (disassembler): Add support for riscv.
579 (disassembler_usage): Likewise.
580 * riscv-dis.c: New file.
581 * riscv-opc.c: New file.
583 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
585 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
586 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
587 (rm_table): Update the RM_0FAE_REG_7 entry.
588 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
589 (cpu_flags): Remove CpuPCOMMIT.
590 * i386-opc.h (CpuPCOMMIT): Removed.
591 (i386_cpu_flags): Remove cpupcommit.
592 * i386-opc.tbl: Remove pcommit.
593 * i386-init.h: Regenerated.
594 * i386-tbl.h: Likewise.
596 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
599 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
600 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
601 32-bit mode. Don't check vex.register_specifier in 32-bit
603 (OP_VEX): Check for invalid mask registers.
605 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
608 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
611 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
614 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
616 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
618 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
619 local variable to `index_regno'.
621 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
623 * arc-tbl.h: Removed any "inv.+" instructions from the table.
625 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
627 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
630 2016-10-11 Jiong Wang <jiong.wang@arm.com>
633 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
635 2016-10-07 Jiong Wang <jiong.wang@arm.com>
638 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
641 2016-10-07 Alan Modra <amodra@gmail.com>
643 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
645 2016-10-06 Alan Modra <amodra@gmail.com>
647 * aarch64-opc.c: Spell fall through comments consistently.
648 * i386-dis.c: Likewise.
649 * aarch64-dis.c: Add missing fall through comments.
650 * aarch64-opc.c: Likewise.
651 * arc-dis.c: Likewise.
652 * arm-dis.c: Likewise.
653 * i386-dis.c: Likewise.
654 * m68k-dis.c: Likewise.
655 * mep-asm.c: Likewise.
656 * ns32k-dis.c: Likewise.
657 * sh-dis.c: Likewise.
658 * tic4x-dis.c: Likewise.
659 * tic6x-dis.c: Likewise.
660 * vax-dis.c: Likewise.
662 2016-10-06 Alan Modra <amodra@gmail.com>
664 * arc-ext.c (create_map): Add missing break.
665 * msp430-decode.opc (encode_as): Likewise.
666 * msp430-decode.c: Regenerate.
668 2016-10-06 Alan Modra <amodra@gmail.com>
670 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
671 * crx-dis.c (print_insn_crx): Likewise.
673 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
676 * i386-dis.c (putop): Don't assign alt twice.
678 2016-09-29 Jiong Wang <jiong.wang@arm.com>
681 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
683 2016-09-29 Alan Modra <amodra@gmail.com>
685 * ppc-opc.c (L): Make compulsory.
686 (LOPT): New, optional form of L.
687 (HTM_R): Define as LOPT.
689 (L32OPT): New, optional for 32-bit L.
690 (L2OPT): New, 2-bit L for dcbf.
693 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
694 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
696 <tlbiel, tlbie>: Use LOPT.
697 <wclr, wclrall>: Use L2.
699 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
701 * Makefile.in: Regenerate.
702 * configure: Likewise.
704 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
706 * arc-ext-tbl.h (EXTINSN2OPF): Define.
707 (EXTINSN2OP): Use EXTINSN2OPF.
708 (bspeekm, bspop, modapp): New extension instructions.
709 * arc-opc.c (F_DNZ_ND): Define.
714 * arc-tbl.h (dbnz): New instruction.
715 (prealloc): Allow it for ARC EM.
718 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
720 * aarch64-opc.c (print_immediate_offset_address): Print spaces
721 after commas in addresses.
722 (aarch64_print_operand): Likewise.
724 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
726 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
727 rather than "should be" or "expected to be" in error messages.
729 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
731 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
732 (print_mnemonic_name): ...here.
733 (print_comment): New function.
734 (print_aarch64_insn): Call it.
735 * aarch64-opc.c (aarch64_conds): Add SVE names.
736 (aarch64_print_operand): Print alternative condition names in
739 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
741 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
742 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
743 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
744 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
745 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
746 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
747 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
748 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
749 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
750 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
751 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
752 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
753 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
754 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
755 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
756 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
757 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
758 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
759 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
760 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
761 (OP_SVE_XWU, OP_SVE_XXU): New macros.
762 (aarch64_feature_sve): New variable.
764 (_SVE_INSN): Likewise.
765 (aarch64_opcode_table): Add SVE instructions.
766 * aarch64-opc.h (extract_fields): Declare.
767 * aarch64-opc-2.c: Regenerate.
768 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
769 * aarch64-asm-2.c: Regenerate.
770 * aarch64-dis.c (extract_fields): Make global.
771 (do_misc_decoding): Handle the new SVE aarch64_ops.
772 * aarch64-dis-2.c: Regenerate.
774 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
776 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
777 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
779 * aarch64-opc.c (fields): Add corresponding entries.
780 * aarch64-asm.c (aarch64_get_variant): New function.
781 (aarch64_encode_variant_using_iclass): Likewise.
782 (aarch64_opcode_encode): Call it.
783 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
784 (aarch64_opcode_decode): Call it.
786 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
788 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
789 and FP register operands.
790 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
791 (FLD_SVE_Vn): New aarch64_field_kinds.
792 * aarch64-opc.c (fields): Add corresponding entries.
793 (aarch64_print_operand): Handle the new SVE core and FP register
795 * aarch64-opc-2.c: Regenerate.
796 * aarch64-asm-2.c: Likewise.
797 * aarch64-dis-2.c: Likewise.
799 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
801 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
803 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
804 * aarch64-opc.c (fields): Add corresponding entry.
805 (operand_general_constraint_met_p): Handle the new SVE FP immediate
807 (aarch64_print_operand): Likewise.
808 * aarch64-opc-2.c: Regenerate.
809 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
810 (ins_sve_float_zero_one): New inserters.
811 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
812 (aarch64_ins_sve_float_half_two): Likewise.
813 (aarch64_ins_sve_float_zero_one): Likewise.
814 * aarch64-asm-2.c: Regenerate.
815 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
816 (ext_sve_float_zero_one): New extractors.
817 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
818 (aarch64_ext_sve_float_half_two): Likewise.
819 (aarch64_ext_sve_float_zero_one): Likewise.
820 * aarch64-dis-2.c: Regenerate.
822 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
824 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
825 integer immediate operands.
826 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
827 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
828 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
829 * aarch64-opc.c (fields): Add corresponding entries.
830 (operand_general_constraint_met_p): Handle the new SVE integer
832 (aarch64_print_operand): Likewise.
833 (aarch64_sve_dupm_mov_immediate_p): New function.
834 * aarch64-opc-2.c: Regenerate.
835 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
836 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
837 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
838 (aarch64_ins_limm): ...here.
839 (aarch64_ins_inv_limm): New function.
840 (aarch64_ins_sve_aimm): Likewise.
841 (aarch64_ins_sve_asimm): Likewise.
842 (aarch64_ins_sve_limm_mov): Likewise.
843 (aarch64_ins_sve_shlimm): Likewise.
844 (aarch64_ins_sve_shrimm): Likewise.
845 * aarch64-asm-2.c: Regenerate.
846 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
847 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
848 * aarch64-dis.c (decode_limm): New function, split out from...
849 (aarch64_ext_limm): ...here.
850 (aarch64_ext_inv_limm): New function.
851 (decode_sve_aimm): Likewise.
852 (aarch64_ext_sve_aimm): Likewise.
853 (aarch64_ext_sve_asimm): Likewise.
854 (aarch64_ext_sve_limm_mov): Likewise.
855 (aarch64_top_bit): Likewise.
856 (aarch64_ext_sve_shlimm): Likewise.
857 (aarch64_ext_sve_shrimm): Likewise.
858 * aarch64-dis-2.c: Regenerate.
860 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
862 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
864 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
865 the AARCH64_MOD_MUL_VL entry.
866 (value_aligned_p): Cope with non-power-of-two alignments.
867 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
868 (print_immediate_offset_address): Likewise.
869 (aarch64_print_operand): Likewise.
870 * aarch64-opc-2.c: Regenerate.
871 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
872 (ins_sve_addr_ri_s9xvl): New inserters.
873 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
874 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
875 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
876 * aarch64-asm-2.c: Regenerate.
877 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
878 (ext_sve_addr_ri_s9xvl): New extractors.
879 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
880 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
881 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
882 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
883 * aarch64-dis-2.c: Regenerate.
885 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
887 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
889 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
890 (FLD_SVE_xs_22): New aarch64_field_kinds.
891 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
892 (get_operand_specific_data): New function.
893 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
894 FLD_SVE_xs_14 and FLD_SVE_xs_22.
895 (operand_general_constraint_met_p): Handle the new SVE address
897 (sve_reg): New array.
898 (get_addr_sve_reg_name): New function.
899 (aarch64_print_operand): Handle the new SVE address operands.
900 * aarch64-opc-2.c: Regenerate.
901 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
902 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
903 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
904 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
905 (aarch64_ins_sve_addr_rr_lsl): Likewise.
906 (aarch64_ins_sve_addr_rz_xtw): Likewise.
907 (aarch64_ins_sve_addr_zi_u5): Likewise.
908 (aarch64_ins_sve_addr_zz): Likewise.
909 (aarch64_ins_sve_addr_zz_lsl): Likewise.
910 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
911 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
912 * aarch64-asm-2.c: Regenerate.
913 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
914 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
915 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
916 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
917 (aarch64_ext_sve_addr_ri_u6): Likewise.
918 (aarch64_ext_sve_addr_rr_lsl): Likewise.
919 (aarch64_ext_sve_addr_rz_xtw): Likewise.
920 (aarch64_ext_sve_addr_zi_u5): Likewise.
921 (aarch64_ext_sve_addr_zz): Likewise.
922 (aarch64_ext_sve_addr_zz_lsl): Likewise.
923 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
924 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
925 * aarch64-dis-2.c: Regenerate.
927 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
929 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
930 AARCH64_OPND_SVE_PATTERN_SCALED.
931 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
932 * aarch64-opc.c (fields): Add a corresponding entry.
933 (set_multiplier_out_of_range_error): New function.
934 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
935 (operand_general_constraint_met_p): Handle
936 AARCH64_OPND_SVE_PATTERN_SCALED.
937 (print_register_offset_address): Use PRIi64 to print the
939 (aarch64_print_operand): Likewise. Handle
940 AARCH64_OPND_SVE_PATTERN_SCALED.
941 * aarch64-opc-2.c: Regenerate.
942 * aarch64-asm.h (ins_sve_scale): New inserter.
943 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
944 * aarch64-asm-2.c: Regenerate.
945 * aarch64-dis.h (ext_sve_scale): New inserter.
946 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
947 * aarch64-dis-2.c: Regenerate.
949 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
951 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
952 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
953 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
954 (FLD_SVE_prfop): Likewise.
955 * aarch64-opc.c: Include libiberty.h.
956 (aarch64_sve_pattern_array): New variable.
957 (aarch64_sve_prfop_array): Likewise.
958 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
959 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
960 AARCH64_OPND_SVE_PRFOP.
961 * aarch64-asm-2.c: Regenerate.
962 * aarch64-dis-2.c: Likewise.
963 * aarch64-opc-2.c: Likewise.
965 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
967 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
968 AARCH64_OPND_QLF_P_[ZM].
969 (aarch64_print_operand): Print /z and /m where appropriate.
971 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
973 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
974 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
975 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
976 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
977 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
978 * aarch64-opc.c (fields): Add corresponding entries here.
979 (operand_general_constraint_met_p): Check that SVE register lists
980 have the correct length. Check the ranges of SVE index registers.
981 Check for cases where p8-p15 are used in 3-bit predicate fields.
982 (aarch64_print_operand): Handle the new SVE operands.
983 * aarch64-opc-2.c: Regenerate.
984 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
985 * aarch64-asm.c (aarch64_ins_sve_index): New function.
986 (aarch64_ins_sve_reglist): Likewise.
987 * aarch64-asm-2.c: Regenerate.
988 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
989 * aarch64-dis.c (aarch64_ext_sve_index): New function.
990 (aarch64_ext_sve_reglist): Likewise.
991 * aarch64-dis-2.c: Regenerate.
993 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
995 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
996 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
997 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
998 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
1001 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1003 * aarch64-opc.c (get_offset_int_reg_name): New function.
1004 (print_immediate_offset_address): Likewise.
1005 (print_register_offset_address): Take the base and offset
1006 registers as parameters.
1007 (aarch64_print_operand): Update caller accordingly. Use
1008 print_immediate_offset_address.
1010 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1012 * aarch64-opc.c (BANK): New macro.
1013 (R32, R64): Take a register number as argument
1014 (int_reg): Use BANK.
1016 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1018 * aarch64-opc.c (print_register_list): Add a prefix parameter.
1019 (aarch64_print_operand): Update accordingly.
1021 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1023 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
1025 * aarch64-asm.h (ins_fpimm): New inserter.
1026 * aarch64-asm.c (aarch64_ins_fpimm): New function.
1027 * aarch64-asm-2.c: Regenerate.
1028 * aarch64-dis.h (ext_fpimm): New extractor.
1029 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
1030 (aarch64_ext_fpimm): New function.
1031 * aarch64-dis-2.c: Regenerate.
1033 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1035 * aarch64-asm.c: Include libiberty.h.
1036 (insert_fields): New function.
1037 (aarch64_ins_imm): Use it.
1038 * aarch64-dis.c (extract_fields): New function.
1039 (aarch64_ext_imm): Use it.
1041 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1043 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
1044 with an esize parameter.
1045 (operand_general_constraint_met_p): Update accordingly.
1046 Fix misindented code.
1047 * aarch64-asm.c (aarch64_ins_limm): Update call to
1048 aarch64_logical_immediate_p.
1050 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1052 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
1054 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
1056 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
1058 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
1060 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
1062 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
1064 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
1065 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
1066 xor3>: Delete mnemonics.
1067 <cp_abort>: Rename mnemonic from ...
1068 <cpabort>: ...to this.
1069 <setb>: Change to a X form instruction.
1070 <sync>: Change to 1 operand form.
1071 <copy>: Delete mnemonic.
1072 <copy_first>: Rename mnemonic from ...
1074 <paste, paste.>: Delete mnemonics.
1075 <paste_last>: Rename mnemonic from ...
1076 <paste.>: ...to this.
1078 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
1080 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
1082 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1084 * s390-mkopc.c (main): Support alternate arch strings.
1086 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
1088 * s390-opc.txt: Fix kmctr instruction type.
1090 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
1092 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
1093 * i386-init.h: Regenerated.
1095 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
1097 * opcodes/arc-dis.c (print_insn_arc): Changed.
1099 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
1101 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
1104 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
1106 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
1107 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
1108 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
1110 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
1112 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
1113 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
1114 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
1115 PREFIX_MOD_3_0FAE_REG_4.
1116 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
1117 PREFIX_MOD_3_0FAE_REG_4.
1118 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
1119 (cpu_flags): Add CpuPTWRITE.
1120 * i386-opc.h (CpuPTWRITE): New.
1121 (i386_cpu_flags): Add cpuptwrite.
1122 * i386-opc.tbl: Add ptwrite instruction.
1123 * i386-init.h: Regenerated.
1124 * i386-tbl.h: Likewise.
1126 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1128 * arc-dis.h: Wrap around in extern "C".
1130 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1132 * aarch64-tbl.h (V8_2_INSN): New macro.
1133 (aarch64_opcode_table): Use it.
1135 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1137 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1138 CORE_INSN, __FP_INSN and SIMD_INSN.
1140 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1142 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1143 (aarch64_opcode_table): Update uses accordingly.
1145 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
1146 Kwok Cheung Yeung <kcy@codesourcery.com>
1149 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1150 'e_cmplwi' to 'e_cmpli' instead.
1151 (OPVUPRT, OPVUPRT_MASK): Define.
1152 (powerpc_opcodes): Add E200Z4 insns.
1153 (vle_opcodes): Add context save/restore insns.
1155 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1157 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1158 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1161 2016-07-27 Graham Markall <graham.markall@embecosm.com>
1163 * arc-nps400-tbl.h: Change block comments to GNU format.
1164 * arc-dis.c: Add new globals addrtypenames,
1165 addrtypenames_max, and addtypeunknown.
1166 (get_addrtype): New function.
1167 (print_insn_arc): Print colons and address types when
1169 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1170 define insert and extract functions for all address types.
1171 (arc_operands): Add operands for colon and all address
1173 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1174 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1175 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1176 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1177 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1178 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1180 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1182 * configure: Regenerated.
1184 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1186 * arc-dis.c (skipclass): New structure.
1187 (decodelist): New variable.
1188 (is_compatible_p): New function.
1189 (new_element): Likewise.
1190 (skip_class_p): Likewise.
1191 (find_format_from_table): Use skip_class_p function.
1192 (find_format): Decode first the extension instructions.
1193 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1195 (parse_option): New function.
1196 (parse_disassembler_options): Likewise.
1197 (print_arc_disassembler_options): Likewise.
1198 (print_insn_arc): Use parse_disassembler_options function. Proper
1199 select ARCv2 cpu variant.
1200 * disassemble.c (disassembler_usage): Add ARC disassembler
1203 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1205 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1206 annotation from the "nal" entry and reorder it beyond "bltzal".
1208 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1210 * sparc-opc.c (ldtxa): New macro.
1211 (sparc_opcodes): Use the macro defined above to add entries for
1212 the LDTXA instructions.
1213 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1216 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1218 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1221 2016-07-01 Jan Beulich <jbeulich@suse.com>
1223 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1224 (movzb): Adjust to cover all permitted suffixes.
1226 * i386-tbl.h: Re-generate.
1228 2016-07-01 Jan Beulich <jbeulich@suse.com>
1230 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1231 (lgdt): Remove Tbyte from non-64-bit variant.
1232 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1233 xsaves64, xsavec64): Remove Disp16.
1234 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1235 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1237 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1238 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1239 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1241 * i386-tbl.h: Re-generate.
1243 2016-07-01 Jan Beulich <jbeulich@suse.com>
1245 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1246 * i386-tbl.h: Re-generate.
1248 2016-06-30 Yao Qi <yao.qi@linaro.org>
1250 * arm-dis.c (print_insn): Fix typo in comment.
1252 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1254 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1255 range of ldst_elemlist operands.
1256 (print_register_list): Use PRIi64 to print the index.
1257 (aarch64_print_operand): Likewise.
1259 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1261 * mcore-opc.h: Remove sentinal.
1262 * mcore-dis.c (print_insn_mcore): Adjust.
1264 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1266 * arc-opc.c: Correct description of availability of NPS400
1269 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1271 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1272 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1273 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1274 xor3>: New mnemonics.
1275 <setb>: Change to a VX form instruction.
1276 (insert_sh6): Add support for rldixor.
1277 (extract_sh6): Likewise.
1279 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1281 * arc-ext.h: Wrap in extern C.
1283 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1285 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1286 Use same method for determining instruction length on ARC700 and
1288 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1289 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1290 with the NPS400 subclass.
1291 * arc-opc.c: Likewise.
1293 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1295 * sparc-opc.c (rdasr): New macro.
1301 (sparc_opcodes): Use the macros above to fix and expand the
1302 definition of read/write instructions from/to
1303 asr/privileged/hyperprivileged instructions.
1304 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1305 %hva_mask_nz. Prefer softint_set and softint_clear over
1306 set_softint and clear_softint.
1307 (print_insn_sparc): Support %ver in Rd.
1309 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1311 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1312 architecture according to the hardware capabilities they require.
1314 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1316 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1317 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1318 bfd_mach_sparc_v9{c,d,e,v,m}.
1319 * sparc-opc.c (MASK_V9C): Define.
1320 (MASK_V9D): Likewise.
1321 (MASK_V9E): Likewise.
1322 (MASK_V9V): Likewise.
1323 (MASK_V9M): Likewise.
1324 (v6): Add MASK_V9{C,D,E,V,M}.
1325 (v6notlet): Likewise.
1329 (v9andleon): Likewise.
1337 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1339 2016-06-15 Nick Clifton <nickc@redhat.com>
1341 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1342 constants to match expected behaviour.
1343 (nds32_parse_opcode): Likewise. Also for whitespace.
1345 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1347 * arc-opc.c (extract_rhv1): Extract value from insn.
1349 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1351 * arc-nps400-tbl.h: Add ldbit instruction.
1352 * arc-opc.c: Add flag classes required for ldbit.
1354 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1356 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1357 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1358 support the above instructions.
1360 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1362 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1363 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1364 csma, cbba, zncv, and hofs.
1365 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1366 support the above instructions.
1368 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1370 * arc-nps400-tbl.h: Add andab and orab instructions.
1372 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1374 * arc-nps400-tbl.h: Add addl-like instructions.
1376 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1378 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1380 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1382 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1385 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1387 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1389 (init_disasm): Handle new command line option "insnlength".
1390 (print_s390_disassembler_options): Mention new option in help
1392 (print_insn_s390): Use the encoded insn length when dumping
1393 unknown instructions.
1395 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1397 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1398 to the address and set as symbol address for LDS/ STS immediate operands.
1400 2016-06-07 Alan Modra <amodra@gmail.com>
1402 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1403 cpu for "vle" to e500.
1404 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1405 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1406 (PPCNONE): Delete, substitute throughout.
1407 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1408 except for major opcode 4 and 31.
1409 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1411 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1413 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1414 ARM_EXT_RAS in relevant entries.
1416 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1419 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1422 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1425 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1426 (indir_v_mode): New.
1427 Add comments for '&'.
1428 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1429 (putop): Handle '&'.
1430 (intel_operand_size): Handle indir_v_mode.
1431 (OP_E_register): Likewise.
1432 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1433 64-bit indirect call/jmp for AMD64.
1434 * i386-tbl.h: Regenerated
1436 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1438 * arc-dis.c (struct arc_operand_iterator): New structure.
1439 (find_format_from_table): All the old content from find_format,
1440 with some minor adjustments, and parameter renaming.
1441 (find_format_long_instructions): New function.
1442 (find_format): Rewritten.
1443 (arc_insn_length): Add LSB parameter.
1444 (extract_operand_value): New function.
1445 (operand_iterator_next): New function.
1446 (print_insn_arc): Use new functions to find opcode, and iterator
1448 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1449 (extract_nps_3bit_dst_short): New function.
1450 (insert_nps_3bit_src2_short): New function.
1451 (extract_nps_3bit_src2_short): New function.
1452 (insert_nps_bitop1_size): New function.
1453 (extract_nps_bitop1_size): New function.
1454 (insert_nps_bitop2_size): New function.
1455 (extract_nps_bitop2_size): New function.
1456 (insert_nps_bitop_mod4_msb): New function.
1457 (extract_nps_bitop_mod4_msb): New function.
1458 (insert_nps_bitop_mod4_lsb): New function.
1459 (extract_nps_bitop_mod4_lsb): New function.
1460 (insert_nps_bitop_dst_pos3_pos4): New function.
1461 (extract_nps_bitop_dst_pos3_pos4): New function.
1462 (insert_nps_bitop_ins_ext): New function.
1463 (extract_nps_bitop_ins_ext): New function.
1464 (arc_operands): Add new operands.
1465 (arc_long_opcodes): New global array.
1466 (arc_num_long_opcodes): New global.
1467 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1469 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1471 * nds32-asm.h: Add extern "C".
1472 * sh-opc.h: Likewise.
1474 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1476 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1477 0,b,limm to the rflt instruction.
1479 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1481 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1484 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1487 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1488 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1489 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1490 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1491 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1492 * i386-init.h: Regenerated.
1494 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1497 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1498 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1499 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1500 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1501 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1502 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1503 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1504 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1505 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1506 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1507 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1508 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1509 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1510 CpuRegMask for AVX512.
1511 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1513 (set_bitfield_from_cpu_flag_init): New function.
1514 (set_bitfield): Remove const on f. Call
1515 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1516 * i386-opc.h (CpuRegMMX): New.
1517 (CpuRegXMM): Likewise.
1518 (CpuRegYMM): Likewise.
1519 (CpuRegZMM): Likewise.
1520 (CpuRegMask): Likewise.
1521 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1523 * i386-init.h: Regenerated.
1524 * i386-tbl.h: Likewise.
1526 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1529 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1530 (opcode_modifiers): Add AMD64 and Intel64.
1531 (main): Properly verify CpuMax.
1532 * i386-opc.h (CpuAMD64): Removed.
1533 (CpuIntel64): Likewise.
1534 (CpuMax): Set to CpuNo64.
1535 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1537 (Intel64): Likewise.
1538 (i386_opcode_modifier): Add amd64 and intel64.
1539 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1541 * i386-init.h: Regenerated.
1542 * i386-tbl.h: Likewise.
1544 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1547 * i386-gen.c (main): Fail if CpuMax is incorrect.
1548 * i386-opc.h (CpuMax): Set to CpuIntel64.
1549 * i386-tbl.h: Regenerated.
1551 2016-05-27 Nick Clifton <nickc@redhat.com>
1554 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1555 (msp430dis_opcode_unsigned): New function.
1556 (msp430dis_opcode_signed): New function.
1557 (msp430_singleoperand): Use the new opcode reading functions.
1558 Only disassenmble bytes if they were successfully read.
1559 (msp430_doubleoperand): Likewise.
1560 (msp430_branchinstr): Likewise.
1561 (msp430x_callx_instr): Likewise.
1562 (print_insn_msp430): Check that it is safe to read bytes before
1563 attempting disassembly. Use the new opcode reading functions.
1565 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1567 * ppc-opc.c (CY): New define. Document it.
1568 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1570 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1572 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1573 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1574 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1575 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1577 * i386-init.h: Regenerated.
1579 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1582 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1583 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1584 * i386-init.h: Regenerated.
1586 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1588 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1589 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1590 * i386-init.h: Regenerated.
1592 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1594 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1596 (print_insn_arc): Set insn_type information.
1597 * arc-opc.c (C_CC): Add F_CLASS_COND.
1598 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1599 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1600 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1601 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1602 (brne, brne_s, jeq_s, jne_s): Likewise.
1604 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1606 * arc-tbl.h (neg): New instruction variant.
1608 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1610 * arc-dis.c (find_format, find_format, get_auxreg)
1611 (print_insn_arc): Changed.
1612 * arc-ext.h (INSERT_XOP): Likewise.
1614 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1616 * tic54x-dis.c (sprint_mmr): Adjust.
1617 * tic54x-opc.c: Likewise.
1619 2016-05-19 Alan Modra <amodra@gmail.com>
1621 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1623 2016-05-19 Alan Modra <amodra@gmail.com>
1625 * ppc-opc.c: Formatting.
1626 (NSISIGNOPT): Define.
1627 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1629 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1631 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1632 replacing references to `micromips_ase' throughout.
1633 (_print_insn_mips): Don't use file-level microMIPS annotation to
1634 determine the disassembly mode with the symbol table.
1636 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1638 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1640 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1642 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1644 * mips-opc.c (D34): New macro.
1645 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1647 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1649 * i386-dis.c (prefix_table): Add RDPID instruction.
1650 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1651 (cpu_flags): Add RDPID bitfield.
1652 * i386-opc.h (enum): Add RDPID element.
1653 (i386_cpu_flags): Add RDPID field.
1654 * i386-opc.tbl: Add RDPID instruction.
1655 * i386-init.h: Regenerate.
1656 * i386-tbl.h: Regenerate.
1658 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1660 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1661 branch type of a symbol.
1662 (print_insn): Likewise.
1664 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1666 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1667 Mainline Security Extensions instructions.
1668 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1669 Extensions instructions.
1670 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1672 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1675 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1677 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1679 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1681 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1682 (arcExtMap_genOpcode): Likewise.
1683 * arc-opc.c (arg_32bit_rc): Define new variable.
1684 (arg_32bit_u6): Likewise.
1685 (arg_32bit_limm): Likewise.
1687 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1689 * aarch64-gen.c (VERIFIER): Define.
1690 * aarch64-opc.c (VERIFIER): Define.
1691 (verify_ldpsw): Use static linkage.
1692 * aarch64-opc.h (verify_ldpsw): Remove.
1693 * aarch64-tbl.h: Use VERIFIER for verifiers.
1695 2016-04-28 Nick Clifton <nickc@redhat.com>
1698 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1699 * aarch64-opc.c (verify_ldpsw): New function.
1700 * aarch64-opc.h (verify_ldpsw): New prototype.
1701 * aarch64-tbl.h: Add initialiser for verifier field.
1702 (LDPSW): Set verifier to verify_ldpsw.
1704 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1708 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1709 smaller than address size.
1711 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1713 * alpha-dis.c: Regenerate.
1714 * crx-dis.c: Likewise.
1715 * disassemble.c: Likewise.
1716 * epiphany-opc.c: Likewise.
1717 * fr30-opc.c: Likewise.
1718 * frv-opc.c: Likewise.
1719 * ip2k-opc.c: Likewise.
1720 * iq2000-opc.c: Likewise.
1721 * lm32-opc.c: Likewise.
1722 * lm32-opinst.c: Likewise.
1723 * m32c-opc.c: Likewise.
1724 * m32r-opc.c: Likewise.
1725 * m32r-opinst.c: Likewise.
1726 * mep-opc.c: Likewise.
1727 * mt-opc.c: Likewise.
1728 * or1k-opc.c: Likewise.
1729 * or1k-opinst.c: Likewise.
1730 * tic80-opc.c: Likewise.
1731 * xc16x-opc.c: Likewise.
1732 * xstormy16-opc.c: Likewise.
1734 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1736 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1737 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1738 calcsd, and calcxd instructions.
1739 * arc-opc.c (insert_nps_bitop_size): Delete.
1740 (extract_nps_bitop_size): Delete.
1741 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1742 (extract_nps_qcmp_m3): Define.
1743 (extract_nps_qcmp_m2): Define.
1744 (extract_nps_qcmp_m1): Define.
1745 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1746 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1747 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1748 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1749 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1752 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1754 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1756 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1758 * Makefile.in: Regenerated with automake 1.11.6.
1759 * aclocal.m4: Likewise.
1761 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1763 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1765 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1766 (extract_nps_cmem_uimm16): New function.
1767 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1769 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1771 * arc-dis.c (arc_insn_length): New function.
1772 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1773 (find_format): Change insnLen parameter to unsigned.
1775 2016-04-13 Nick Clifton <nickc@redhat.com>
1778 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1779 the LD.B and LD.BU instructions.
1781 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1783 * arc-dis.c (find_format): Check for extension flags.
1784 (print_flags): New function.
1785 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1787 * arc-ext.c (arcExtMap_coreRegName): Use
1788 LAST_EXTENSION_CORE_REGISTER.
1789 (arcExtMap_coreReadWrite): Likewise.
1790 (dump_ARC_extmap): Update printing.
1791 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1792 (arc_aux_regs): Add cpu field.
1793 * arc-regs.h: Add cpu field, lower case name aux registers.
1795 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1797 * arc-tbl.h: Add rtsc, sleep with no arguments.
1799 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1801 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1803 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1804 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1805 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1806 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1807 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1808 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1809 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1810 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1811 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1812 (arc_opcode arc_opcodes): Null terminate the array.
1813 (arc_num_opcodes): Remove.
1814 * arc-ext.h (INSERT_XOP): Define.
1815 (extInstruction_t): Likewise.
1816 (arcExtMap_instName): Delete.
1817 (arcExtMap_insn): New function.
1818 (arcExtMap_genOpcode): Likewise.
1819 * arc-ext.c (ExtInstruction): Remove.
1820 (create_map): Zero initialize instruction fields.
1821 (arcExtMap_instName): Remove.
1822 (arcExtMap_insn): New function.
1823 (dump_ARC_extmap): More info while debuging.
1824 (arcExtMap_genOpcode): New function.
1825 * arc-dis.c (find_format): New function.
1826 (print_insn_arc): Use find_format.
1827 (arc_get_disassembler): Enable dump_ARC_extmap only when
1830 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1832 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1833 instruction bits out.
1835 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1837 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1838 * arc-opc.c (arc_flag_operands): Add new flags.
1839 (arc_flag_classes): Add new classes.
1841 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1843 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1845 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1847 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1848 encode1, rflt, crc16, and crc32 instructions.
1849 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1850 (arc_flag_classes): Add C_NPS_R.
1851 (insert_nps_bitop_size_2b): New function.
1852 (extract_nps_bitop_size_2b): Likewise.
1853 (insert_nps_bitop_uimm8): Likewise.
1854 (extract_nps_bitop_uimm8): Likewise.
1855 (arc_operands): Add new operand entries.
1857 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1859 * arc-regs.h: Add a new subclass field. Add double assist
1860 accumulator register values.
1861 * arc-tbl.h: Use DPA subclass to mark the double assist
1862 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1863 * arc-opc.c (RSP): Define instead of SP.
1864 (arc_aux_regs): Add the subclass field.
1866 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1868 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1870 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1872 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1875 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1877 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1878 issues. No functional changes.
1880 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1882 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1883 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1884 (RTT): Remove duplicate.
1885 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1886 (PCT_CONFIG*): Remove.
1887 (D1L, D1H, D2H, D2L): Define.
1889 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1891 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1893 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1895 * arc-tbl.h (invld07): Remove.
1896 * arc-ext-tbl.h: New file.
1897 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1898 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1900 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1902 Fix -Wstack-usage warnings.
1903 * aarch64-dis.c (print_operands): Substitute size.
1904 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1906 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1908 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1909 to get a proper diagnostic when an invalid ASR register is used.
1911 2016-03-22 Nick Clifton <nickc@redhat.com>
1913 * configure: Regenerate.
1915 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1917 * arc-nps400-tbl.h: New file.
1918 * arc-opc.c: Add top level comment.
1919 (insert_nps_3bit_dst): New function.
1920 (extract_nps_3bit_dst): New function.
1921 (insert_nps_3bit_src2): New function.
1922 (extract_nps_3bit_src2): New function.
1923 (insert_nps_bitop_size): New function.
1924 (extract_nps_bitop_size): New function.
1925 (arc_flag_operands): Add nps400 entries.
1926 (arc_flag_classes): Add nps400 entries.
1927 (arc_operands): Add nps400 entries.
1928 (arc_opcodes): Add nps400 include.
1930 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1932 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1933 the new class enum values.
1935 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1937 * arc-dis.c (print_insn_arc): Handle nps400.
1939 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1941 * arc-opc.c (BASE): Delete.
1943 2016-03-18 Nick Clifton <nickc@redhat.com>
1946 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1947 of MOV insn that aliases an ORR insn.
1949 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1951 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1953 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1955 * mcore-opc.h: Add const qualifiers.
1956 * microblaze-opc.h (struct op_code_struct): Likewise.
1957 * sh-opc.h: Likewise.
1958 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1959 (tic4x_print_op): Likewise.
1961 2016-03-02 Alan Modra <amodra@gmail.com>
1963 * or1k-desc.h: Regenerate.
1964 * fr30-ibld.c: Regenerate.
1965 * rl78-decode.c: Regenerate.
1967 2016-03-01 Nick Clifton <nickc@redhat.com>
1970 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1972 2016-02-24 Renlin Li <renlin.li@arm.com>
1974 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1975 (print_insn_coprocessor): Support fp16 instructions.
1977 2016-02-24 Renlin Li <renlin.li@arm.com>
1979 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1980 vminnm, vrint(mpna).
1982 2016-02-24 Renlin Li <renlin.li@arm.com>
1984 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1985 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1987 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1989 * i386-dis.c (print_insn): Parenthesize expression to prevent
1990 truncated addresses.
1993 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1994 Janek van Oirschot <jvanoirs@synopsys.com>
1996 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1999 2016-02-04 Nick Clifton <nickc@redhat.com>
2002 * msp430-dis.c (print_insn_msp430): Add a special case for
2003 decoding an RRC instruction with the ZC bit set in the extension
2006 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2008 * cgen-ibld.in (insert_normal): Rework calculation of shift.
2009 * epiphany-ibld.c: Regenerate.
2010 * fr30-ibld.c: Regenerate.
2011 * frv-ibld.c: Regenerate.
2012 * ip2k-ibld.c: Regenerate.
2013 * iq2000-ibld.c: Regenerate.
2014 * lm32-ibld.c: Regenerate.
2015 * m32c-ibld.c: Regenerate.
2016 * m32r-ibld.c: Regenerate.
2017 * mep-ibld.c: Regenerate.
2018 * mt-ibld.c: Regenerate.
2019 * or1k-ibld.c: Regenerate.
2020 * xc16x-ibld.c: Regenerate.
2021 * xstormy16-ibld.c: Regenerate.
2023 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
2025 * epiphany-dis.c: Regenerated from latest cpu files.
2027 2016-02-01 Michael McConville <mmcco@mykolab.com>
2029 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
2032 2016-01-25 Renlin Li <renlin.li@arm.com>
2034 * arm-dis.c (mapping_symbol_for_insn): New function.
2035 (find_ifthen_state): Call mapping_symbol_for_insn().
2037 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
2039 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
2040 of MSR UAO immediate operand.
2042 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
2044 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
2045 instruction support.
2047 2016-01-17 Alan Modra <amodra@gmail.com>
2049 * configure: Regenerate.
2051 2016-01-14 Nick Clifton <nickc@redhat.com>
2053 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
2054 instructions that can support stack pointer operations.
2055 * rl78-decode.c: Regenerate.
2056 * rl78-dis.c: Fix display of stack pointer in MOVW based
2059 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
2061 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
2062 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
2063 erxtatus_el1 and erxaddr_el1.
2065 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
2067 * arm-dis.c (arm_opcodes): Add "esb".
2068 (thumb_opcodes): Likewise.
2070 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
2072 * ppc-opc.c <xscmpnedp>: Delete.
2073 <xvcmpnedp>: Likewise.
2074 <xvcmpnedp.>: Likewise.
2075 <xvcmpnesp>: Likewise.
2076 <xvcmpnesp.>: Likewise.
2078 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
2081 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
2084 2016-01-01 Alan Modra <amodra@gmail.com>
2086 Update year range in copyright notice of all files.
2088 For older changes see ChangeLog-2015
2090 Copyright (C) 2016 Free Software Foundation, Inc.
2092 Copying and distribution of this file, with or without modification,
2093 are permitted in any medium without royalty provided the copyright
2094 notice and this notice are preserved.
2100 version-control: never