1 2020-03-04 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
4 (prefix_table): Move vmmcall here. Add vmgexit.
5 (rm_table): Replace vmmcall entry by prefix_table[] escape.
6 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
7 (cpu_flags): Add CpuSEV_ES entry.
8 * i386-opc.h (CpuSEV_ES): New.
9 (union i386_cpu_flags): Add cpusev_es field.
10 * i386-opc.tbl (vmgexit): New.
11 * i386-init.h, i386-tbl.h: Re-generate.
13 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
15 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
17 * i386-opc.h (IGNORESIZE): New.
18 (DEFAULTSIZE): Likewise.
19 (IgnoreSize): Removed.
20 (DefaultSize): Likewise.
22 (i386_opcode_modifier): Replace ignoresize/defaultsize with
24 * i386-opc.tbl (IgnoreSize): New.
25 (DefaultSize): Likewise.
26 * i386-tbl.h: Regenerated.
28 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
31 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
34 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
37 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
38 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
39 * i386-tbl.h: Regenerated.
41 2020-02-26 Alan Modra <amodra@gmail.com>
43 * aarch64-asm.c: Indent labels correctly.
44 * aarch64-dis.c: Likewise.
45 * aarch64-gen.c: Likewise.
46 * aarch64-opc.c: Likewise.
47 * alpha-dis.c: Likewise.
48 * i386-dis.c: Likewise.
49 * nds32-asm.c: Likewise.
50 * nfp-dis.c: Likewise.
51 * visium-dis.c: Likewise.
53 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
55 * arc-regs.h (int_vector_base): Make it available for all ARC
58 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
60 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
63 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
65 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
66 c.mv/c.li if rs1 is zero.
68 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
70 * i386-gen.c (cpu_flag_init): Replace CpuABM with
71 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
73 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
74 * i386-opc.h (CpuABM): Removed.
76 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
77 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
78 popcnt. Remove CpuABM from lzcnt.
79 * i386-init.h: Regenerated.
80 * i386-tbl.h: Likewise.
82 2020-02-17 Jan Beulich <jbeulich@suse.com>
84 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
85 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
86 VexW1 instead of open-coding them.
87 * i386-tbl.h: Re-generate.
89 2020-02-17 Jan Beulich <jbeulich@suse.com>
91 * i386-opc.tbl (AddrPrefixOpReg): Define.
92 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
93 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
94 templates. Drop NoRex64.
95 * i386-tbl.h: Re-generate.
97 2020-02-17 Jan Beulich <jbeulich@suse.com>
100 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
101 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
102 into Intel syntax instance (with Unpsecified) and AT&T one
104 (vcvtneps2bf16): Likewise, along with folding the two so far
106 * i386-tbl.h: Re-generate.
108 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
110 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
113 2020-02-17 Alan Modra <amodra@gmail.com>
115 * i386-gen.c (cpu_flag_init): Correct last change.
117 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
119 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
122 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
124 * i386-opc.tbl (movsx): Remove Intel syntax comments.
127 2020-02-14 Jan Beulich <jbeulich@suse.com>
130 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
131 destination for Cpu64-only variant.
132 (movzx): Fold patterns.
133 * i386-tbl.h: Re-generate.
135 2020-02-13 Jan Beulich <jbeulich@suse.com>
137 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
138 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
139 CPU_ANY_SSE4_FLAGS entry.
140 * i386-init.h: Re-generate.
142 2020-02-12 Jan Beulich <jbeulich@suse.com>
144 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
145 with Unspecified, making the present one AT&T syntax only.
146 * i386-tbl.h: Re-generate.
148 2020-02-12 Jan Beulich <jbeulich@suse.com>
150 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
151 * i386-tbl.h: Re-generate.
153 2020-02-12 Jan Beulich <jbeulich@suse.com>
156 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
157 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
158 Amd64 and Intel64 templates.
159 (call, jmp): Likewise for far indirect variants. Dro
161 * i386-tbl.h: Re-generate.
163 2020-02-11 Jan Beulich <jbeulich@suse.com>
165 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
166 * i386-opc.h (ShortForm): Delete.
167 (struct i386_opcode_modifier): Remove shortform field.
168 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
169 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
170 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
171 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
173 * i386-tbl.h: Re-generate.
175 2020-02-11 Jan Beulich <jbeulich@suse.com>
177 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
178 fucompi): Drop ShortForm from operand-less templates.
179 * i386-tbl.h: Re-generate.
181 2020-02-11 Alan Modra <amodra@gmail.com>
183 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
184 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
185 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
186 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
187 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
189 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
191 * arm-dis.c (print_insn_cde): Define 'V' parse character.
192 (cde_opcodes): Add VCX* instructions.
194 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
195 Matthew Malcomson <matthew.malcomson@arm.com>
197 * arm-dis.c (struct cdeopcode32): New.
198 (CDE_OPCODE): New macro.
199 (cde_opcodes): New disassembly table.
200 (regnames): New option to table.
201 (cde_coprocs): New global variable.
202 (print_insn_cde): New
203 (print_insn_thumb32): Use print_insn_cde.
204 (parse_arm_disassembler_options): Parse coprocN args.
206 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
209 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
211 * i386-opc.h (AMD64): Removed.
215 (INTEL64ONLY): Likewise.
216 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
217 * i386-opc.tbl (Amd64): New.
219 (Intel64Only): Likewise.
220 Replace AMD64 with Amd64. Update sysenter/sysenter with
221 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
222 * i386-tbl.h: Regenerated.
224 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
227 * z80-dis.c: Add support for GBZ80 opcodes.
229 2020-02-04 Alan Modra <amodra@gmail.com>
231 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
233 2020-02-03 Alan Modra <amodra@gmail.com>
235 * m32c-ibld.c: Regenerate.
237 2020-02-01 Alan Modra <amodra@gmail.com>
239 * frv-ibld.c: Regenerate.
241 2020-01-31 Jan Beulich <jbeulich@suse.com>
243 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
244 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
245 (OP_E_memory): Replace xmm_mdq_mode case label by
246 vex_scalar_w_dq_mode one.
247 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
249 2020-01-31 Jan Beulich <jbeulich@suse.com>
251 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
252 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
253 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
254 (intel_operand_size): Drop vex_w_dq_mode case label.
256 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
258 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
259 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
261 2020-01-30 Alan Modra <amodra@gmail.com>
263 * m32c-ibld.c: Regenerate.
265 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
267 * bpf-opc.c: Regenerate.
269 2020-01-30 Jan Beulich <jbeulich@suse.com>
271 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
272 (dis386): Use them to replace C2/C3 table entries.
273 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
274 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
275 ones. Use Size64 instead of DefaultSize on Intel64 ones.
276 * i386-tbl.h: Re-generate.
278 2020-01-30 Jan Beulich <jbeulich@suse.com>
280 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
282 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
284 * i386-tbl.h: Re-generate.
286 2020-01-30 Alan Modra <amodra@gmail.com>
288 * tic4x-dis.c (tic4x_dp): Make unsigned.
290 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
291 Jan Beulich <jbeulich@suse.com>
294 * i386-dis.c (MOVSXD_Fixup): New function.
295 (movsxd_mode): New enum.
296 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
297 (intel_operand_size): Handle movsxd_mode.
298 (OP_E_register): Likewise.
300 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
301 register on movsxd. Add movsxd with 16-bit destination register
302 for AMD64 and Intel64 ISAs.
303 * i386-tbl.h: Regenerated.
305 2020-01-27 Tamar Christina <tamar.christina@arm.com>
308 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
309 * aarch64-asm-2.c: Regenerate
310 * aarch64-dis-2.c: Likewise.
311 * aarch64-opc-2.c: Likewise.
313 2020-01-21 Jan Beulich <jbeulich@suse.com>
315 * i386-opc.tbl (sysret): Drop DefaultSize.
316 * i386-tbl.h: Re-generate.
318 2020-01-21 Jan Beulich <jbeulich@suse.com>
320 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
322 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
323 * i386-tbl.h: Re-generate.
325 2020-01-20 Nick Clifton <nickc@redhat.com>
327 * po/de.po: Updated German translation.
328 * po/pt_BR.po: Updated Brazilian Portuguese translation.
329 * po/uk.po: Updated Ukranian translation.
331 2020-01-20 Alan Modra <amodra@gmail.com>
333 * hppa-dis.c (fput_const): Remove useless cast.
335 2020-01-20 Alan Modra <amodra@gmail.com>
337 * arm-dis.c (print_insn_arm): Wrap 'T' value.
339 2020-01-18 Nick Clifton <nickc@redhat.com>
341 * configure: Regenerate.
342 * po/opcodes.pot: Regenerate.
344 2020-01-18 Nick Clifton <nickc@redhat.com>
346 Binutils 2.34 branch created.
348 2020-01-17 Christian Biesinger <cbiesinger@google.com>
350 * opintl.h: Fix spelling error (seperate).
352 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
354 * i386-opc.tbl: Add {vex} pseudo prefix.
355 * i386-tbl.h: Regenerated.
357 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
360 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
361 (neon_opcodes): Likewise.
362 (select_arm_features): Make sure we enable MVE bits when selecting
363 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
366 2020-01-16 Jan Beulich <jbeulich@suse.com>
368 * i386-opc.tbl: Drop stale comment from XOP section.
370 2020-01-16 Jan Beulich <jbeulich@suse.com>
372 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
373 (extractps): Add VexWIG to SSE2AVX forms.
374 * i386-tbl.h: Re-generate.
376 2020-01-16 Jan Beulich <jbeulich@suse.com>
378 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
379 Size64 from and use VexW1 on SSE2AVX forms.
380 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
381 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
382 * i386-tbl.h: Re-generate.
384 2020-01-15 Alan Modra <amodra@gmail.com>
386 * tic4x-dis.c (tic4x_version): Make unsigned long.
387 (optab, optab_special, registernames): New file scope vars.
388 (tic4x_print_register): Set up registernames rather than
389 malloc'd registertable.
390 (tic4x_disassemble): Delete optable and optable_special. Use
391 optab and optab_special instead. Throw away old optab,
392 optab_special and registernames when info->mach changes.
394 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
397 * z80-dis.c (suffix): Use .db instruction to generate double
400 2020-01-14 Alan Modra <amodra@gmail.com>
402 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
403 values to unsigned before shifting.
405 2020-01-13 Thomas Troeger <tstroege@gmx.de>
407 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
409 (print_insn_thumb16, print_insn_thumb32): Likewise.
410 (print_insn): Initialize the insn info.
411 * i386-dis.c (print_insn): Initialize the insn info fields, and
414 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
416 * arc-opc.c (C_NE): Make it required.
418 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
420 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
421 reserved register name.
423 2020-01-13 Alan Modra <amodra@gmail.com>
425 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
426 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
428 2020-01-13 Alan Modra <amodra@gmail.com>
430 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
431 result of wasm_read_leb128 in a uint64_t and check that bits
432 are not lost when copying to other locals. Use uint32_t for
433 most locals. Use PRId64 when printing int64_t.
435 2020-01-13 Alan Modra <amodra@gmail.com>
437 * score-dis.c: Formatting.
438 * score7-dis.c: Formatting.
440 2020-01-13 Alan Modra <amodra@gmail.com>
442 * score-dis.c (print_insn_score48): Use unsigned variables for
443 unsigned values. Don't left shift negative values.
444 (print_insn_score32): Likewise.
445 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
447 2020-01-13 Alan Modra <amodra@gmail.com>
449 * tic4x-dis.c (tic4x_print_register): Remove dead code.
451 2020-01-13 Alan Modra <amodra@gmail.com>
453 * fr30-ibld.c: Regenerate.
455 2020-01-13 Alan Modra <amodra@gmail.com>
457 * xgate-dis.c (print_insn): Don't left shift signed value.
458 (ripBits): Formatting, use 1u.
460 2020-01-10 Alan Modra <amodra@gmail.com>
462 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
463 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
465 2020-01-10 Alan Modra <amodra@gmail.com>
467 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
468 and XRREG value earlier to avoid a shift with negative exponent.
469 * m10200-dis.c (disassemble): Similarly.
471 2020-01-09 Nick Clifton <nickc@redhat.com>
474 * z80-dis.c (ld_ii_ii): Use correct cast.
476 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
479 * z80-dis.c (ld_ii_ii): Use character constant when checking
482 2020-01-09 Jan Beulich <jbeulich@suse.com>
484 * i386-dis.c (SEP_Fixup): New.
486 (dis386_twobyte): Use it for sysenter/sysexit.
487 (enum x86_64_isa): Change amd64 enumerator to value 1.
488 (OP_J): Compare isa64 against intel64 instead of amd64.
489 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
491 * i386-tbl.h: Re-generate.
493 2020-01-08 Alan Modra <amodra@gmail.com>
495 * z8k-dis.c: Include libiberty.h
496 (instr_data_s): Make max_fetched unsigned.
497 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
498 Don't exceed byte_info bounds.
499 (output_instr): Make num_bytes unsigned.
500 (unpack_instr): Likewise for nibl_count and loop.
501 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
503 * z8k-opc.h: Regenerate.
505 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
507 * arc-tbl.h (llock): Use 'LLOCK' as class.
509 (scond): Use 'SCOND' as class.
511 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
514 2020-01-06 Alan Modra <amodra@gmail.com>
516 * m32c-ibld.c: Regenerate.
518 2020-01-06 Alan Modra <amodra@gmail.com>
521 * z80-dis.c (suffix): Don't use a local struct buffer copy.
522 Peek at next byte to prevent recursion on repeated prefix bytes.
523 Ensure uninitialised "mybuf" is not accessed.
524 (print_insn_z80): Don't zero n_fetch and n_used here,..
525 (print_insn_z80_buf): ..do it here instead.
527 2020-01-04 Alan Modra <amodra@gmail.com>
529 * m32r-ibld.c: Regenerate.
531 2020-01-04 Alan Modra <amodra@gmail.com>
533 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
535 2020-01-04 Alan Modra <amodra@gmail.com>
537 * crx-dis.c (match_opcode): Avoid shift left of signed value.
539 2020-01-04 Alan Modra <amodra@gmail.com>
541 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
543 2020-01-03 Jan Beulich <jbeulich@suse.com>
545 * aarch64-tbl.h (aarch64_opcode_table): Use
546 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
548 2020-01-03 Jan Beulich <jbeulich@suse.com>
550 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
551 forms of SUDOT and USDOT.
553 2020-01-03 Jan Beulich <jbeulich@suse.com>
555 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
557 * opcodes/aarch64-dis-2.c: Re-generate.
559 2020-01-03 Jan Beulich <jbeulich@suse.com>
561 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
563 * opcodes/aarch64-dis-2.c: Re-generate.
565 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
567 * z80-dis.c: Add support for eZ80 and Z80 instructions.
569 2020-01-01 Alan Modra <amodra@gmail.com>
571 Update year range in copyright notice of all files.
573 For older changes see ChangeLog-2019
575 Copyright (C) 2020 Free Software Foundation, Inc.
577 Copying and distribution of this file, with or without modification,
578 are permitted in any medium without royalty provided the copyright
579 notice and this notice are preserved.
585 version-control: never