opcodes/ChangeLog

   1 2006-12-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (CMPXCHG8B_Fixup): New.
   4         (grps): Use CMPXCHG8B_Fixup for cmpxchg8b.
   5
   6 2006-12-11  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         * i386-dis.c (Eq): Replaced by ...
   9         (Mq): New. This.
  10         (Ma): Defined with OP_M instead of OP_E.
  11         (grps): Updated cmpxchg8b and vmptrst for Eq -> Mq.
  12         (OP_M): Added bound, cmpxchg8b and vmptrst to bad modrm list.
  13
  14 2006-12-11  Daniel Jacobowitz  <dan@codesourcery.com>
  15
  16         * po/Make-in (.po.gmo): Put gmo files in objdir.
  17
  18 2006-12-09  H.J. Lu  <hongjiu.lu@intel.com>
  19
  20         * i386-dis.c (X86_64_1): New.
  21         (X86_64_2): Likewise.
  22         (X86_64_3): Likewise.
  23         (dis386): Replace 0x60, 0x61 and 0x62 entries with x86-64
  24         tables.
  25         (x86_64_table): Add entries for 0x60, 0x61 and 0x62.
  26
  27 2006-12-09  H.J. Lu  <hongjiu.lu@intel.com>
  28
  29         * i386-dis.c: Adjust white spaces.
  30
  31 2006-12-04  Jan Beulich  <jbeulich@novell.com>
  32
  33         * i386-dis.c (OP_J): Update used_prefixes in v_mode.
  34
  35 2006-11-30  Jan Beulich  <jbeulich@novell.com>
  36
  37         * i386-dis.c (SEG_Fixup): Delete.
  38         (Sv): Use OP_SEG.
  39         (putop): New suffix character 'D'.
  40         (dis386): Use it.
  41         (grps): Likewise.
  42         (OP_SEG): Handle bytemode other than w_mode.
  43
  44 2006-11-30  Jan Beulich  <jbeulich@novell.com>
  45
  46         * i386-dis.c (zAX): New.
  47         (Xz): New.
  48         (Yzr): New.
  49         (z_mode): New.
  50         (z_mode_ax_reg): New.
  51         (putop): New suffix character 'G'.
  52         (dis386): Use it for in, out, ins, and outs.
  53         (intel_operand_size): Handle z_mode.
  54         (OP_REG): Delete unreachable case indir_dx_reg.
  55         (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle
  56         z_mode_ax_reg.
  57         (OP_ESreg): Fix Intel syntax operand size handling.
  58         (OP_DSreg): Likewise.
  59
  60 2006-11-30  Jan Beulich  <jbeulich@novell.com>
  61
  62         * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally.
  63         (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix
  64         used. For 'R' and 'W' suffix, simplify and fix Intel mode.
  65
  66 2006-11-29  Paul Brook  <paul@codesourcery.com>
  67
  68         * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd.
  69
  70 2006-11-22  Daniel Jacobowitz  <dan@codesourcery.com>
  71
  72         * arm-dis.c (last_is_thumb): Delete.
  73         (enum map_type, last_type): New.
  74         (print_insn_data): New.
  75         (get_sym_code_type): Take MAP_TYPE argument.  Check the type of
  76         the right symbol.  Handle $d.
  77         (print_insn): Check for mapping symbols even without a normal
  78         symbol.  Adjust searching.  If $d is found see how much data
  79         to print.  Handle data.
  80
  81 2006-11-16  Nathan Sidwell  <nathan@codesourcery.com>
  82
  83         * m68k-opc.c (m68k_opcodes): Place trap instructions before set
  84         conditionals.  Add tpf coldfire instruction as alias for trapf.
  85
  86 2006-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  87
  88         * i386-dis.c (print_insn): Check PREFIX_REPNZ before
  89         PREFIX_DATA when prefix user table is used.
  90
  91 2006-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  92
  93         * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
  94         (twobyte_uses_DATA_prefix): This.
  95         (twobyte_uses_REPNZ_prefix): New.
  96         (twobyte_uses_REPZ_prefix): Likewise.
  97         (threebyte_0x38_uses_DATA_prefix): Likewise.
  98         (threebyte_0x38_uses_REPNZ_prefix): Likewise.
  99         (threebyte_0x38_uses_REPZ_prefix): Likewise.
 100         (threebyte_0x3a_uses_DATA_prefix): Likewise.
 101         (threebyte_0x3a_uses_REPNZ_prefix): Likewise.
 102         (threebyte_0x3a_uses_REPZ_prefix): Likewise.
 103         (print_insn): Updated checking usages of DATA/REPNZ/REPZ
 104         prefixes.
 105
 106 2006-11-06  Troy Rollo  <troy@corvu.com.au>
 107
 108         * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.
 109
 110 2006-11-01  Mei Ligang  <ligang@sunnorth.com.cn>
 111
 112         * score-opc.h (score_opcodes): Delete modifier '0x'.
 113
 114 2006-10-30  Paul Brook  <paul@codesourcery.com>
 115
 116         * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
 117         (get_sym_code_type): New function.
 118         (print_insn): Search for mapping symbols.
 119
 120 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 121
 122         * score-dis.c (print_insn): Correct the error code to print
 123         correct PCE instruction disassembly.
 124
 125 2006-10-26  Ben Elliston  <bje@au.ibm.com>
 126             Anton Blanchard  <anton@samba.org>
 127             Peter Bergner  <bergner@vnet.ibm.com>
 128
 129         * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
 130         AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
 131         (POWER6): Define.
 132         (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
 133         "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
 134         Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
 135         "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
 136         "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
 137         "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
 138         "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
 139         "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
 140         "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
 141         "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
 142         "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
 143         "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
 144         "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
 145         "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
 146         "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
 147         "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
 148         "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
 149         "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
 150         "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
 151         "diexq" and "diexq." opcodes.
 152
 153 2006-10-26  Daniel Jacobowitz  <dan@codesourcery.com>
 154
 155         * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
 156
 157 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 158             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 159             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 160             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 161             Alan Modra  <amodra@bigpond.net.au>
 162
 163         * spu-dis.c: New file.
 164         * spu-opc.c: New file.
 165         * configure.in: Add SPU support.
 166         * disassemble.c: Likewise.
 167         * Makefile.am: Likewise.  Run "make dep-am".
 168         * Makefile.in: Regenerate.
 169         * configure: Regenerate.
 170         * po/POTFILES.in: Regenerate.
 171
 172 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 173
 174         * ppc-opc.c (CELL): New define.
 175         (powerpc_opcodes): Enable hrfid for Cell.  Add ldbrx and stdbrx,
 176         cell specific instructions.  Add {st,l}x{r,l}{,l} cell specific
 177         VMX instructions.
 178         * ppc-dis.c (powerpc_dialect): Handle cell.
 179
 180 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 181
 182         * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
 183         amdfam10 architecture.
 184         (PREGRP37): NEW.
 185         (print_insn): Disallow REP prefix for POPCNT.
 186
 187 2006-10-20  Andrew Stubbs  <andrew.stubbs@st.com>
 188
 189         * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
 190         duplicating it.
 191
 192 2006-10-18  Dave Brolley  <brolley@redhat.com>
 193
 194         * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
 195         * configure: Regenerated.
 196
 197 2006-09-29  Alan Modra  <amodra@bigpond.net.au>
 198
 199         * po/POTFILES.in: Regenerate.
 200
 201 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 202             Joseph Myers  <joseph@codesourcery.com>
 203             Ian Lance Taylor  <ian@wasabisystems.com>
 204             Ben Elliston  <bje@wasabisystems.com>
 205
 206         * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
 207         only be used with the default multiply-add operation, so if N is
 208         set, don't bother printing X.  Add new iwmmxt instructions.
 209         (IWMMXT_INSN_COUNT): Update.
 210         (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
 211         with a 'c' suffix.
 212         (print_insn_coprocessor): Check for iWMMXt2.  Handle format
 213         specifiers 'r', 'i'.
 214
 215 2006-09-24  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 216
 217         PR binutils/3100
 218         * i386-dis.c (prefix_user_table): Fix the second operand of
 219         maskmovdqu instruction to allow only %xmm register instead of
 220         both %xmm register and memory.
 221
 222 2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
 223
 224         PR binutils/3235
 225         * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
 226         address size prefix.
 227
 228 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 229
 230         * score-dis.c: New file.
 231         * score-opc.h: New file.
 232         * Makefile.am: Add Score files.
 233         * Makefile.in: Regenerate.
 234         * configure.in: Add support for Score target.
 235         * configure: Regenerate.
 236         * disassemble.c: Add support for Score target.
 237
 238 2006-09-16  Nick Clifton  <nickc@redhat.com>
 239             Pedro Alves  <pedro_alves@portugalmail.pt>
 240
 241         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
 242         macros defined in bfd.h.
 243         * cris-dis.c: Likewise.
 244         * h8300-dis.c: Likewise.
 245         * i386-dis.c: Likewise.
 246         * ia64-gen.c: Likewise.
 247         * mips-dis: Likewise.
 248
 249 2006-09-04  Paul Brook  <paul@codesourcery.com>
 250
 251         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
 252
 253 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         * i386-dis.c (three_byte_table): Expand to 256 elements.
 256
 257 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 258
 259         PR binutils/3000
 260         * i386-dis.c (MXC,EMC): Define.
 261         (OP_MXC): New function to handle cvt* (convert instructions) between
 262         %xmm and %mm register correctly.
 263         (OP_EMC): ditto.
 264         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
 265         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
 266         with EMC/MXC.
 267
 268 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
 269
 270         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
 271         "fdaddl" entry.
 272
 273 2006-07-19  Paul Brook  <paul@codesourcery.com>
 274
 275         * armd-dis.c (arm_opcodes): Fix rbit opcode.
 276
 277 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
 280         "sldt", "str" and "smsw".
 281
 282 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 283
 284         PR binutils/2829
 285         * i386-dis.c (GRP11_C6): NEW.
 286         (GRP11_C7): Likewise.
 287         (GRP12): Updated.
 288         (GRP13): Likewise.
 289         (GRP14): Likewise.
 290         (GRP15): Likewise.
 291         (GRP16): Likewise.
 292         (GRPAMD): Likewise.
 293         (GRPPADLCK1): Likewise.
 294         (GRPPADLCK2): Likewise.
 295         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
 296         respectively.
 297         (grps): Add entries for GRP11_C6 and GRP11_C7.
 298
 299 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 300            Michael Meissner             <michael.meissner@amd.com>
 301
 302         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
 303         support for amdfam10 SSE4a/ABM instructions. Modify all
 304         initializer macros to have additional arguments. Disallow REP
 305         prefix for non-string instructions.
 306         (print_insn): Ditto.
 307
 308 2006-07-05  Julian Brown  <julian@codesourcery.com>
 309
 310         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
 311
 312 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
 315         (twobyte_has_modrm): Set 1 for 0x1f.
 316
 317 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         * i386-dis.c (NOP_Fixup): Removed.
 320         (NOP_Fixup1): New.
 321         (NOP_Fixup2): Likewise.
 322         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 323
 324 2006-06-12  Julian Brown  <julian@codesourcery.com>
 325
 326         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
 327         on 64-bit hosts.
 328
 329 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 330
 331         * i386.c (GRP10): Renamed to ...
 332         (GRP12): This.
 333         (GRP11): Renamed to ...
 334         (GRP13): This.
 335         (GRP12): Renamed to ...
 336         (GRP14): This.
 337         (GRP13): Renamed to ...
 338         (GRP15): This.
 339         (GRP14): Renamed to ...
 340         (GRP16): This.
 341         (dis386_twobyte): Updated.
 342         (grps): Likewise.
 343
 344 2006-06-09  Nick Clifton  <nickc@redhat.com>
 345
 346         * po/fi.po: Updated Finnish translation.
 347
 348 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 349
 350         * po/Make-in (pdf, ps): New dummy targets.
 351
 352 2006-06-06  Paul Brook  <paul@codesourcery.com>
 353
 354         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 355         instructions.
 356         (neon_opcodes): Add conditional execution specifiers.
 357         (thumb_opcodes): Ditto.
 358         (thumb32_opcodes): Ditto.
 359         (arm_conditional): Change 0xe to "al" and add "" to end.
 360         (ifthen_state, ifthen_next_state, ifthen_address): New.
 361         (IFTHEN_COND): Define.
 362         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 363         (print_insn_arm): Change %c to use new values of arm_conditional.
 364         (print_insn_thumb16): Print thumb conditions.  Add %I.
 365         (print_insn_thumb32): Print thumb conditions.
 366         (find_ifthen_state): New function.
 367         (print_insn): Track IT block state.
 368
 369 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 370             Anton Blanchard  <anton@samba.org>
 371             Peter Bergner  <bergner@vnet.ibm.com>
 372
 373         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 374         (print_ppc_disassembler_options): Mention power6.
 375
 376 2006-06-06  Thiemo Seufer  <ths@mips.com>
 377             Chao-ying Fu  <fu@mips.com>
 378
 379         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 380         * mips-opc.c: Add DSP64 instructions.
 381
 382 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 383
 384         * m68hc11-dis.c (print_insn): Warning fix.
 385
 386 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 387
 388         * po/Make-in (top_builddir): Define.
 389
 390 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 391
 392         * Makefile.am: Run "make dep-am".
 393         * Makefile.in: Regenerate.
 394         * config.in: Regenerate.
 395
 396 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 397
 398         * Makefile.am (INCLUDES): Use @INCINTL@.
 399         * acinclude.m4: Include new gettext macros.
 400         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 401         Remove local code for po/Makefile.
 402         * Makefile.in, aclocal.m4, configure: Regenerated.
 403
 404 2006-05-30  Nick Clifton  <nickc@redhat.com>
 405
 406         * po/es.po: Updated Spanish translation.
 407
 408 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 409
 410         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 411         and fmovem entries.  Put register list entries before immediate
 412         mask entries.  Use "l" rather than "L" in the fmovem entries.
 413         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 414         out from INFO.
 415         (m68k_scan_mask): New function, split out from...
 416         (print_insn_m68k): ...here.  If no architecture has been set,
 417         first try printing an m680x0 instruction, then try a Coldfire one.
 418
 419 2006-05-24  Nick Clifton  <nickc@redhat.com>
 420
 421         * po/ga.po: Updated Irish translation.
 422
 423 2006-05-22  Nick Clifton  <nickc@redhat.com>
 424
 425         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 426
 427 2006-05-22  Nick Clifton  <nickc@redhat.com>
 428
 429         * po/nl.po: Updated translation.
 430
 431 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 432
 433         * avr-dis.c: Formatting fix.
 434
 435 2006-05-14  Thiemo Seufer  <ths@mips.com>
 436
 437         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 438         (mips16_opcodes): Change membership of instructions to their
 439         lowest baseline ISA.
 440
 441 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 442
 443         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 444
 445 2006-05-05  Julian Brown  <julian@codesourcery.com>
 446
 447         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 448         vldm/vstm.
 449
 450 2006-05-05  Thiemo Seufer  <ths@mips.com>
 451             David Ung  <davidu@mips.com>
 452
 453         * mips-opc.c: Add macro for cache instruction.
 454
 455 2006-05-04  Thiemo Seufer  <ths@mips.com>
 456             Nigel Stephens  <nigel@mips.com>
 457             David Ung  <davidu@mips.com>
 458
 459         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 460         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 461         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 462         MIPS64R2.
 463         * mips-opc.c: fix random typos in comments.
 464         (INSN_SMARTMIPS): New defines.
 465         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 466         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 467         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 468         FP_S and FP_D flags to denote single and double register
 469         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 470         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 471         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 472         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 473         release 2 ISAs.
 474         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 475
 476 2006-05-03  Thiemo Seufer  <ths@mips.com>
 477
 478         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 479
 480 2006-05-02  Thiemo Seufer  <ths@mips.com>
 481             Nigel Stephens  <nigel@mips.com>
 482             David Ung  <davidu@mips.com>
 483
 484         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 485         (print_mips16_insn_arg): Force mips16 to odd addresses.
 486
 487 2006-04-30  Thiemo Seufer  <ths@mips.com>
 488             David Ung  <davidu@mips.com>
 489
 490         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 491         "udi0" to "udi15".
 492         * mips-dis.c (print_insn_args): Adds udi argument handling.
 493
 494 2006-04-28  James E Wilson  <wilson@specifix.com>
 495
 496         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 497         error message.
 498
 499 2006-04-28  Thiemo Seufer  <ths@mips.com>
 500             David Ung  <davidu@mips.com>
 501             Nigel Stephens  <nigel@mips.com>
 502
 503         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 504         names.
 505
 506 2006-04-28  Thiemo Seufer  <ths@mips.com>
 507             Nigel Stephens  <nigel@mips.com>
 508             David Ung  <davidu@mips.com>
 509
 510         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 511         (print_insn_mips):  Adjust print_insn_args call.
 512
 513 2006-04-28  Thiemo Seufer  <ths@mips.com>
 514             Nigel Stephens  <nigel@mips.com>
 515
 516         * mips-dis.c (print_insn_args): Print $fcc only for FP
 517         instructions, use $cc elsewise.
 518
 519 2006-04-28  Thiemo Seufer  <ths@mips.com>
 520             Nigel Stephens  <nigel@mips.com>
 521
 522         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 523         Map MIPS16 registers to O32 names.
 524         (print_mips16_insn_arg): Use mips16_reg_names.
 525
 526 2006-04-26  Julian Brown  <julian@codesourcery.com>
 527
 528         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 529         VMOV.
 530
 531 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 532             Julian Brown  <julian@codesourcery.com>
 533
 534         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 535         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 536         Add unified load/store instruction names.
 537         (neon_opcode_table): New.
 538         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 539         (arm_decode_bitfield): New.
 540         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 541         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 542         (print_insn_neon): New.
 543         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 544         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 545         (print_insn_thumb32): Likewise.
 546
 547 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 548
 549         * Makefile.am: Run "make dep-am".
 550         * Makefile.in: Regenerate.
 551
 552 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 553
 554         * avr-dis.c (avr_operand): Warning fix.
 555
 556         * configure: Regenerate.
 557
 558 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 559
 560         * po/POTFILES.in: Regenerated.
 561
 562 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 563
 564         PR binutils/2454
 565         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 566         the symolic form of an address, so that the output of objdump -d
 567         can be reassembled.
 568
 569 2006-04-10  DJ Delorie  <dj@redhat.com>
 570
 571         * m32c-asm.c: Regenerate.
 572
 573 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 574
 575         * Makefile.am: Add install-html target.
 576         * Makefile.in: Regenerate.
 577
 578 2006-04-06  Nick Clifton  <nickc@redhat.com>
 579
 580         * po/vi/po: Updated Vietnamese translation.
 581
 582 2006-03-31  Paul Koning  <ni1d@arrl.net>
 583
 584         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 585
 586 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 587
 588         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 589         logic to identify halfword shifts.
 590
 591 2006-03-16  Paul Brook  <paul@codesourcery.com>
 592
 593         * arm-dis.c (arm_opcodes): Rename swi to svc.
 594         (thumb_opcodes): Ditto.
 595
 596 2006-03-13  DJ Delorie  <dj@redhat.com>
 597
 598         * m32c-asm.c: Regenerate.
 599         * m32c-desc.c: Likewise.
 600         * m32c-desc.h: Likewise.
 601         * m32c-dis.c: Likewise.
 602         * m32c-ibld.c: Likewise.
 603         * m32c-opc.c: Likewise.
 604         * m32c-opc.h: Likewise.
 605
 606 2006-03-10  DJ Delorie  <dj@redhat.com>
 607
 608         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 609         * m32c-opc.c: Likewise.
 610         * m32c-opc.h: Likewise.
 611
 612
 613 2006-03-09  Nick Clifton  <nickc@redhat.com>
 614
 615         * po/sv.po: Updated Swedish translation.
 616
 617 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 618
 619         PR binutils/2428
 620         * i386-dis.c (REP_Fixup): New function.
 621         (AL): Remove duplicate.
 622         (Xbr): New.
 623         (Xvr): Likewise.
 624         (Ybr): Likewise.
 625         (Yvr): Likewise.
 626         (indirDXr): Likewise.
 627         (ALr): Likewise.
 628         (eAXr): Likewise.
 629         (dis386): Updated entries of ins, outs, movs, lods and stos.
 630
 631 2006-03-05  Nick Clifton  <nickc@redhat.com>
 632
 633         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 634         signed 32-bit value into an unsigned 32-bit field when the host is
 635         a 64-bit machine.
 636         * fr30-ibld.c: Regenerate.
 637         * frv-ibld.c: Regenerate.
 638         * ip2k-ibld.c: Regenerate.
 639         * iq2000-asm.c: Regenerate.
 640         * iq2000-ibld.c: Regenerate.
 641         * m32c-ibld.c: Regenerate.
 642         * m32r-ibld.c: Regenerate.
 643         * openrisc-ibld.c: Regenerate.
 644         * xc16x-ibld.c: Regenerate.
 645         * xstormy16-ibld.c: Regenerate.
 646
 647 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 648
 649         * xc16x-asm.c: Regenerate.
 650         * xc16x-dis.c: Regenerate.
 651
 652 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 653
 654         * po/Make-in: Add html target.
 655
 656 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 657
 658         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 659         Intel Merom New Instructions.
 660         (THREE_BYTE_0): Likewise.
 661         (THREE_BYTE_1): Likewise.
 662         (three_byte_table): Likewise.
 663         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 664         THREE_BYTE_1 for entry 0x3a.
 665         (twobyte_has_modrm): Updated.
 666         (twobyte_uses_SSE_prefix): Likewise.
 667         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 668         Instructions.
 669
 670 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 671
 672         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 673         (v9_hpriv_reg_names): New table.
 674         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 675         New cases '$' and '%' for read/write hyperprivileged register.
 676         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 677         window handling and rdhpr/wrhpr instructions.
 678
 679 2006-02-24  DJ Delorie  <dj@redhat.com>
 680
 681         * m32c-desc.c: Regenerate with linker relaxation attributes.
 682         * m32c-desc.h: Likewise.
 683         * m32c-dis.c: Likewise.
 684         * m32c-opc.c: Likewise.
 685
 686 2006-02-24  Paul Brook  <paul@codesourcery.com>
 687
 688         * arm-dis.c (arm_opcodes): Add V7 instructions.
 689         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 690         (print_arm_address): New function.
 691         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 692         (psr_name): New function.
 693         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 694
 695 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 696
 697         * ia64-opc-i.c (bXc): New.
 698         (mXc): Likewise.
 699         (OpX2TaTbYaXcC): Likewise.
 700         (TF). Likewise.
 701         (TFCM). Likewise.
 702         (ia64_opcodes_i): Add instructions for tf.
 703
 704         * ia64-opc.h (IMMU5b): New.
 705
 706         * ia64-asmtab.c: Regenerated.
 707
 708 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 709
 710         * ia64-gen.c: Update copyright years.
 711         * ia64-opc-b.c: Likewise.
 712
 713 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 714
 715         * ia64-gen.c (lookup_regindex): Handle ".vm".
 716         (print_dependency_table): Handle '\"'.
 717
 718         * ia64-ic.tbl: Updated from SDM 2.2.
 719         * ia64-raw.tbl: Likewise.
 720         * ia64-waw.tbl: Likewise.
 721         * ia64-asmtab.c: Regenerated.
 722
 723         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 724
 725 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 726             Anil Paranjape   <anilp1@kpitcummins.com>
 727             Shilin Shakti    <shilins@kpitcummins.com>
 728
 729         * xc16x-desc.h: New file
 730         * xc16x-desc.c: New file
 731         * xc16x-opc.h: New file
 732         * xc16x-opc.c: New file
 733         * xc16x-ibld.c: New file
 734         * xc16x-asm.c: New file
 735         * xc16x-dis.c: New file
 736         * Makefile.am: Entries for xc16x
 737         * Makefile.in: Regenerate
 738         * cofigure.in: Add xc16x target information.
 739         * configure: Regenerate.
 740         * disassemble.c: Add xc16x target information.
 741
 742 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 743
 744         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 745         moves.
 746
 747 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 748
 749         * i386-dis.c ('Z'): Add a new macro.
 750         (dis386_twobyte): Use "movZ" for control register moves.
 751
 752 2006-02-10  Nick Clifton  <nickc@redhat.com>
 753
 754         * iq2000-asm.c: Regenerate.
 755
 756 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 757
 758         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 759
 760 2006-01-26  David Ung  <davidu@mips.com>
 761
 762         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 763         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 764         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 765         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 766         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 767
 768 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 769
 770         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 771         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 772         disassembled.
 773         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 774         buffer overflows when disassembling instructions like
 775         ld (ix+123),0x23
 776         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 777         operand, if the offset is negative.
 778
 779 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 780
 781         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 782         unsigned char to hold data to be disassembled.
 783
 784 2006-01-17  Andreas Schwab  <schwab@suse.de>
 785
 786         PR binutils/1486
 787         * disassemble.c (disassemble_init_for_target): Set
 788         disassembler_needs_relocs for bfd_arch_arm.
 789
 790 2006-01-16  Paul Brook  <paul@codesourcery.com>
 791
 792         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 793         f?add?, and f?sub? instructions.
 794
 795 2006-01-16  Nick Clifton  <nickc@redhat.com>
 796
 797         * po/zh_CN.po: New Chinese (simplified) translation.
 798         * configure.in (ALL_LINGUAS): Add "zh_CH".
 799         * configure: Regenerate.
 800
 801 2006-01-05  Paul Brook  <paul@codesourcery.com>
 802
 803         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 804
 805 2006-01-06  DJ Delorie  <dj@redhat.com>
 806
 807         * m32c-desc.c: Regenerate.
 808         * m32c-opc.c: Regenerate.
 809         * m32c-opc.h: Regenerate.
 810
 811 2006-01-03  DJ Delorie  <dj@redhat.com>
 812
 813         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 814         * m32c-ibld.c: Regenerated.
 815
 816 For older changes see ChangeLog-2005
 817 \f
 818 Local Variables:
 819 mode: change-log
 820 left-margin: 8
 821 fill-column: 74
 822 version-control: never
 823 End: