1 2020-05-11 Alan Modra <amodra@gmail.com>
3 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
4 xxgenpcvwm, xxgenpcvdm.
6 2020-05-11 Alan Modra <amodra@gmail.com>
8 * ppc-opc.c (MP, VXVAM_MASK): Define.
9 (VXVAPS_MASK): Use VXVA_MASK.
10 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
11 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
12 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
13 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
15 2020-05-11 Alan Modra <amodra@gmail.com>
16 Peter Bergner <bergner@linux.ibm.com>
18 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
20 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
21 YMSK2, XA6a, XA6ap, XB6a entries.
22 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
23 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
25 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
26 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
27 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
28 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
29 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
30 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
31 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
32 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
33 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
34 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
35 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
36 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
37 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
38 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
40 2020-05-11 Alan Modra <amodra@gmail.com>
42 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
43 (insert_xts, extract_xts): New functions.
44 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
45 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
46 (VXRC_MASK, VXSH_MASK): Define.
47 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
48 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
49 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
50 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
51 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
52 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
53 xxblendvh, xxblendvw, xxblendvd, xxpermx.
55 2020-05-11 Alan Modra <amodra@gmail.com>
57 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
58 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
59 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
60 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
61 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
63 2020-05-11 Alan Modra <amodra@gmail.com>
65 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
66 (XTP, DQXP, DQXP_MASK): Define.
67 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
68 (prefix_opcodes): Add plxvp and pstxvp.
70 2020-05-11 Alan Modra <amodra@gmail.com>
72 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
73 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
74 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
76 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
78 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
80 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
82 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
84 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
86 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
88 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
90 2020-05-11 Alan Modra <amodra@gmail.com>
92 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
94 2020-05-11 Alan Modra <amodra@gmail.com>
96 * ppc-dis.c (ppc_opts): Add "power10" entry.
97 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
98 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
100 2020-05-11 Nick Clifton <nickc@redhat.com>
102 * po/fr.po: Updated French translation.
104 2020-04-30 Alex Coplan <alex.coplan@arm.com>
106 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
107 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
108 (operand_general_constraint_met_p): validate
109 AARCH64_OPND_UNDEFINED.
110 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
112 * aarch64-asm-2.c: Regenerated.
113 * aarch64-dis-2.c: Regenerated.
114 * aarch64-opc-2.c: Regenerated.
116 2020-04-29 Nick Clifton <nickc@redhat.com>
119 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
122 2020-04-29 Nick Clifton <nickc@redhat.com>
124 * po/sv.po: Updated Swedish translation.
126 2020-04-29 Nick Clifton <nickc@redhat.com>
129 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
130 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
131 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
134 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
137 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
138 cmpi only on m68020up and cpu32.
140 2020-04-20 Sudakshina Das <sudi.das@arm.com>
142 * aarch64-asm.c (aarch64_ins_none): New.
143 * aarch64-asm.h (ins_none): New declaration.
144 * aarch64-dis.c (aarch64_ext_none): New.
145 * aarch64-dis.h (ext_none): New declaration.
146 * aarch64-opc.c (aarch64_print_operand): Update case for
147 AARCH64_OPND_BARRIER_PSB.
148 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
149 (AARCH64_OPERANDS): Update inserter/extracter for
150 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
151 * aarch64-asm-2.c: Regenerated.
152 * aarch64-dis-2.c: Regenerated.
153 * aarch64-opc-2.c: Regenerated.
155 2020-04-20 Sudakshina Das <sudi.das@arm.com>
157 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
158 (aarch64_feature_ras, RAS): Likewise.
159 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
160 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
161 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
162 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
163 * aarch64-asm-2.c: Regenerated.
164 * aarch64-dis-2.c: Regenerated.
165 * aarch64-opc-2.c: Regenerated.
167 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
169 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
170 (print_insn_neon): Support disassembly of conditional
173 2020-02-16 David Faust <david.faust@oracle.com>
175 * bpf-desc.c: Regenerate.
176 * bpf-desc.h: Likewise.
177 * bpf-opc.c: Regenerate.
178 * bpf-opc.h: Likewise.
180 2020-04-07 Lili Cui <lili.cui@intel.com>
182 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
183 (prefix_table): New instructions (see prefixes above).
185 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
186 CPU_ANY_TSXLDTRK_FLAGS.
187 (cpu_flags): Add CpuTSXLDTRK.
188 * i386-opc.h (enum): Add CpuTSXLDTRK.
189 (i386_cpu_flags): Add cputsxldtrk.
190 * i386-opc.tbl: Add XSUSPLDTRK insns.
191 * i386-init.h: Regenerate.
192 * i386-tbl.h: Likewise.
194 2020-04-02 Lili Cui <lili.cui@intel.com>
196 * i386-dis.c (prefix_table): New instructions serialize.
197 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
198 CPU_ANY_SERIALIZE_FLAGS.
199 (cpu_flags): Add CpuSERIALIZE.
200 * i386-opc.h (enum): Add CpuSERIALIZE.
201 (i386_cpu_flags): Add cpuserialize.
202 * i386-opc.tbl: Add SERIALIZE insns.
203 * i386-init.h: Regenerate.
204 * i386-tbl.h: Likewise.
206 2020-03-26 Alan Modra <amodra@gmail.com>
208 * disassemble.h (opcodes_assert): Declare.
209 (OPCODES_ASSERT): Define.
210 * disassemble.c: Don't include assert.h. Include opintl.h.
211 (opcodes_assert): New function.
212 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
213 (bfd_h8_disassemble): Reduce size of data array. Correctly
214 calculate maxlen. Omit insn decoding when insn length exceeds
215 maxlen. Exit from nibble loop when looking for E, before
216 accessing next data byte. Move processing of E outside loop.
217 Replace tests of maxlen in loop with assertions.
219 2020-03-26 Alan Modra <amodra@gmail.com>
221 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
223 2020-03-25 Alan Modra <amodra@gmail.com>
225 * z80-dis.c (suffix): Init mybuf.
227 2020-03-22 Alan Modra <amodra@gmail.com>
229 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
230 successflly read from section.
232 2020-03-22 Alan Modra <amodra@gmail.com>
234 * arc-dis.c (find_format): Use ISO C string concatenation rather
235 than line continuation within a string. Don't access needs_limm
236 before testing opcode != NULL.
238 2020-03-22 Alan Modra <amodra@gmail.com>
240 * ns32k-dis.c (print_insn_arg): Update comment.
241 (print_insn_ns32k): Reduce size of index_offset array, and
242 initialize, passing -1 to print_insn_arg for args that are not
243 an index. Don't exit arg loop early. Abort on bad arg number.
245 2020-03-22 Alan Modra <amodra@gmail.com>
247 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
248 * s12z-opc.c: Formatting.
249 (operands_f): Return an int.
250 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
251 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
252 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
253 (exg_sex_discrim): Likewise.
254 (create_immediate_operand, create_bitfield_operand),
255 (create_register_operand_with_size, create_register_all_operand),
256 (create_register_all16_operand, create_simple_memory_operand),
257 (create_memory_operand, create_memory_auto_operand): Don't
258 segfault on malloc failure.
259 (z_ext24_decode): Return an int status, negative on fail, zero
261 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
262 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
263 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
264 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
265 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
266 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
267 (loop_primitive_decode, shift_decode, psh_pul_decode),
268 (bit_field_decode): Similarly.
269 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
270 to return value, update callers.
271 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
272 Don't segfault on NULL operand.
273 (decode_operation): Return OP_INVALID on first fail.
274 (decode_s12z): Check all reads, returning -1 on fail.
276 2020-03-20 Alan Modra <amodra@gmail.com>
278 * metag-dis.c (print_insn_metag): Don't ignore status from
281 2020-03-20 Alan Modra <amodra@gmail.com>
283 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
284 Initialize parts of buffer not written when handling a possible
285 2-byte insn at end of section. Don't attempt decoding of such
286 an insn by the 4-byte machinery.
288 2020-03-20 Alan Modra <amodra@gmail.com>
290 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
291 partially filled buffer. Prevent lookup of 4-byte insns when
292 only VLE 2-byte insns are possible due to section size. Print
293 ".word" rather than ".long" for 2-byte leftovers.
295 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
298 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
300 2020-03-13 Jan Beulich <jbeulich@suse.com>
302 * i386-dis.c (X86_64_0D): Rename to ...
303 (X86_64_0E): ... this.
305 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
307 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
308 * Makefile.in: Regenerated.
310 2020-03-09 Jan Beulich <jbeulich@suse.com>
312 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
314 * i386-tbl.h: Re-generate.
316 2020-03-09 Jan Beulich <jbeulich@suse.com>
318 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
319 vprot*, vpsha*, and vpshl*.
320 * i386-tbl.h: Re-generate.
322 2020-03-09 Jan Beulich <jbeulich@suse.com>
324 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
325 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
326 * i386-tbl.h: Re-generate.
328 2020-03-09 Jan Beulich <jbeulich@suse.com>
330 * i386-gen.c (set_bitfield): Ignore zero-length field names.
331 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
332 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
333 * i386-tbl.h: Re-generate.
335 2020-03-09 Jan Beulich <jbeulich@suse.com>
337 * i386-gen.c (struct template_arg, struct template_instance,
338 struct template_param, struct template, templates,
339 parse_template, expand_templates): New.
340 (process_i386_opcodes): Various local variables moved to
341 expand_templates. Call parse_template and expand_templates.
342 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
343 * i386-tbl.h: Re-generate.
345 2020-03-06 Jan Beulich <jbeulich@suse.com>
347 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
348 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
349 register and memory source templates. Replace VexW= by VexW*
351 * i386-tbl.h: Re-generate.
353 2020-03-06 Jan Beulich <jbeulich@suse.com>
355 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
356 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
357 * i386-tbl.h: Re-generate.
359 2020-03-06 Jan Beulich <jbeulich@suse.com>
361 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
362 * i386-tbl.h: Re-generate.
364 2020-03-06 Jan Beulich <jbeulich@suse.com>
366 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
367 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
368 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
369 VexW0 on SSE2AVX variants.
370 (vmovq): Drop NoRex64 from XMM/XMM variants.
371 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
372 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
373 applicable use VexW0.
374 * i386-tbl.h: Re-generate.
376 2020-03-06 Jan Beulich <jbeulich@suse.com>
378 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
379 * i386-opc.h (Rex64): Delete.
380 (struct i386_opcode_modifier): Remove rex64 field.
381 * i386-opc.tbl (crc32): Drop Rex64.
382 Replace Rex64 with Size64 everywhere else.
383 * i386-tbl.h: Re-generate.
385 2020-03-06 Jan Beulich <jbeulich@suse.com>
387 * i386-dis.c (OP_E_memory): Exclude recording of used address
388 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
389 addressed memory operands for MPX insns.
391 2020-03-06 Jan Beulich <jbeulich@suse.com>
393 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
394 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
395 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
396 (ptwrite): Split into non-64-bit and 64-bit forms.
397 * i386-tbl.h: Re-generate.
399 2020-03-06 Jan Beulich <jbeulich@suse.com>
401 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
403 * i386-tbl.h: Re-generate.
405 2020-03-04 Jan Beulich <jbeulich@suse.com>
407 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
408 (prefix_table): Move vmmcall here. Add vmgexit.
409 (rm_table): Replace vmmcall entry by prefix_table[] escape.
410 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
411 (cpu_flags): Add CpuSEV_ES entry.
412 * i386-opc.h (CpuSEV_ES): New.
413 (union i386_cpu_flags): Add cpusev_es field.
414 * i386-opc.tbl (vmgexit): New.
415 * i386-init.h, i386-tbl.h: Re-generate.
417 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
419 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
421 * i386-opc.h (IGNORESIZE): New.
422 (DEFAULTSIZE): Likewise.
423 (IgnoreSize): Removed.
424 (DefaultSize): Likewise.
426 (i386_opcode_modifier): Replace ignoresize/defaultsize with
428 * i386-opc.tbl (IgnoreSize): New.
429 (DefaultSize): Likewise.
430 * i386-tbl.h: Regenerated.
432 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
435 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
438 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
441 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
442 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
443 * i386-tbl.h: Regenerated.
445 2020-02-26 Alan Modra <amodra@gmail.com>
447 * aarch64-asm.c: Indent labels correctly.
448 * aarch64-dis.c: Likewise.
449 * aarch64-gen.c: Likewise.
450 * aarch64-opc.c: Likewise.
451 * alpha-dis.c: Likewise.
452 * i386-dis.c: Likewise.
453 * nds32-asm.c: Likewise.
454 * nfp-dis.c: Likewise.
455 * visium-dis.c: Likewise.
457 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
459 * arc-regs.h (int_vector_base): Make it available for all ARC
462 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
464 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
467 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
469 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
470 c.mv/c.li if rs1 is zero.
472 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
474 * i386-gen.c (cpu_flag_init): Replace CpuABM with
475 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
477 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
478 * i386-opc.h (CpuABM): Removed.
480 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
481 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
482 popcnt. Remove CpuABM from lzcnt.
483 * i386-init.h: Regenerated.
484 * i386-tbl.h: Likewise.
486 2020-02-17 Jan Beulich <jbeulich@suse.com>
488 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
489 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
490 VexW1 instead of open-coding them.
491 * i386-tbl.h: Re-generate.
493 2020-02-17 Jan Beulich <jbeulich@suse.com>
495 * i386-opc.tbl (AddrPrefixOpReg): Define.
496 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
497 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
498 templates. Drop NoRex64.
499 * i386-tbl.h: Re-generate.
501 2020-02-17 Jan Beulich <jbeulich@suse.com>
504 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
505 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
506 into Intel syntax instance (with Unpsecified) and AT&T one
508 (vcvtneps2bf16): Likewise, along with folding the two so far
510 * i386-tbl.h: Re-generate.
512 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
514 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
517 2020-02-17 Alan Modra <amodra@gmail.com>
519 * i386-gen.c (cpu_flag_init): Correct last change.
521 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
523 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
526 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
528 * i386-opc.tbl (movsx): Remove Intel syntax comments.
531 2020-02-14 Jan Beulich <jbeulich@suse.com>
534 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
535 destination for Cpu64-only variant.
536 (movzx): Fold patterns.
537 * i386-tbl.h: Re-generate.
539 2020-02-13 Jan Beulich <jbeulich@suse.com>
541 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
542 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
543 CPU_ANY_SSE4_FLAGS entry.
544 * i386-init.h: Re-generate.
546 2020-02-12 Jan Beulich <jbeulich@suse.com>
548 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
549 with Unspecified, making the present one AT&T syntax only.
550 * i386-tbl.h: Re-generate.
552 2020-02-12 Jan Beulich <jbeulich@suse.com>
554 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
555 * i386-tbl.h: Re-generate.
557 2020-02-12 Jan Beulich <jbeulich@suse.com>
560 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
561 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
562 Amd64 and Intel64 templates.
563 (call, jmp): Likewise for far indirect variants. Dro
565 * i386-tbl.h: Re-generate.
567 2020-02-11 Jan Beulich <jbeulich@suse.com>
569 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
570 * i386-opc.h (ShortForm): Delete.
571 (struct i386_opcode_modifier): Remove shortform field.
572 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
573 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
574 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
575 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
577 * i386-tbl.h: Re-generate.
579 2020-02-11 Jan Beulich <jbeulich@suse.com>
581 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
582 fucompi): Drop ShortForm from operand-less templates.
583 * i386-tbl.h: Re-generate.
585 2020-02-11 Alan Modra <amodra@gmail.com>
587 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
588 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
589 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
590 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
591 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
593 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
595 * arm-dis.c (print_insn_cde): Define 'V' parse character.
596 (cde_opcodes): Add VCX* instructions.
598 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
599 Matthew Malcomson <matthew.malcomson@arm.com>
601 * arm-dis.c (struct cdeopcode32): New.
602 (CDE_OPCODE): New macro.
603 (cde_opcodes): New disassembly table.
604 (regnames): New option to table.
605 (cde_coprocs): New global variable.
606 (print_insn_cde): New
607 (print_insn_thumb32): Use print_insn_cde.
608 (parse_arm_disassembler_options): Parse coprocN args.
610 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
613 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
615 * i386-opc.h (AMD64): Removed.
619 (INTEL64ONLY): Likewise.
620 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
621 * i386-opc.tbl (Amd64): New.
623 (Intel64Only): Likewise.
624 Replace AMD64 with Amd64. Update sysenter/sysenter with
625 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
626 * i386-tbl.h: Regenerated.
628 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
631 * z80-dis.c: Add support for GBZ80 opcodes.
633 2020-02-04 Alan Modra <amodra@gmail.com>
635 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
637 2020-02-03 Alan Modra <amodra@gmail.com>
639 * m32c-ibld.c: Regenerate.
641 2020-02-01 Alan Modra <amodra@gmail.com>
643 * frv-ibld.c: Regenerate.
645 2020-01-31 Jan Beulich <jbeulich@suse.com>
647 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
648 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
649 (OP_E_memory): Replace xmm_mdq_mode case label by
650 vex_scalar_w_dq_mode one.
651 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
653 2020-01-31 Jan Beulich <jbeulich@suse.com>
655 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
656 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
657 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
658 (intel_operand_size): Drop vex_w_dq_mode case label.
660 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
662 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
663 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
665 2020-01-30 Alan Modra <amodra@gmail.com>
667 * m32c-ibld.c: Regenerate.
669 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
671 * bpf-opc.c: Regenerate.
673 2020-01-30 Jan Beulich <jbeulich@suse.com>
675 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
676 (dis386): Use them to replace C2/C3 table entries.
677 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
678 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
679 ones. Use Size64 instead of DefaultSize on Intel64 ones.
680 * i386-tbl.h: Re-generate.
682 2020-01-30 Jan Beulich <jbeulich@suse.com>
684 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
686 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
688 * i386-tbl.h: Re-generate.
690 2020-01-30 Alan Modra <amodra@gmail.com>
692 * tic4x-dis.c (tic4x_dp): Make unsigned.
694 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
695 Jan Beulich <jbeulich@suse.com>
698 * i386-dis.c (MOVSXD_Fixup): New function.
699 (movsxd_mode): New enum.
700 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
701 (intel_operand_size): Handle movsxd_mode.
702 (OP_E_register): Likewise.
704 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
705 register on movsxd. Add movsxd with 16-bit destination register
706 for AMD64 and Intel64 ISAs.
707 * i386-tbl.h: Regenerated.
709 2020-01-27 Tamar Christina <tamar.christina@arm.com>
712 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
713 * aarch64-asm-2.c: Regenerate
714 * aarch64-dis-2.c: Likewise.
715 * aarch64-opc-2.c: Likewise.
717 2020-01-21 Jan Beulich <jbeulich@suse.com>
719 * i386-opc.tbl (sysret): Drop DefaultSize.
720 * i386-tbl.h: Re-generate.
722 2020-01-21 Jan Beulich <jbeulich@suse.com>
724 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
726 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
727 * i386-tbl.h: Re-generate.
729 2020-01-20 Nick Clifton <nickc@redhat.com>
731 * po/de.po: Updated German translation.
732 * po/pt_BR.po: Updated Brazilian Portuguese translation.
733 * po/uk.po: Updated Ukranian translation.
735 2020-01-20 Alan Modra <amodra@gmail.com>
737 * hppa-dis.c (fput_const): Remove useless cast.
739 2020-01-20 Alan Modra <amodra@gmail.com>
741 * arm-dis.c (print_insn_arm): Wrap 'T' value.
743 2020-01-18 Nick Clifton <nickc@redhat.com>
745 * configure: Regenerate.
746 * po/opcodes.pot: Regenerate.
748 2020-01-18 Nick Clifton <nickc@redhat.com>
750 Binutils 2.34 branch created.
752 2020-01-17 Christian Biesinger <cbiesinger@google.com>
754 * opintl.h: Fix spelling error (seperate).
756 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
758 * i386-opc.tbl: Add {vex} pseudo prefix.
759 * i386-tbl.h: Regenerated.
761 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
764 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
765 (neon_opcodes): Likewise.
766 (select_arm_features): Make sure we enable MVE bits when selecting
767 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
770 2020-01-16 Jan Beulich <jbeulich@suse.com>
772 * i386-opc.tbl: Drop stale comment from XOP section.
774 2020-01-16 Jan Beulich <jbeulich@suse.com>
776 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
777 (extractps): Add VexWIG to SSE2AVX forms.
778 * i386-tbl.h: Re-generate.
780 2020-01-16 Jan Beulich <jbeulich@suse.com>
782 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
783 Size64 from and use VexW1 on SSE2AVX forms.
784 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
785 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
786 * i386-tbl.h: Re-generate.
788 2020-01-15 Alan Modra <amodra@gmail.com>
790 * tic4x-dis.c (tic4x_version): Make unsigned long.
791 (optab, optab_special, registernames): New file scope vars.
792 (tic4x_print_register): Set up registernames rather than
793 malloc'd registertable.
794 (tic4x_disassemble): Delete optable and optable_special. Use
795 optab and optab_special instead. Throw away old optab,
796 optab_special and registernames when info->mach changes.
798 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
801 * z80-dis.c (suffix): Use .db instruction to generate double
804 2020-01-14 Alan Modra <amodra@gmail.com>
806 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
807 values to unsigned before shifting.
809 2020-01-13 Thomas Troeger <tstroege@gmx.de>
811 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
813 (print_insn_thumb16, print_insn_thumb32): Likewise.
814 (print_insn): Initialize the insn info.
815 * i386-dis.c (print_insn): Initialize the insn info fields, and
818 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
820 * arc-opc.c (C_NE): Make it required.
822 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
824 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
825 reserved register name.
827 2020-01-13 Alan Modra <amodra@gmail.com>
829 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
830 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
832 2020-01-13 Alan Modra <amodra@gmail.com>
834 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
835 result of wasm_read_leb128 in a uint64_t and check that bits
836 are not lost when copying to other locals. Use uint32_t for
837 most locals. Use PRId64 when printing int64_t.
839 2020-01-13 Alan Modra <amodra@gmail.com>
841 * score-dis.c: Formatting.
842 * score7-dis.c: Formatting.
844 2020-01-13 Alan Modra <amodra@gmail.com>
846 * score-dis.c (print_insn_score48): Use unsigned variables for
847 unsigned values. Don't left shift negative values.
848 (print_insn_score32): Likewise.
849 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
851 2020-01-13 Alan Modra <amodra@gmail.com>
853 * tic4x-dis.c (tic4x_print_register): Remove dead code.
855 2020-01-13 Alan Modra <amodra@gmail.com>
857 * fr30-ibld.c: Regenerate.
859 2020-01-13 Alan Modra <amodra@gmail.com>
861 * xgate-dis.c (print_insn): Don't left shift signed value.
862 (ripBits): Formatting, use 1u.
864 2020-01-10 Alan Modra <amodra@gmail.com>
866 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
867 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
869 2020-01-10 Alan Modra <amodra@gmail.com>
871 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
872 and XRREG value earlier to avoid a shift with negative exponent.
873 * m10200-dis.c (disassemble): Similarly.
875 2020-01-09 Nick Clifton <nickc@redhat.com>
878 * z80-dis.c (ld_ii_ii): Use correct cast.
880 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
883 * z80-dis.c (ld_ii_ii): Use character constant when checking
886 2020-01-09 Jan Beulich <jbeulich@suse.com>
888 * i386-dis.c (SEP_Fixup): New.
890 (dis386_twobyte): Use it for sysenter/sysexit.
891 (enum x86_64_isa): Change amd64 enumerator to value 1.
892 (OP_J): Compare isa64 against intel64 instead of amd64.
893 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
895 * i386-tbl.h: Re-generate.
897 2020-01-08 Alan Modra <amodra@gmail.com>
899 * z8k-dis.c: Include libiberty.h
900 (instr_data_s): Make max_fetched unsigned.
901 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
902 Don't exceed byte_info bounds.
903 (output_instr): Make num_bytes unsigned.
904 (unpack_instr): Likewise for nibl_count and loop.
905 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
907 * z8k-opc.h: Regenerate.
909 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
911 * arc-tbl.h (llock): Use 'LLOCK' as class.
913 (scond): Use 'SCOND' as class.
915 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
918 2020-01-06 Alan Modra <amodra@gmail.com>
920 * m32c-ibld.c: Regenerate.
922 2020-01-06 Alan Modra <amodra@gmail.com>
925 * z80-dis.c (suffix): Don't use a local struct buffer copy.
926 Peek at next byte to prevent recursion on repeated prefix bytes.
927 Ensure uninitialised "mybuf" is not accessed.
928 (print_insn_z80): Don't zero n_fetch and n_used here,..
929 (print_insn_z80_buf): ..do it here instead.
931 2020-01-04 Alan Modra <amodra@gmail.com>
933 * m32r-ibld.c: Regenerate.
935 2020-01-04 Alan Modra <amodra@gmail.com>
937 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
939 2020-01-04 Alan Modra <amodra@gmail.com>
941 * crx-dis.c (match_opcode): Avoid shift left of signed value.
943 2020-01-04 Alan Modra <amodra@gmail.com>
945 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
947 2020-01-03 Jan Beulich <jbeulich@suse.com>
949 * aarch64-tbl.h (aarch64_opcode_table): Use
950 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
952 2020-01-03 Jan Beulich <jbeulich@suse.com>
954 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
955 forms of SUDOT and USDOT.
957 2020-01-03 Jan Beulich <jbeulich@suse.com>
959 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
961 * opcodes/aarch64-dis-2.c: Re-generate.
963 2020-01-03 Jan Beulich <jbeulich@suse.com>
965 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
967 * opcodes/aarch64-dis-2.c: Re-generate.
969 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
971 * z80-dis.c: Add support for eZ80 and Z80 instructions.
973 2020-01-01 Alan Modra <amodra@gmail.com>
975 Update year range in copyright notice of all files.
977 For older changes see ChangeLog-2019
979 Copyright (C) 2020 Free Software Foundation, Inc.
981 Copying and distribution of this file, with or without modification,
982 are permitted in any medium without royalty provided the copyright
983 notice and this notice are preserved.
989 version-control: never