opcodes/ChangeLog

   1 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
   2             Vineet Sharma      <vineets@noida.hcltech.com>
   3
   4         * maxq-dis.c: New file.
   5         * disassemble.c (ARCH_maxq): Define.
   6         (disassembler): Add 'print_insn_maxq_little' for handling maxq
   7         instructions..
   8         * configure.in: Add case for bfd_maxq_arch.
   9         * configure: Regenerate.
  10         * Makefile.am: Add support for maxq-dis.c
  11         * Makefile.in: Regenerate.
  12         * aclocal.m4: Regenerate.
  13
  14 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  15
  16         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
  17         mode.
  18         * crx-dis.c: Likewise.
  19
  20 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  21
  22         Generally, handle CRISv32.
  23         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
  24         (struct cris_disasm_data): New type.
  25         (format_reg, format_hex, cris_constraint, print_flags)
  26         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
  27         callers changed.
  28         (format_sup_reg, print_insn_crisv32_with_register_prefix)
  29         (print_insn_crisv32_without_register_prefix)
  30         (print_insn_crisv10_v32_with_register_prefix)
  31         (print_insn_crisv10_v32_without_register_prefix)
  32         (cris_parse_disassembler_options): New functions.
  33         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
  34         parameter.  All callers changed.
  35         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
  36         failure.
  37         (cris_constraint) <case 'Y', 'U'>: New cases.
  38         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
  39         for constraint 'n'.
  40         (print_with_operands) <case 'Y'>: New case.
  41         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
  42         <case 'N', 'Y', 'Q'>: New cases.
  43         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
  44         (print_insn_cris_with_register_prefix)
  45         (print_insn_cris_without_register_prefix): Call
  46         cris_parse_disassembler_options.
  47         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
  48         for CRISv32 and the size of immediate operands.  New v32-only
  49         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
  50         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
  51         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
  52         Change brp to be v3..v10.
  53         (cris_support_regs): New vector.
  54         (cris_opcodes): Update head comment.  New format characters '[',
  55         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
  56         Add new opcodes for v32 and adjust existing opcodes to accommodate
  57         differences to earlier variants.
  58         (cris_cond15s): New vector.
  59
  60 2004-11-04 Jan Beulich <jbeulich@novell.com>
  61
  62         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
  63         (indirEb): Remove.
  64         (Mp): Use f_mode rather than none at all.
  65         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
  66         replaces what previously was x_mode; x_mode now means 128-bit SSE
  67         operands.
  68         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
  69         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
  70         pinsrw's second operand is Edqw.
  71         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
  72         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
  73         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
  74         mode when an operand size override is present or always suffixing.
  75         More instructions will need to be added to this group.
  76         (putop): Handle new macro chars 'C' (short/long suffix selector),
  77         'I' (Intel mode override for following macro char), and 'J' (for
  78         adding the 'l' prefix to far branches in AT&T mode). When an
  79         alternative was specified in the template, honor macro character when
  80         specified for Intel mode.
  81         (OP_E): Handle new *_mode values. Correct pointer specifications for
  82         memory operands. Consolidate output of index register.
  83         (OP_G): Handle new *_mode values.
  84         (OP_I): Handle const_1_mode.
  85         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
  86         respective opcode prefix bits have been consumed.
  87         (OP_EM, OP_EX): Provide some default handling for generating pointer
  88         specifications.
  89
  90 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
  91
  92         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
  93         COP_INST macro.
  94
  95 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  96
  97         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
  98         (getregliststring): Support HI/LO and user registers.
  99         * crx-opc.c (crx_instruction): Update data structure according to the
 100         rearrangement done in CRX opcode header file.
 101         (crx_regtab):  Likewise.
 102         (crx_optab):  Likewise.
 103         (crx_instruction): Reorder load/stor instructions, remove unsupported
 104         formats.
 105         support new Co-Processor instruction 'cpi'.
 106
 107 2004-10-27  Nick Clifton  <nickc@redhat.com>
 108
 109         * opcodes/iq2000-asm.c: Regenerate.
 110         * opcodes/iq2000-desc.c: Regenerate.
 111         * opcodes/iq2000-desc.h: Regenerate.
 112         * opcodes/iq2000-dis.c: Regenerate.
 113         * opcodes/iq2000-ibld.c: Regenerate.
 114         * opcodes/iq2000-opc.c: Regenerate.
 115         * opcodes/iq2000-opc.h: Regenerate.
 116
 117 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 118
 119         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 120         us4, us5 (respectively).
 121         Remove unsupported 'popa' instruction.
 122         Reverse operands order in store co-processor instructions.
 123
 124 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 125
 126         * Makefile.am: Run "make dep-am"
 127         * Makefile.in: Regenerate.
 128
 129 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 130
 131         * xtensa-dis.c: Use ISO C90 formatting.
 132
 133 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 134
 135         * ppc-opc.c: Revert 2004-09-09 change.
 136
 137 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 138
 139         * xtensa-dis.c (state_names): Delete.
 140         (fetch_data): Use xtensa_isa_maxlength.
 141         (print_xtensa_operand): Replace operand parameter with opcode/operand
 142         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 143         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 144         instruction bundles.  Use xmalloc instead of malloc.
 145
 146 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 147
 148         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 149         initializers.
 150
 151 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 152
 153         * crx-opc.c (crx_instruction): Support Co-processor insns.
 154         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 155         (getregliststring): Change function to use the above enum.
 156         (print_arg): Handle CO-Processor insns.
 157         (crx_cinvs): Add 'b' option to invalidate the branch-target
 158         cache.
 159
 160 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 161
 162         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 163         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 164         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 165         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 166         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 167
 168 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 169
 170         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 171         rather than add it.
 172
 173 2004-09-30  Paul Brook  <paul@codesourcery.com>
 174
 175         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 176         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 177
 178 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 179
 180         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 181         (CONFIG_STATUS_DEPENDENCIES): New.
 182         (Makefile): Removed.
 183         (config.status): Likewise.
 184         * Makefile.in: Regenerated.
 185
 186 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 187
 188         * Makefile.am: Run "make dep-am".
 189         * Makefile.in: Regenerate.
 190         * aclocal.m4: Regenerate.
 191         * configure: Regenerate.
 192         * po/POTFILES.in: Regenerate.
 193         * po/opcodes.pot: Regenerate.
 194
 195 2004-09-11  Andreas Schwab  <schwab@suse.de>
 196
 197         * configure: Rebuild.
 198
 199 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 200
 201         * ppc-opc.c (L): Make this field not optional.
 202
 203 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 204
 205         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 206         Fix parameter to 'm[t|f]csr' insns.
 207
 208 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 209
 210         * configure.in: Autoupdate to autoconf 2.59.
 211         * aclocal.m4: Rebuild with aclocal 1.4p6.
 212         * configure: Rebuild with autoconf 2.59.
 213         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 214         bfd changes for autoconf 2.59 on the way).
 215         * config.in: Rebuild with autoheader 2.59.
 216
 217 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 218
 219         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 220
 221 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 222
 223         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 224         (GRPPADLCK2): New define.
 225         (twobyte_has_modrm): True for 0xA6.
 226         (grps): GRPPADLCK2 for opcode 0xA6.
 227
 228 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 229
 230         Introduce SH2a support.
 231         * sh-opc.h (arch_sh2a_base): Renumber.
 232         (arch_sh2a_nofpu_base): Remove.
 233         (arch_sh_base_mask): Adjust.
 234         (arch_opann_mask): New.
 235         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 236         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 237         (sh_table): Adjust whitespace.
 238         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 239         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 240         instruction list throughout.
 241         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 242         of arch_sh2a in instruction list throughout.
 243         (arch_sh2e_up): Accomodate above changes.
 244         (arch_sh2_up): Ditto.
 245         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 246         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 247         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 248         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 249         * sh-opc.h (arch_sh2a_nofpu): New.
 250         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 251         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 252         instruction.
 253         2004-01-20  DJ Delorie  <dj@redhat.com>
 254         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 255         2003-12-29  DJ Delorie  <dj@redhat.com>
 256         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 257         sh_opcode_info, sh_table): Add sh2a support.
 258         (arch_op32): New, to tag 32-bit opcodes.
 259         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 260         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 261         * sh-opc.h (arch_sh2a): Add.
 262         * sh-dis.c (arch_sh2a): Handle.
 263         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 264
 265 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 266
 267         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 268
 269 2004-07-22  Nick Clifton  <nickc@redhat.com>
 270
 271         PR/280
 272         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 273         insns - this is done by objdump itself.
 274         * h8500-dis.c (print_insn_h8500): Likewise.
 275
 276 2004-07-21  Jan Beulich <jbeulich@novell.com>
 277
 278         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 279         regardless of address size prefix in effect.
 280         (ptr_reg): Size or address registers does not depend on rex64, but
 281         on the presence of an address size override.
 282         (OP_MMX): Use rex.x only for xmm registers.
 283         (OP_EM): Use rex.z only for xmm registers.
 284
 285 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 286
 287         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 288         move/branch operations to the bottom so that VR5400 multimedia
 289         instructions take precedence in disassembly.
 290
 291 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 292
 293         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 294         ISA-specific "break" encoding.
 295
 296 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 297
 298         * arm-opc.h: Fix typo in comment.
 299
 300 2004-07-11  Andreas Schwab  <schwab@suse.de>
 301
 302         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 303
 304 2004-07-09  Andreas Schwab  <schwab@suse.de>
 305
 306         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 307
 308 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 309
 310         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 311         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 312         (crx-dis.lo): New target.
 313         (crx-opc.lo): Likewise.
 314         * Makefile.in: Regenerate.
 315         * configure.in: Handle bfd_crx_arch.
 316         * configure: Regenerate.
 317         * crx-dis.c: New file.
 318         * crx-opc.c: New file.
 319         * disassemble.c (ARCH_crx): Define.
 320         (disassembler): Handle ARCH_crx.
 321
 322 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 323
 324         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 325         * ia64-asmtab.c: Regnerate.
 326
 327 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 328
 329         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 330         (extract_fxm): Don't test dialect.
 331         (XFXFXM_MASK): Include the power4 bit.
 332         (XFXM): Add p4 param.
 333         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 334
 335 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 336
 337         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 338         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 339
 340 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 341
 342         * ppc-opc.c (BH, XLBH_MASK): Define.
 343         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 344
 345 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 346
 347         * i386-dis.c (x_mode): Comment.
 348         (two_source_ops): File scope.
 349         (float_mem): Correct fisttpll and fistpll.
 350         (float_mem_mode): New table.
 351         (dofloat): Use it.
 352         (OP_E): Correct intel mode PTR output.
 353         (ptr_reg): Use open_char and close_char.
 354         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 355         operands.  Set two_source_ops.
 356
 357 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 358
 359         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 360         instead of _raw_size.
 361
 362 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 363
 364         * ia64-gen.c (in_iclass): Handle more postinc st
 365         and ld variants.
 366         * ia64-asmtab.c: Rebuilt.
 367
 368 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 369
 370         * s390-opc.txt: Correct architecture mask for some opcodes.
 371         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 372         in the esa mode as well.
 373
 374 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 375
 376         * sh-dis.c (target_arch): Make unsigned.
 377         (print_insn_sh): Replace (most of) switch with a call to
 378         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 379         * sh-opc.h: Redefine architecture flags values.
 380         Add sh3-nommu architecture.
 381         Reorganise <arch>_up macros so they make more visual sense.
 382         (SH_MERGE_ARCH_SET): Define new macro.
 383         (SH_VALID_BASE_ARCH_SET): Likewise.
 384         (SH_VALID_MMU_ARCH_SET): Likewise.
 385         (SH_VALID_CO_ARCH_SET): Likewise.
 386         (SH_VALID_ARCH_SET): Likewise.
 387         (SH_MERGE_ARCH_SET_VALID): Likewise.
 388         (SH_ARCH_SET_HAS_FPU): Likewise.
 389         (SH_ARCH_SET_HAS_DSP): Likewise.
 390         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 391         (sh_get_arch_from_bfd_mach): Add prototype.
 392         (sh_get_arch_up_from_bfd_mach): Likewise.
 393         (sh_get_bfd_mach_from_arch_set): Likewise.
 394         (sh_merge_bfd_arc): Likewise.
 395
 396 2004-05-24  Peter Barada  <peter@the-baradas.com>
 397
 398         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 399         into new match_insn_m68k function.  Loop over canidate
 400         matches and select first that completely matches.
 401         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 402         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 403         to verify addressing for MAC/EMAC.
 404         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 405         reigster halves since 'fpu' and 'spl' look misleading.
 406         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 407         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 408         first, tighten up match masks.
 409         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 410         'size' from special case code in print_insn_m68k to
 411         determine decode size of insns.
 412
 413 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 414
 415         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 416         well as when -mpower4.
 417
 418 2004-05-13  Nick Clifton  <nickc@redhat.com>
 419
 420         * po/fr.po: Updated French translation.
 421
 422 2004-05-05  Peter Barada  <peter@the-baradas.com>
 423
 424         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 425         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 426         * m68k-op.c: Switch from ColdFire chips to core variants.
 427
 428 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 429
 430         PR 147.
 431         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 432
 433 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 434
 435         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 436         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 437
 438 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 439
 440         * sh-dis.c (print_insn_sh): Print the value in constant pool
 441         as a symbol if it looks like a symbol.
 442
 443 2004-04-22  Peter Barada <peter@the-baradas.com>
 444
 445         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 446         appropriate ColdFire architectures.
 447         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 448         mask addressing.
 449         Add EMAC instructions, fix MAC instructions. Remove
 450         macmw/macml/msacmw/msacml instructions since mask addressing now
 451         supported.
 452
 453 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 454
 455         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 456         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 457         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 458         macro.  Adjust all users.
 459
 460 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 461
 462         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 463         separately.
 464
 465 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 466
 467         * m32r-asm.c: Regenerate.
 468
 469 2004-03-29  Stan Shebs  <shebs@apple.com>
 470
 471         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 472         used.
 473
 474 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 475
 476         * aclocal.m4: Regenerate.
 477         * config.in: Regenerate.
 478         * configure: Regenerate.
 479         * po/POTFILES.in: Regenerate.
 480         * po/opcodes.pot: Regenerate.
 481
 482 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 483
 484         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 485         PPC_OPERANDS_GPR_0.
 486         * ppc-opc.c (RA0): Define.
 487         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 488         (RAOPT): Rename from RAO.  Update all uses.
 489         (powerpc_opcodes): Use RA0 as appropriate.
 490
 491 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 492
 493         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 494
 495 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 496
 497         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 498
 499 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 500
 501         * i386-dis.c (GRPPLOCK): Delete.
 502         (grps): Delete GRPPLOCK entry.
 503
 504 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 505
 506         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 507         (M, Mp): Use OP_M.
 508         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 509         (GRPPADLCK): Define.
 510         (dis386): Use NOP_Fixup on "nop".
 511         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 512         (twobyte_has_modrm): Set for 0xa7.
 513         (padlock_table): Delete.  Move to..
 514         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 515         and clflush.
 516         (print_insn): Revert PADLOCK_SPECIAL code.
 517         (OP_E): Delete sfence, lfence, mfence checks.
 518
 519 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 520
 521         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 522         (INVLPG_Fixup): New function.
 523         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 524
 525 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 526
 527         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 528         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 529         (padlock_table): New struct with PadLock instructions.
 530         (print_insn): Handle PADLOCK_SPECIAL.
 531
 532 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 533
 534         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 535         (OP_E): Twiddle clflush to sfence here.
 536
 537 2004-03-08  Nick Clifton  <nickc@redhat.com>
 538
 539         * po/de.po: Updated German translation.
 540
 541 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 542
 543         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 544         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 545         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 546         accordingly.
 547
 548 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 549
 550         * frv-asm.c: Regenerate.
 551         * frv-desc.c: Regenerate.
 552         * frv-desc.h: Regenerate.
 553         * frv-dis.c: Regenerate.
 554         * frv-ibld.c: Regenerate.
 555         * frv-opc.c: Regenerate.
 556         * frv-opc.h: Regenerate.
 557
 558 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 559
 560         * frv-desc.c, frv-opc.c: Regenerate.
 561
 562 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 563
 564         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 565
 566 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 567
 568         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 569         Also correct mistake in the comment.
 570
 571 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 572
 573         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 574         ensure that double registers have even numbers.
 575         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 576         that reserved instruction 0xfffd does not decode the same
 577         as 0xfdfd (ftrv).
 578         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 579         REG_N refers to a double register.
 580         Add REG_N_B01 nibble type and use it instead of REG_NM
 581         in ftrv.
 582         Adjust the bit patterns in a few comments.
 583
 584 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 585
 586         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 587
 588 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 589
 590         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 591
 592 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 593
 594         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 595
 596 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 597
 598         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 599         mtivor32, mtivor33, mtivor34.
 600
 601 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 602
 603         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 604
 605 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 606
 607         * arm-opc.h Maverick accumulator register opcode fixes.
 608
 609 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 610
 611         * m32r-dis.c: Regenerate.
 612
 613 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 614
 615         * sh-opc.h (sh_table): "fsrra", not "fssra".
 616
 617 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 618
 619         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 620         contraints.
 621
 622 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 623
 624         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 625
 626 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 627
 628         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 629         1.  Don't print scale factor on AT&T mode when index missing.
 630
 631 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 632
 633         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 634         when loaded into XR registers.
 635
 636 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 637
 638         * frv-desc.h: Regenerate.
 639         * frv-desc.c: Regenerate.
 640         * frv-opc.c: Regenerate.
 641
 642 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 643
 644         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 645
 646 2004-01-09  Paul Brook  <paul@codesourcery.com>
 647
 648         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 649         specific opcodes.
 650
 651 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 652
 653         * Makefile.am (libopcodes_la_DEPENDENCIES)
 654         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 655         comment about the problem.
 656         * Makefile.in: Regenerate.
 657
 658 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 659
 660         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 661         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 662         cut&paste errors in shifting/truncating numerical operands.
 663         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 664         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 665         (parse_uslo16): Likewise.
 666         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 667         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 668         (parse_s12): Likewise.
 669         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 670         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 671         (parse_uslo16): Likewise.
 672         (parse_uhi16): Parse gothi and gotfuncdeschi.
 673         (parse_d12): Parse got12 and gotfuncdesc12.
 674         (parse_s12): Likewise.
 675
 676 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 677
 678         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 679         instruction which looks similar to an 'rla' instruction.
 680
 681 For older changes see ChangeLog-0203
 682 \f
 683 Local Variables:
 684 mode: change-log
 685 left-margin: 8
 686 fill-column: 74
 687 version-control: never
 688 End: