opcodes/ChangeLog

   1 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/24719
   4         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
   5         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
   6         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
   7         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
   8         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
   9         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
  10         EVEX_LEN_0F38C7_R_6_P_2_W_1.
  11         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
  12         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
  13         PREFIX_EVEX_0F38C6_REG_6 entries.
  14         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
  15         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
  16         EVEX_W_0F38C7_R_6_P_2 entries.
  17         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
  18         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
  19         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
  20         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
  21         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
  22         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
  23         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
  24
  25 2019-06-27  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
  28         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
  29         VEX_LEN_0F2D_P_3): Delete.
  30         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
  31         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
  32         (prefix_table): ... here.
  33
  34 2019-06-27  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-dis.c (Iq): Delete.
  37         (Id): New.
  38         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
  39         TBM insns.
  40         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
  41         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
  42         (OP_E_memory): Also honor needindex when deciding whether an
  43         address size prefix needs printing.
  44         (OP_I): Remove handling of q_mode. Add handling of d_mode.
  45
  46 2019-06-26  Jim Wilson  <jimw@sifive.com>
  47
  48         PR binutils/24739
  49         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
  50         Set info->display_endian to info->endian_code.
  51
  52 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  53
  54         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
  55         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
  56         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
  57         OPERAND_TYPE_ACC64 entries.
  58         * i386-init.h: Re-generate.
  59
  60 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
  63         Delete.
  64         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
  65         of dqa_mode.
  66         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
  67         entries here.
  68         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
  69         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
  70
  71 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
  74         variables.
  75
  76 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  77
  78         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
  79         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
  80         movnti.
  81         * i386-opc.tbl (movnti): Add IgnoreSize.
  82         * i386-tbl.h: Re-generate.
  83
  84 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.tbl (and): Mark Imm8S form for optimization.
  87         * i386-tbl.h: Re-generate.
  88
  89 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  90
  91         * i386-dis-evex.h: Break into ...
  92         * i386-dis-evex-len.h: New file.
  93         * i386-dis-evex-mod.h: Likewise.
  94         * i386-dis-evex-prefix.h: Likewise.
  95         * i386-dis-evex-reg.h: Likewise.
  96         * i386-dis-evex-w.h: Likewise.
  97         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
  98         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
  99         i386-dis-evex-mod.h.
 100
 101 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 102
 103         PR binutils/24700
 104         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 105         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 106         EVEX_W_0F385B_P_2.
 107         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 108         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 109         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 110         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 111         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 112         EVEX_LEN_0F385B_P_2_W_1.
 113         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 114         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 115         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 116         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 117         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 118         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 119         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 120         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 121         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 122         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 123
 124 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 125
 126         PR binutils/24691
 127         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 128         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 129         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 130         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 131         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 132         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 133         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 134         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 135         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 136         EVEX_LEN_0F3A43_P_2_W_1.
 137         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 138         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 139         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 140         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 141         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 142         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 143         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 144         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 145         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 146         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 147         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 148         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 149
 150 2019-06-14  Nick Clifton  <nickc@redhat.com>
 151
 152         * po/fr.po; Updated French translation.
 153
 154 2019-06-13  Stafford Horne  <shorne@gmail.com>
 155
 156         * or1k-asm.c: Regenerated.
 157         * or1k-desc.c: Regenerated.
 158         * or1k-desc.h: Regenerated.
 159         * or1k-dis.c: Regenerated.
 160         * or1k-ibld.c: Regenerated.
 161         * or1k-opc.c: Regenerated.
 162         * or1k-opc.h: Regenerated.
 163         * or1k-opinst.c: Regenerated.
 164
 165 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 166
 167         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 168
 169 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 170
 171         PR binutils/24633
 172         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 173         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 174         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 175         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 176         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 177         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 178         EVEX_LEN_0F3A1B_P_2_W_1.
 179         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 180         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 181         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 182         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 183         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 184         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 185         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 186         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 187
 188 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 189
 190         PR binutils/24626
 191         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 192         EVEX.vvvv when disassembling VEX and EVEX instructions.
 193         (OP_VEX): Set vex.register_specifier to 0 after readding
 194         vex.register_specifier.
 195         (OP_Vex_2src_1): Likewise.
 196         (OP_Vex_2src_2): Likewise.
 197         (OP_LWP_E): Likewise.
 198         (OP_EX_Vex): Don't check vex.register_specifier.
 199         (OP_XMM_Vex): Likewise.
 200
 201 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 202             Lili Cui  <lili.cui@intel.com>
 203
 204         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 205         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 206         instructions.
 207         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 208         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 209         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 210         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 211         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 212         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 213         * i386-init.h: Regenerated.
 214         * i386-tbl.h: Likewise.
 215
 216 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 217             Lili Cui  <lili.cui@intel.com>
 218
 219         * doc/c-i386.texi: Document enqcmd.
 220         * testsuite/gas/i386/enqcmd-intel.d: New file.
 221         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 222         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 223         * testsuite/gas/i386/enqcmd.d: Likewise.
 224         * testsuite/gas/i386/enqcmd.s: Likewise.
 225         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 226         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 227         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 228         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 229         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 230         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 231         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 232         and x86-64-enqcmd.
 233
 234 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 235
 236         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 237
 238 2019-06-03  Alan Modra  <amodra@gmail.com>
 239
 240         * ppc-dis.c (prefix_opcd_indices): Correct size.
 241
 242 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 243
 244         PR gas/24625
 245         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 246         Disp8ShiftVL.
 247         * i386-tbl.h: Regenerated.
 248
 249 2019-05-24  Alan Modra  <amodra@gmail.com>
 250
 251         * po/POTFILES.in: Regenerate.
 252
 253 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 254             Alan Modra  <amodra@gmail.com>
 255
 256         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 257         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 258         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 259         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 260         XTOP>): Define and add entries.
 261         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 262         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 263         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 264         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 265
 266 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 267             Alan Modra  <amodra@gmail.com>
 268
 269         * ppc-dis.c (ppc_opts): Add "future" entry.
 270         (PREFIX_OPCD_SEGS): Define.
 271         (prefix_opcd_indices): New array.
 272         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 273         (lookup_prefix): New function.
 274         (print_insn_powerpc): Handle 64-bit prefix instructions.
 275         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 276         (PMRR, POWERXX): Define.
 277         (prefix_opcodes): New instruction table.
 278         (prefix_num_opcodes): New constant.
 279
 280 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 281
 282         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 283         * configure: Regenerated.
 284         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 285         and cpu/bpf.opc.
 286         (HFILES): Add bpf-desc.h and bpf-opc.h.
 287         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 288         bpf-ibld.c and bpf-opc.c.
 289         (BPF_DEPS): Define.
 290         * Makefile.in: Regenerated.
 291         * disassemble.c (ARCH_bpf): Define.
 292         (disassembler): Add case for bfd_arch_bpf.
 293         (disassemble_init_for_target): Likewise.
 294         (enum epbf_isa_attr): Define.
 295         * disassemble.h: extern print_insn_bpf.
 296         * bpf-asm.c: Generated.
 297         * bpf-opc.h: Likewise.
 298         * bpf-opc.c: Likewise.
 299         * bpf-ibld.c: Likewise.
 300         * bpf-dis.c: Likewise.
 301         * bpf-desc.h: Likewise.
 302         * bpf-desc.c: Likewise.
 303
 304 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 305
 306         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 307         and VMSR with the new operands.
 308
 309 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 310
 311         * arm-dis.c (enum mve_instructions): New enum
 312         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 313         and cneg.
 314         (mve_opcodes): New instructions as above.
 315         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 316         csneg and csel.
 317         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 318
 319 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 320
 321         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 322         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 323         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 324         uqshl, urshrl and urshr.
 325         (is_mve_okay_in_it): Add new instructions to TRUE list.
 326         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 327         (print_insn_mve): Updated to accept new %j,
 328         %<bitfield>m and %<bitfield>n patterns.
 329
 330 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 331
 332         * mips-opc.c (mips_builtin_opcodes): Change source register
 333         constraint for DAUI.
 334
 335 2019-05-20  Nick Clifton  <nickc@redhat.com>
 336
 337         * po/fr.po: Updated French translation.
 338
 339 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 340             Michael Collison <michael.collison@arm.com>
 341
 342         * arm-dis.c (thumb32_opcodes): Add new instructions.
 343         (enum mve_instructions): Likewise.
 344         (enum mve_undefined): Add new reasons.
 345         (is_mve_encoding_conflict): Handle new instructions.
 346         (is_mve_undefined): Likewise.
 347         (is_mve_unpredictable): Likewise.
 348         (print_mve_undefined): Likewise.
 349         (print_mve_size): Likewise.
 350
 351 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 352             Michael Collison <michael.collison@arm.com>
 353
 354         * arm-dis.c (thumb32_opcodes): Add new instructions.
 355         (enum mve_instructions): Likewise.
 356         (is_mve_encoding_conflict): Handle new instructions.
 357         (is_mve_undefined): Likewise.
 358         (is_mve_unpredictable): Likewise.
 359         (print_mve_size): Likewise.
 360
 361 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 362             Michael Collison <michael.collison@arm.com>
 363
 364         * arm-dis.c (thumb32_opcodes): Add new instructions.
 365         (enum mve_instructions): Likewise.
 366         (is_mve_encoding_conflict): Likewise.
 367         (is_mve_unpredictable): Likewise.
 368         (print_mve_size): Likewise.
 369
 370 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 371             Michael Collison <michael.collison@arm.com>
 372
 373         * arm-dis.c (thumb32_opcodes): Add new instructions.
 374         (enum mve_instructions): Likewise.
 375         (is_mve_encoding_conflict): Handle new instructions.
 376         (is_mve_undefined): Likewise.
 377         (is_mve_unpredictable): Likewise.
 378         (print_mve_size): Likewise.
 379
 380 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 381             Michael Collison <michael.collison@arm.com>
 382
 383         * arm-dis.c (thumb32_opcodes): Add new instructions.
 384         (enum mve_instructions): Likewise.
 385         (is_mve_encoding_conflict): Handle new instructions.
 386         (is_mve_undefined): Likewise.
 387         (is_mve_unpredictable): Likewise.
 388         (print_mve_size): Likewise.
 389         (print_insn_mve): Likewise.
 390
 391 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 392             Michael Collison <michael.collison@arm.com>
 393
 394         * arm-dis.c (thumb32_opcodes): Add new instructions.
 395         (print_insn_thumb32): Handle new instructions.
 396
 397 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 398             Michael Collison <michael.collison@arm.com>
 399
 400         * arm-dis.c (enum mve_instructions): Add new instructions.
 401         (enum mve_undefined): Add new reasons.
 402         (is_mve_encoding_conflict): Handle new instructions.
 403         (is_mve_undefined): Likewise.
 404         (is_mve_unpredictable): Likewise.
 405         (print_mve_undefined): Likewise.
 406         (print_mve_size): Likewise.
 407         (print_mve_shift_n): Likewise.
 408         (print_insn_mve): Likewise.
 409
 410 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 411             Michael Collison <michael.collison@arm.com>
 412
 413         * arm-dis.c (enum mve_instructions): Add new instructions.
 414         (is_mve_encoding_conflict): Handle new instructions.
 415         (is_mve_unpredictable): Likewise.
 416         (print_mve_rotate): Likewise.
 417         (print_mve_size): Likewise.
 418         (print_insn_mve): Likewise.
 419
 420 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 421             Michael Collison <michael.collison@arm.com>
 422
 423         * arm-dis.c (enum mve_instructions): Add new instructions.
 424         (is_mve_encoding_conflict): Handle new instructions.
 425         (is_mve_unpredictable): Likewise.
 426         (print_mve_size): Likewise.
 427         (print_insn_mve): Likewise.
 428
 429 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 430             Michael Collison <michael.collison@arm.com>
 431
 432         * arm-dis.c (enum mve_instructions): Add new instructions.
 433         (enum mve_undefined): Add new reasons.
 434         (is_mve_encoding_conflict): Handle new instructions.
 435         (is_mve_undefined): Likewise.
 436         (is_mve_unpredictable): Likewise.
 437         (print_mve_undefined): Likewise.
 438         (print_mve_size): Likewise.
 439         (print_insn_mve): Likewise.
 440
 441 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 442             Michael Collison <michael.collison@arm.com>
 443
 444         * arm-dis.c (enum mve_instructions): Add new instructions.
 445         (is_mve_encoding_conflict): Handle new instructions.
 446         (is_mve_undefined): Likewise.
 447         (is_mve_unpredictable): Likewise.
 448         (print_mve_size): Likewise.
 449         (print_insn_mve): Likewise.
 450
 451 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 452             Michael Collison <michael.collison@arm.com>
 453
 454         * arm-dis.c (enum mve_instructions): Add new instructions.
 455         (enum mve_unpredictable): Add new reasons.
 456         (enum mve_undefined): Likewise.
 457         (is_mve_okay_in_it): Handle new isntructions.
 458         (is_mve_encoding_conflict): Likewise.
 459         (is_mve_undefined): Likewise.
 460         (is_mve_unpredictable): Likewise.
 461         (print_mve_vmov_index): Likewise.
 462         (print_simd_imm8): Likewise.
 463         (print_mve_undefined): Likewise.
 464         (print_mve_unpredictable): Likewise.
 465         (print_mve_size): Likewise.
 466         (print_insn_mve): Likewise.
 467
 468 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 469             Michael Collison <michael.collison@arm.com>
 470
 471         * arm-dis.c (enum mve_instructions): Add new instructions.
 472         (enum mve_unpredictable): Add new reasons.
 473         (enum mve_undefined): Likewise.
 474         (is_mve_encoding_conflict): Handle new instructions.
 475         (is_mve_undefined): Likewise.
 476         (is_mve_unpredictable): Likewise.
 477         (print_mve_undefined): Likewise.
 478         (print_mve_unpredictable): Likewise.
 479         (print_mve_rounding_mode): Likewise.
 480         (print_mve_vcvt_size): Likewise.
 481         (print_mve_size): Likewise.
 482         (print_insn_mve): Likewise.
 483
 484 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 485             Michael Collison <michael.collison@arm.com>
 486
 487         * arm-dis.c (enum mve_instructions): Add new instructions.
 488         (enum mve_unpredictable): Add new reasons.
 489         (enum mve_undefined): Likewise.
 490         (is_mve_undefined): Handle new instructions.
 491         (is_mve_unpredictable): Likewise.
 492         (print_mve_undefined): Likewise.
 493         (print_mve_unpredictable): Likewise.
 494         (print_mve_size): Likewise.
 495         (print_insn_mve): Likewise.
 496
 497 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 498             Michael Collison <michael.collison@arm.com>
 499
 500         * arm-dis.c (enum mve_instructions): Add new instructions.
 501         (enum mve_undefined): Add new reasons.
 502         (insns): Add new instructions.
 503         (is_mve_encoding_conflict):
 504         (print_mve_vld_str_addr): New print function.
 505         (is_mve_undefined): Handle new instructions.
 506         (is_mve_unpredictable): Likewise.
 507         (print_mve_undefined): Likewise.
 508         (print_mve_size): Likewise.
 509         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 510         (print_insn_mve):  Handle new operands.
 511
 512 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 513             Michael Collison <michael.collison@arm.com>
 514
 515         * arm-dis.c (enum mve_instructions): Add new instructions.
 516         (enum mve_unpredictable): Add new reasons.
 517         (is_mve_encoding_conflict): Handle new instructions.
 518         (is_mve_unpredictable): Likewise.
 519         (mve_opcodes): Add new instructions.
 520         (print_mve_unpredictable): Handle new reasons.
 521         (print_mve_register_blocks): New print function.
 522         (print_mve_size): Handle new instructions.
 523         (print_insn_mve): Likewise.
 524
 525 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 526             Michael Collison <michael.collison@arm.com>
 527
 528         * arm-dis.c (enum mve_instructions): Add new instructions.
 529         (enum mve_unpredictable): Add new reasons.
 530         (enum mve_undefined): Likewise.
 531         (is_mve_encoding_conflict): Handle new instructions.
 532         (is_mve_undefined): Likewise.
 533         (is_mve_unpredictable): Likewise.
 534         (coprocessor_opcodes): Move NEON VDUP from here...
 535         (neon_opcodes): ... to here.
 536         (mve_opcodes): Add new instructions.
 537         (print_mve_undefined):  Handle new reasons.
 538         (print_mve_unpredictable): Likewise.
 539         (print_mve_size): Handle new instructions.
 540         (print_insn_neon): Handle vdup.
 541         (print_insn_mve): Handle new operands.
 542
 543 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 544             Michael Collison <michael.collison@arm.com>
 545
 546         * arm-dis.c (enum mve_instructions): Add new instructions.
 547         (enum mve_unpredictable): Add new values.
 548         (mve_opcodes): Add new instructions.
 549         (vec_condnames): New array with vector conditions.
 550         (mve_predicatenames): New array with predicate suffixes.
 551         (mve_vec_sizename): New array with vector sizes.
 552         (enum vpt_pred_state): New enum with vector predication states.
 553         (struct vpt_block): New struct type for vpt blocks.
 554         (vpt_block_state): Global struct to keep track of state.
 555         (mve_extract_pred_mask): New helper function.
 556         (num_instructions_vpt_block): Likewise.
 557         (mark_outside_vpt_block): Likewise.
 558         (mark_inside_vpt_block): Likewise.
 559         (invert_next_predicate_state): Likewise.
 560         (update_next_predicate_state): Likewise.
 561         (update_vpt_block_state): Likewise.
 562         (is_vpt_instruction): Likewise.
 563         (is_mve_encoding_conflict): Add entries for new instructions.
 564         (is_mve_unpredictable): Likewise.
 565         (print_mve_unpredictable): Handle new cases.
 566         (print_instruction_predicate): Likewise.
 567         (print_mve_size): New function.
 568         (print_vec_condition): New function.
 569         (print_insn_mve): Handle vpt blocks and new print operands.
 570
 571 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 572
 573         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 574         8, 14 and 15 for Armv8.1-M Mainline.
 575
 576 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 577             Michael Collison <michael.collison@arm.com>
 578
 579         * arm-dis.c (enum mve_instructions): New enum.
 580         (enum mve_unpredictable): Likewise.
 581         (enum mve_undefined): Likewise.
 582         (struct mopcode32): New struct.
 583         (is_mve_okay_in_it): New function.
 584         (is_mve_architecture): Likewise.
 585         (arm_decode_field): Likewise.
 586         (arm_decode_field_multiple): Likewise.
 587         (is_mve_encoding_conflict): Likewise.
 588         (is_mve_undefined): Likewise.
 589         (is_mve_unpredictable): Likewise.
 590         (print_mve_undefined): Likewise.
 591         (print_mve_unpredictable): Likewise.
 592         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 593         (print_insn_mve): New function.
 594         (print_insn_thumb32): Handle MVE architecture.
 595         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 596
 597 2019-05-10  Nick Clifton  <nickc@redhat.com>
 598
 599         PR 24538
 600         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 601         end of the table prematurely.
 602
 603 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 604
 605         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 606         macros for R6.
 607
 608 2019-05-11  Alan Modra  <amodra@gmail.com>
 609
 610         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 611         when -Mraw is in effect.
 612
 613 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 614
 615         * aarch64-dis-2.c: Regenerate.
 616         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 617         (OP_SVE_BBB): New variant set.
 618         (OP_SVE_DDDD): New variant set.
 619         (OP_SVE_HHH): New variant set.
 620         (OP_SVE_HHHU): New variant set.
 621         (OP_SVE_SSS): New variant set.
 622         (OP_SVE_SSSU): New variant set.
 623         (OP_SVE_SHH): New variant set.
 624         (OP_SVE_SBBU): New variant set.
 625         (OP_SVE_DSS): New variant set.
 626         (OP_SVE_DHHU): New variant set.
 627         (OP_SVE_VMV_HSD_BHS): New variant set.
 628         (OP_SVE_VVU_HSD_BHS): New variant set.
 629         (OP_SVE_VVVU_SD_BH): New variant set.
 630         (OP_SVE_VVVU_BHSD): New variant set.
 631         (OP_SVE_VVV_QHD_DBS): New variant set.
 632         (OP_SVE_VVV_HSD_BHS): New variant set.
 633         (OP_SVE_VVV_HSD_BHS2): New variant set.
 634         (OP_SVE_VVV_BHS_HSD): New variant set.
 635         (OP_SVE_VV_BHS_HSD): New variant set.
 636         (OP_SVE_VVV_SD): New variant set.
 637         (OP_SVE_VVU_BHS_HSD): New variant set.
 638         (OP_SVE_VZVV_SD): New variant set.
 639         (OP_SVE_VZVV_BH): New variant set.
 640         (OP_SVE_VZV_SD): New variant set.
 641         (aarch64_opcode_table): Add sve2 instructions.
 642
 643 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 644
 645         * aarch64-asm-2.c: Regenerated.
 646         * aarch64-dis-2.c: Regenerated.
 647         * aarch64-opc-2.c: Regenerated.
 648         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 649         for SVE_SHLIMM_UNPRED_22.
 650         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 651         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 652         operand.
 653
 654 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 655
 656         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 657         sve_size_tsz_bhs iclass encode.
 658         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 659         sve_size_tsz_bhs iclass decode.
 660
 661 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 662
 663         * aarch64-asm-2.c: Regenerated.
 664         * aarch64-dis-2.c: Regenerated.
 665         * aarch64-opc-2.c: Regenerated.
 666         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 667         for SVE_Zm4_11_INDEX.
 668         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 669         (fields): Handle SVE_i2h field.
 670         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 671         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 672
 673 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 674
 675         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 676         sve_shift_tsz_bhsd iclass encode.
 677         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 678         sve_shift_tsz_bhsd iclass decode.
 679
 680 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 681
 682         * aarch64-asm-2.c: Regenerated.
 683         * aarch64-dis-2.c: Regenerated.
 684         * aarch64-opc-2.c: Regenerated.
 685         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 686         (aarch64_encode_variant_using_iclass): Handle
 687         sve_shift_tsz_hsd iclass encode.
 688         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 689         sve_shift_tsz_hsd iclass decode.
 690         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 691         for SVE_SHRIMM_UNPRED_22.
 692         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 693         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 694         operand.
 695
 696 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 697
 698         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 699         sve_size_013 iclass encode.
 700         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 701         sve_size_013 iclass decode.
 702
 703 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 704
 705         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 706         sve_size_bh iclass encode.
 707         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 708         sve_size_bh iclass decode.
 709
 710 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 711
 712         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 713         sve_size_sd2 iclass encode.
 714         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 715         sve_size_sd2 iclass decode.
 716         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 717         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 718
 719 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 720
 721         * aarch64-asm-2.c: Regenerated.
 722         * aarch64-dis-2.c: Regenerated.
 723         * aarch64-opc-2.c: Regenerated.
 724         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 725         for SVE_ADDR_ZX.
 726         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 727         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 728
 729 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 730
 731         * aarch64-asm-2.c: Regenerated.
 732         * aarch64-dis-2.c: Regenerated.
 733         * aarch64-opc-2.c: Regenerated.
 734         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 735         for SVE_Zm3_11_INDEX.
 736         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 737         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 738         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 739         fields.
 740         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 741
 742 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 743
 744         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 745         sve_size_hsd2 iclass encode.
 746         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 747         sve_size_hsd2 iclass decode.
 748         * aarch64-opc.c (fields): Handle SVE_size field.
 749         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 750
 751 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 752
 753         * aarch64-asm-2.c: Regenerated.
 754         * aarch64-dis-2.c: Regenerated.
 755         * aarch64-opc-2.c: Regenerated.
 756         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 757         for SVE_IMM_ROT3.
 758         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 759         (fields): Handle SVE_rot3 field.
 760         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 761         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 762
 763 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 764
 765         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 766         instructions.
 767
 768 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 769
 770         * aarch64-tbl.h
 771         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 772         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 773         aarch64_feature_sve2bitperm): New feature sets.
 774         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 775         for feature set addresses.
 776         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 777         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 778
 779 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 780             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 781
 782         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 783         argument and set ASE_EVA_R6 appropriately.
 784         (set_default_mips_dis_options): Pass ISA to above.
 785         (parse_mips_dis_option): Likewise.
 786         * mips-opc.c (EVAR6): New macro.
 787         (mips_builtin_opcodes): Add llwpe, scwpe.
 788
 789 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 790
 791         * aarch64-asm-2.c: Regenerated.
 792         * aarch64-dis-2.c: Regenerated.
 793         * aarch64-opc-2.c: Regenerated.
 794         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 795         AARCH64_OPND_TME_UIMM16.
 796         (aarch64_print_operand): Likewise.
 797         * aarch64-tbl.h (QL_IMM_NIL): New.
 798         (TME): New.
 799         (_TME_INSN): New.
 800         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 801
 802 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 803
 804         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 805
 806 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 807             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 808
 809         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 810
 811 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 812
 813         * s12z-opc.h: Add extern "C" bracketing to help
 814         users who wish to use this interface in c++ code.
 815
 816 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 817
 818         * s12z-opc.c (bm_decode): Handle bit map operations with the
 819         "reserved0" mode.
 820
 821 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 822
 823         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 824         specifier.  Add entries for VLDR and VSTR of system registers.
 825         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 826         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 827         of %J and %K format specifier.
 828
 829 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 830
 831         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 832         Add new entries for VSCCLRM instruction.
 833         (print_insn_coprocessor): Handle new %C format control code.
 834
 835 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 836
 837         * arm-dis.c (enum isa): New enum.
 838         (struct sopcode32): New structure.
 839         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 840         set isa field of all current entries to ANY.
 841         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 842         Only match an entry if its isa field allows the current mode.
 843
 844 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 845
 846         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 847         CLRM.
 848         (print_insn_thumb32): Add logic to print %n CLRM register list.
 849
 850 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 851
 852         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 853         and %Q patterns.
 854
 855 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 856
 857         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 858         (print_insn_thumb32): Edit the switch case for %Z.
 859
 860 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 861
 862         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 863
 864 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 865
 866         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 867
 868 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 869
 870         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 871
 872 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 873
 874         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 875         Arm register with r13 and r15 unpredictable.
 876         (thumb32_opcodes): New instructions for bfx and bflx.
 877
 878 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 879
 880         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 881
 882 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 883
 884         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 885
 886 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 887
 888         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 889
 890 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 891
 892         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 893
 894 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 895
 896         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 897         "optr". ("operator" is a reserved word in c++).
 898
 899 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 900
 901         * aarch64-opc.c (aarch64_print_operand): Add case for
 902         AARCH64_OPND_Rt_SP.
 903         (verify_constraints): Likewise.
 904         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 905         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 906         to accept Rt|SP as first operand.
 907         (AARCH64_OPERANDS): Add new Rt_SP.
 908         * aarch64-asm-2.c: Regenerated.
 909         * aarch64-dis-2.c: Regenerated.
 910         * aarch64-opc-2.c: Regenerated.
 911
 912 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 913
 914         * aarch64-asm-2.c: Regenerated.
 915         * aarch64-dis-2.c: Likewise.
 916         * aarch64-opc-2.c: Likewise.
 917         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 918
 919 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 920
 921         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 922
 923 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 924
 925         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 926         * i386-init.h: Regenerated.
 927
 928 2019-04-07  Alan Modra  <amodra@gmail.com>
 929
 930         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 931         op_separator to control printing of spaces, comma and parens
 932         rather than need_comma, need_paren and spaces vars.
 933
 934 2019-04-07  Alan Modra  <amodra@gmail.com>
 935
 936         PR 24421
 937         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 938         (print_insn_neon, print_insn_arm): Likewise.
 939
 940 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 941
 942         * i386-dis-evex.h (evex_table): Updated to support BF16
 943         instructions.
 944         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 945         and EVEX_W_0F3872_P_3.
 946         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 947         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 948         * i386-opc.h (enum): Add CpuAVX512_BF16.
 949         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 950         * i386-opc.tbl: Add AVX512 BF16 instructions.
 951         * i386-init.h: Regenerated.
 952         * i386-tbl.h: Likewise.
 953
 954 2019-04-05  Alan Modra  <amodra@gmail.com>
 955
 956         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 957         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 958         to favour printing of "-" branch hint when using the "y" bit.
 959         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 960
 961 2019-04-05  Alan Modra  <amodra@gmail.com>
 962
 963         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 964         opcode until first operand is output.
 965
 966 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 967
 968         PR gas/24349
 969         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 970         (valid_bo_post_v2): Add support for 'at' branch hints.
 971         (insert_bo): Only error on branch on ctr.
 972         (get_bo_hint_mask): New function.
 973         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 974         for inserting 'at' branch hints.
 975         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 976         for extracting 'at' branch hints.
 977         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 978         (BOE): Delete operand.
 979         (BOM, BOP): New operands.
 980         (RM): Update value.
 981         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 982         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 983         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 984         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 985         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 986         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 987         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 988         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 989         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 990         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 991         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 992         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 993         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 994         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 995         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 996         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 997         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 998         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 999         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1000         bttarl+>: New extended mnemonics.
1001
1002 2019-03-28  Alan Modra  <amodra@gmail.com>
1003
1004         PR 24390
1005         * ppc-opc.c (BTF): Define.
1006         (powerpc_opcodes): Use for mtfsb*.
1007         * ppc-dis.c (print_insn_powerpc): Print fields with both
1008         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1009
1010 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1011
1012         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1013         (mapping_symbol_for_insn): Implement new algorithm.
1014         (print_insn): Remove duplicate code.
1015
1016 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1017
1018         * aarch64-dis.c (print_insn_aarch64):
1019         Implement override.
1020
1021 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1022
1023         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1024         order.
1025
1026 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1027
1028         * aarch64-dis.c (last_stop_offset): New.
1029         (print_insn_aarch64): Use stop_offset.
1030
1031 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1032
1033         PR gas/24359
1034         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1035         CPU_ANY_AVX2_FLAGS.
1036         * i386-init.h: Regenerated.
1037
1038 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1039
1040         PR gas/24348
1041         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1042         vmovdqu16, vmovdqu32 and vmovdqu64.
1043         * i386-tbl.h: Regenerated.
1044
1045 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1046
1047         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1048         from vstrszb, vstrszh, and vstrszf.
1049
1050 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1051
1052         * s390-opc.txt: Add instruction descriptions.
1053
1054 2019-02-08  Jim Wilson  <jimw@sifive.com>
1055
1056         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1057         <bne>: Likewise.
1058
1059 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1060
1061         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1062
1063 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1064
1065         PR binutils/23212
1066         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1067         * aarch64-opc.c (verify_elem_sd): New.
1068         (fields): Add FLD_sz entr.
1069         * aarch64-tbl.h (_SIMD_INSN): New.
1070         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1071         fmulx scalar and vector by element isns.
1072
1073 2019-02-07  Nick Clifton  <nickc@redhat.com>
1074
1075         * po/sv.po: Updated Swedish translation.
1076
1077 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1078
1079         * s390-mkopc.c (main): Accept arch13 as cpu string.
1080         * s390-opc.c: Add new instruction formats and instruction opcode
1081         masks.
1082         * s390-opc.txt: Add new arch13 instructions.
1083
1084 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1085
1086         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1087         (aarch64_opcode): Change encoding for stg, stzg
1088         st2g and st2zg.
1089         * aarch64-asm-2.c: Regenerated.
1090         * aarch64-dis-2.c: Regenerated.
1091         * aarch64-opc-2.c: Regenerated.
1092
1093 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1094
1095         * aarch64-asm-2.c: Regenerated.
1096         * aarch64-dis-2.c: Likewise.
1097         * aarch64-opc-2.c: Likewise.
1098         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1099
1100 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1101             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1102
1103         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1104         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1105         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1106         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1107         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1108         case for ldstgv_indexed.
1109         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1110         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1111         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1112         * aarch64-asm-2.c: Regenerated.
1113         * aarch64-dis-2.c: Regenerated.
1114         * aarch64-opc-2.c: Regenerated.
1115
1116 2019-01-23  Nick Clifton  <nickc@redhat.com>
1117
1118         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1119
1120 2019-01-21  Nick Clifton  <nickc@redhat.com>
1121
1122         * po/de.po: Updated German translation.
1123         * po/uk.po: Updated Ukranian translation.
1124
1125 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1126         * mips-dis.c (mips_arch_choices): Fix typo in
1127         gs464, gs464e and gs264e descriptors.
1128
1129 2019-01-19  Nick Clifton  <nickc@redhat.com>
1130
1131         * configure: Regenerate.
1132         * po/opcodes.pot: Regenerate.
1133
1134 2018-06-24  Nick Clifton  <nickc@redhat.com>
1135
1136         2.32 branch created.
1137
1138 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1139
1140         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1141         if it is null.
1142         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1143         zero.
1144
1145 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1146
1147         * configure: Regenerate.
1148
1149 2019-01-07  Alan Modra  <amodra@gmail.com>
1150
1151         * configure: Regenerate.
1152         * po/POTFILES.in: Regenerate.
1153
1154 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1155
1156         * s12z-opc.c: New file.
1157         * s12z-opc.h: New file.
1158         * s12z-dis.c: Removed all code not directly related to display
1159         of instructions.  Used the interface provided by the new files
1160         instead.
1161         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1162         * Makefile.in: Regenerate.
1163         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1164         * configure: Regenerate.
1165
1166 2019-01-01  Alan Modra  <amodra@gmail.com>
1167
1168         Update year range in copyright notice of all files.
1169
1170 For older changes see ChangeLog-2018
1171 \f
1172 Copyright (C) 2019 Free Software Foundation, Inc.
1173
1174 Copying and distribution of this file, with or without modification,
1175 are permitted in any medium without royalty provided the copyright
1176 notice and this notice are preserved.
1177
1178 Local Variables:
1179 mode: change-log
1180 left-margin: 8
1181 fill-column: 74
1182 version-control: never
1183 End: