opcodes/ChangeLog

   1 2019-07-01  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
   4         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
   5         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
   6         * i386-tbl.h: Re-generate.
   7
   8 2019-07-01  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
  11         Disp8MemShift from register only templates.
  12         * i386-tbl.h: Re-generate.
  13
  14 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  15
  16         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
  17         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
  18         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
  19         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
  20         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
  21         EVEX_W_0F11_P_3_M_1): Delete.
  22         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
  23         EVEX_W_0F11_P_3): New.
  24         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
  25         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
  26         MOD_EVEX_0F11_PREFIX_3 table entries.
  27         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
  28         PREFIX_EVEX_0F11 table entries.
  29         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
  30         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
  31         EVEX_W_0F11_P_3_M_{0,1} table entries.
  32
  33 2019-07-01  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
  36         Delete.
  37
  38 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
  39
  40         PR binutils/24719
  41         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
  42         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
  43         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
  44         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
  45         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
  46         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
  47         EVEX_LEN_0F38C7_R_6_P_2_W_1.
  48         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
  49         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
  50         PREFIX_EVEX_0F38C6_REG_6 entries.
  51         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
  52         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
  53         EVEX_W_0F38C7_R_6_P_2 entries.
  54         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
  55         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
  56         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
  57         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
  58         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
  59         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
  60         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
  61
  62 2019-06-27  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
  65         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
  66         VEX_LEN_0F2D_P_3): Delete.
  67         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
  68         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
  69         (prefix_table): ... here.
  70
  71 2019-06-27  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-dis.c (Iq): Delete.
  74         (Id): New.
  75         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
  76         TBM insns.
  77         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
  78         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
  79         (OP_E_memory): Also honor needindex when deciding whether an
  80         address size prefix needs printing.
  81         (OP_I): Remove handling of q_mode. Add handling of d_mode.
  82
  83 2019-06-26  Jim Wilson  <jimw@sifive.com>
  84
  85         PR binutils/24739
  86         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
  87         Set info->display_endian to info->endian_code.
  88
  89 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  90
  91         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
  92         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
  93         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
  94         OPERAND_TYPE_ACC64 entries.
  95         * i386-init.h: Re-generate.
  96
  97 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 100         Delete.
 101         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 102         of dqa_mode.
 103         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 104         entries here.
 105         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 106         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 107
 108 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 111         variables.
 112
 113 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 116         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 117         movnti.
 118         * i386-opc.tbl (movnti): Add IgnoreSize.
 119         * i386-tbl.h: Re-generate.
 120
 121 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 122
 123         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 124         * i386-tbl.h: Re-generate.
 125
 126 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 127
 128         * i386-dis-evex.h: Break into ...
 129         * i386-dis-evex-len.h: New file.
 130         * i386-dis-evex-mod.h: Likewise.
 131         * i386-dis-evex-prefix.h: Likewise.
 132         * i386-dis-evex-reg.h: Likewise.
 133         * i386-dis-evex-w.h: Likewise.
 134         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 135         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 136         i386-dis-evex-mod.h.
 137
 138 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         PR binutils/24700
 141         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 142         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 143         EVEX_W_0F385B_P_2.
 144         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 145         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 146         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 147         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 148         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 149         EVEX_LEN_0F385B_P_2_W_1.
 150         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 151         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 152         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 153         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 154         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 155         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 156         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 157         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 158         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 159         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 160
 161 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 162
 163         PR binutils/24691
 164         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 165         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 166         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 167         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 168         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 169         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 170         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 171         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 172         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 173         EVEX_LEN_0F3A43_P_2_W_1.
 174         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 175         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 176         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 177         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 178         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 179         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 180         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 181         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 182         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 183         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 184         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 185         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 186
 187 2019-06-14  Nick Clifton  <nickc@redhat.com>
 188
 189         * po/fr.po; Updated French translation.
 190
 191 2019-06-13  Stafford Horne  <shorne@gmail.com>
 192
 193         * or1k-asm.c: Regenerated.
 194         * or1k-desc.c: Regenerated.
 195         * or1k-desc.h: Regenerated.
 196         * or1k-dis.c: Regenerated.
 197         * or1k-ibld.c: Regenerated.
 198         * or1k-opc.c: Regenerated.
 199         * or1k-opc.h: Regenerated.
 200         * or1k-opinst.c: Regenerated.
 201
 202 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 203
 204         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 205
 206 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         PR binutils/24633
 209         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 210         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 211         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 212         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 213         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 214         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 215         EVEX_LEN_0F3A1B_P_2_W_1.
 216         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 217         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 218         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 219         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 220         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 221         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 222         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 223         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 224
 225 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 226
 227         PR binutils/24626
 228         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 229         EVEX.vvvv when disassembling VEX and EVEX instructions.
 230         (OP_VEX): Set vex.register_specifier to 0 after readding
 231         vex.register_specifier.
 232         (OP_Vex_2src_1): Likewise.
 233         (OP_Vex_2src_2): Likewise.
 234         (OP_LWP_E): Likewise.
 235         (OP_EX_Vex): Don't check vex.register_specifier.
 236         (OP_XMM_Vex): Likewise.
 237
 238 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 239             Lili Cui  <lili.cui@intel.com>
 240
 241         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 242         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 243         instructions.
 244         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 245         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 246         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 247         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 248         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 249         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 250         * i386-init.h: Regenerated.
 251         * i386-tbl.h: Likewise.
 252
 253 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 254             Lili Cui  <lili.cui@intel.com>
 255
 256         * doc/c-i386.texi: Document enqcmd.
 257         * testsuite/gas/i386/enqcmd-intel.d: New file.
 258         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 259         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 260         * testsuite/gas/i386/enqcmd.d: Likewise.
 261         * testsuite/gas/i386/enqcmd.s: Likewise.
 262         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 263         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 264         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 265         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 266         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 267         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 268         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 269         and x86-64-enqcmd.
 270
 271 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 272
 273         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 274
 275 2019-06-03  Alan Modra  <amodra@gmail.com>
 276
 277         * ppc-dis.c (prefix_opcd_indices): Correct size.
 278
 279 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 280
 281         PR gas/24625
 282         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 283         Disp8ShiftVL.
 284         * i386-tbl.h: Regenerated.
 285
 286 2019-05-24  Alan Modra  <amodra@gmail.com>
 287
 288         * po/POTFILES.in: Regenerate.
 289
 290 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 291             Alan Modra  <amodra@gmail.com>
 292
 293         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 294         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 295         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 296         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 297         XTOP>): Define and add entries.
 298         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 299         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 300         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 301         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 302
 303 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 304             Alan Modra  <amodra@gmail.com>
 305
 306         * ppc-dis.c (ppc_opts): Add "future" entry.
 307         (PREFIX_OPCD_SEGS): Define.
 308         (prefix_opcd_indices): New array.
 309         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 310         (lookup_prefix): New function.
 311         (print_insn_powerpc): Handle 64-bit prefix instructions.
 312         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 313         (PMRR, POWERXX): Define.
 314         (prefix_opcodes): New instruction table.
 315         (prefix_num_opcodes): New constant.
 316
 317 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 318
 319         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 320         * configure: Regenerated.
 321         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 322         and cpu/bpf.opc.
 323         (HFILES): Add bpf-desc.h and bpf-opc.h.
 324         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 325         bpf-ibld.c and bpf-opc.c.
 326         (BPF_DEPS): Define.
 327         * Makefile.in: Regenerated.
 328         * disassemble.c (ARCH_bpf): Define.
 329         (disassembler): Add case for bfd_arch_bpf.
 330         (disassemble_init_for_target): Likewise.
 331         (enum epbf_isa_attr): Define.
 332         * disassemble.h: extern print_insn_bpf.
 333         * bpf-asm.c: Generated.
 334         * bpf-opc.h: Likewise.
 335         * bpf-opc.c: Likewise.
 336         * bpf-ibld.c: Likewise.
 337         * bpf-dis.c: Likewise.
 338         * bpf-desc.h: Likewise.
 339         * bpf-desc.c: Likewise.
 340
 341 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 342
 343         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 344         and VMSR with the new operands.
 345
 346 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 347
 348         * arm-dis.c (enum mve_instructions): New enum
 349         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 350         and cneg.
 351         (mve_opcodes): New instructions as above.
 352         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 353         csneg and csel.
 354         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 355
 356 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 357
 358         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 359         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 360         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 361         uqshl, urshrl and urshr.
 362         (is_mve_okay_in_it): Add new instructions to TRUE list.
 363         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 364         (print_insn_mve): Updated to accept new %j,
 365         %<bitfield>m and %<bitfield>n patterns.
 366
 367 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 368
 369         * mips-opc.c (mips_builtin_opcodes): Change source register
 370         constraint for DAUI.
 371
 372 2019-05-20  Nick Clifton  <nickc@redhat.com>
 373
 374         * po/fr.po: Updated French translation.
 375
 376 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 377             Michael Collison <michael.collison@arm.com>
 378
 379         * arm-dis.c (thumb32_opcodes): Add new instructions.
 380         (enum mve_instructions): Likewise.
 381         (enum mve_undefined): Add new reasons.
 382         (is_mve_encoding_conflict): Handle new instructions.
 383         (is_mve_undefined): Likewise.
 384         (is_mve_unpredictable): Likewise.
 385         (print_mve_undefined): Likewise.
 386         (print_mve_size): Likewise.
 387
 388 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 389             Michael Collison <michael.collison@arm.com>
 390
 391         * arm-dis.c (thumb32_opcodes): Add new instructions.
 392         (enum mve_instructions): Likewise.
 393         (is_mve_encoding_conflict): Handle new instructions.
 394         (is_mve_undefined): Likewise.
 395         (is_mve_unpredictable): Likewise.
 396         (print_mve_size): Likewise.
 397
 398 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 399             Michael Collison <michael.collison@arm.com>
 400
 401         * arm-dis.c (thumb32_opcodes): Add new instructions.
 402         (enum mve_instructions): Likewise.
 403         (is_mve_encoding_conflict): Likewise.
 404         (is_mve_unpredictable): Likewise.
 405         (print_mve_size): Likewise.
 406
 407 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 408             Michael Collison <michael.collison@arm.com>
 409
 410         * arm-dis.c (thumb32_opcodes): Add new instructions.
 411         (enum mve_instructions): Likewise.
 412         (is_mve_encoding_conflict): Handle new instructions.
 413         (is_mve_undefined): Likewise.
 414         (is_mve_unpredictable): Likewise.
 415         (print_mve_size): Likewise.
 416
 417 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 418             Michael Collison <michael.collison@arm.com>
 419
 420         * arm-dis.c (thumb32_opcodes): Add new instructions.
 421         (enum mve_instructions): Likewise.
 422         (is_mve_encoding_conflict): Handle new instructions.
 423         (is_mve_undefined): Likewise.
 424         (is_mve_unpredictable): Likewise.
 425         (print_mve_size): Likewise.
 426         (print_insn_mve): Likewise.
 427
 428 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 429             Michael Collison <michael.collison@arm.com>
 430
 431         * arm-dis.c (thumb32_opcodes): Add new instructions.
 432         (print_insn_thumb32): Handle new instructions.
 433
 434 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 435             Michael Collison <michael.collison@arm.com>
 436
 437         * arm-dis.c (enum mve_instructions): Add new instructions.
 438         (enum mve_undefined): Add new reasons.
 439         (is_mve_encoding_conflict): Handle new instructions.
 440         (is_mve_undefined): Likewise.
 441         (is_mve_unpredictable): Likewise.
 442         (print_mve_undefined): Likewise.
 443         (print_mve_size): Likewise.
 444         (print_mve_shift_n): Likewise.
 445         (print_insn_mve): Likewise.
 446
 447 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 448             Michael Collison <michael.collison@arm.com>
 449
 450         * arm-dis.c (enum mve_instructions): Add new instructions.
 451         (is_mve_encoding_conflict): Handle new instructions.
 452         (is_mve_unpredictable): Likewise.
 453         (print_mve_rotate): Likewise.
 454         (print_mve_size): Likewise.
 455         (print_insn_mve): Likewise.
 456
 457 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 458             Michael Collison <michael.collison@arm.com>
 459
 460         * arm-dis.c (enum mve_instructions): Add new instructions.
 461         (is_mve_encoding_conflict): Handle new instructions.
 462         (is_mve_unpredictable): Likewise.
 463         (print_mve_size): Likewise.
 464         (print_insn_mve): Likewise.
 465
 466 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 467             Michael Collison <michael.collison@arm.com>
 468
 469         * arm-dis.c (enum mve_instructions): Add new instructions.
 470         (enum mve_undefined): Add new reasons.
 471         (is_mve_encoding_conflict): Handle new instructions.
 472         (is_mve_undefined): Likewise.
 473         (is_mve_unpredictable): Likewise.
 474         (print_mve_undefined): Likewise.
 475         (print_mve_size): Likewise.
 476         (print_insn_mve): Likewise.
 477
 478 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 479             Michael Collison <michael.collison@arm.com>
 480
 481         * arm-dis.c (enum mve_instructions): Add new instructions.
 482         (is_mve_encoding_conflict): Handle new instructions.
 483         (is_mve_undefined): Likewise.
 484         (is_mve_unpredictable): Likewise.
 485         (print_mve_size): Likewise.
 486         (print_insn_mve): Likewise.
 487
 488 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 489             Michael Collison <michael.collison@arm.com>
 490
 491         * arm-dis.c (enum mve_instructions): Add new instructions.
 492         (enum mve_unpredictable): Add new reasons.
 493         (enum mve_undefined): Likewise.
 494         (is_mve_okay_in_it): Handle new isntructions.
 495         (is_mve_encoding_conflict): Likewise.
 496         (is_mve_undefined): Likewise.
 497         (is_mve_unpredictable): Likewise.
 498         (print_mve_vmov_index): Likewise.
 499         (print_simd_imm8): Likewise.
 500         (print_mve_undefined): Likewise.
 501         (print_mve_unpredictable): Likewise.
 502         (print_mve_size): Likewise.
 503         (print_insn_mve): Likewise.
 504
 505 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 506             Michael Collison <michael.collison@arm.com>
 507
 508         * arm-dis.c (enum mve_instructions): Add new instructions.
 509         (enum mve_unpredictable): Add new reasons.
 510         (enum mve_undefined): Likewise.
 511         (is_mve_encoding_conflict): Handle new instructions.
 512         (is_mve_undefined): Likewise.
 513         (is_mve_unpredictable): Likewise.
 514         (print_mve_undefined): Likewise.
 515         (print_mve_unpredictable): Likewise.
 516         (print_mve_rounding_mode): Likewise.
 517         (print_mve_vcvt_size): Likewise.
 518         (print_mve_size): Likewise.
 519         (print_insn_mve): Likewise.
 520
 521 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 522             Michael Collison <michael.collison@arm.com>
 523
 524         * arm-dis.c (enum mve_instructions): Add new instructions.
 525         (enum mve_unpredictable): Add new reasons.
 526         (enum mve_undefined): Likewise.
 527         (is_mve_undefined): Handle new instructions.
 528         (is_mve_unpredictable): Likewise.
 529         (print_mve_undefined): Likewise.
 530         (print_mve_unpredictable): Likewise.
 531         (print_mve_size): Likewise.
 532         (print_insn_mve): Likewise.
 533
 534 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 535             Michael Collison <michael.collison@arm.com>
 536
 537         * arm-dis.c (enum mve_instructions): Add new instructions.
 538         (enum mve_undefined): Add new reasons.
 539         (insns): Add new instructions.
 540         (is_mve_encoding_conflict):
 541         (print_mve_vld_str_addr): New print function.
 542         (is_mve_undefined): Handle new instructions.
 543         (is_mve_unpredictable): Likewise.
 544         (print_mve_undefined): Likewise.
 545         (print_mve_size): Likewise.
 546         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 547         (print_insn_mve):  Handle new operands.
 548
 549 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 550             Michael Collison <michael.collison@arm.com>
 551
 552         * arm-dis.c (enum mve_instructions): Add new instructions.
 553         (enum mve_unpredictable): Add new reasons.
 554         (is_mve_encoding_conflict): Handle new instructions.
 555         (is_mve_unpredictable): Likewise.
 556         (mve_opcodes): Add new instructions.
 557         (print_mve_unpredictable): Handle new reasons.
 558         (print_mve_register_blocks): New print function.
 559         (print_mve_size): Handle new instructions.
 560         (print_insn_mve): Likewise.
 561
 562 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 563             Michael Collison <michael.collison@arm.com>
 564
 565         * arm-dis.c (enum mve_instructions): Add new instructions.
 566         (enum mve_unpredictable): Add new reasons.
 567         (enum mve_undefined): Likewise.
 568         (is_mve_encoding_conflict): Handle new instructions.
 569         (is_mve_undefined): Likewise.
 570         (is_mve_unpredictable): Likewise.
 571         (coprocessor_opcodes): Move NEON VDUP from here...
 572         (neon_opcodes): ... to here.
 573         (mve_opcodes): Add new instructions.
 574         (print_mve_undefined):  Handle new reasons.
 575         (print_mve_unpredictable): Likewise.
 576         (print_mve_size): Handle new instructions.
 577         (print_insn_neon): Handle vdup.
 578         (print_insn_mve): Handle new operands.
 579
 580 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 581             Michael Collison <michael.collison@arm.com>
 582
 583         * arm-dis.c (enum mve_instructions): Add new instructions.
 584         (enum mve_unpredictable): Add new values.
 585         (mve_opcodes): Add new instructions.
 586         (vec_condnames): New array with vector conditions.
 587         (mve_predicatenames): New array with predicate suffixes.
 588         (mve_vec_sizename): New array with vector sizes.
 589         (enum vpt_pred_state): New enum with vector predication states.
 590         (struct vpt_block): New struct type for vpt blocks.
 591         (vpt_block_state): Global struct to keep track of state.
 592         (mve_extract_pred_mask): New helper function.
 593         (num_instructions_vpt_block): Likewise.
 594         (mark_outside_vpt_block): Likewise.
 595         (mark_inside_vpt_block): Likewise.
 596         (invert_next_predicate_state): Likewise.
 597         (update_next_predicate_state): Likewise.
 598         (update_vpt_block_state): Likewise.
 599         (is_vpt_instruction): Likewise.
 600         (is_mve_encoding_conflict): Add entries for new instructions.
 601         (is_mve_unpredictable): Likewise.
 602         (print_mve_unpredictable): Handle new cases.
 603         (print_instruction_predicate): Likewise.
 604         (print_mve_size): New function.
 605         (print_vec_condition): New function.
 606         (print_insn_mve): Handle vpt blocks and new print operands.
 607
 608 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 609
 610         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 611         8, 14 and 15 for Armv8.1-M Mainline.
 612
 613 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 614             Michael Collison <michael.collison@arm.com>
 615
 616         * arm-dis.c (enum mve_instructions): New enum.
 617         (enum mve_unpredictable): Likewise.
 618         (enum mve_undefined): Likewise.
 619         (struct mopcode32): New struct.
 620         (is_mve_okay_in_it): New function.
 621         (is_mve_architecture): Likewise.
 622         (arm_decode_field): Likewise.
 623         (arm_decode_field_multiple): Likewise.
 624         (is_mve_encoding_conflict): Likewise.
 625         (is_mve_undefined): Likewise.
 626         (is_mve_unpredictable): Likewise.
 627         (print_mve_undefined): Likewise.
 628         (print_mve_unpredictable): Likewise.
 629         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 630         (print_insn_mve): New function.
 631         (print_insn_thumb32): Handle MVE architecture.
 632         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 633
 634 2019-05-10  Nick Clifton  <nickc@redhat.com>
 635
 636         PR 24538
 637         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 638         end of the table prematurely.
 639
 640 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 641
 642         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 643         macros for R6.
 644
 645 2019-05-11  Alan Modra  <amodra@gmail.com>
 646
 647         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 648         when -Mraw is in effect.
 649
 650 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 651
 652         * aarch64-dis-2.c: Regenerate.
 653         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 654         (OP_SVE_BBB): New variant set.
 655         (OP_SVE_DDDD): New variant set.
 656         (OP_SVE_HHH): New variant set.
 657         (OP_SVE_HHHU): New variant set.
 658         (OP_SVE_SSS): New variant set.
 659         (OP_SVE_SSSU): New variant set.
 660         (OP_SVE_SHH): New variant set.
 661         (OP_SVE_SBBU): New variant set.
 662         (OP_SVE_DSS): New variant set.
 663         (OP_SVE_DHHU): New variant set.
 664         (OP_SVE_VMV_HSD_BHS): New variant set.
 665         (OP_SVE_VVU_HSD_BHS): New variant set.
 666         (OP_SVE_VVVU_SD_BH): New variant set.
 667         (OP_SVE_VVVU_BHSD): New variant set.
 668         (OP_SVE_VVV_QHD_DBS): New variant set.
 669         (OP_SVE_VVV_HSD_BHS): New variant set.
 670         (OP_SVE_VVV_HSD_BHS2): New variant set.
 671         (OP_SVE_VVV_BHS_HSD): New variant set.
 672         (OP_SVE_VV_BHS_HSD): New variant set.
 673         (OP_SVE_VVV_SD): New variant set.
 674         (OP_SVE_VVU_BHS_HSD): New variant set.
 675         (OP_SVE_VZVV_SD): New variant set.
 676         (OP_SVE_VZVV_BH): New variant set.
 677         (OP_SVE_VZV_SD): New variant set.
 678         (aarch64_opcode_table): Add sve2 instructions.
 679
 680 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 681
 682         * aarch64-asm-2.c: Regenerated.
 683         * aarch64-dis-2.c: Regenerated.
 684         * aarch64-opc-2.c: Regenerated.
 685         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 686         for SVE_SHLIMM_UNPRED_22.
 687         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 688         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 689         operand.
 690
 691 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 692
 693         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 694         sve_size_tsz_bhs iclass encode.
 695         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 696         sve_size_tsz_bhs iclass decode.
 697
 698 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 699
 700         * aarch64-asm-2.c: Regenerated.
 701         * aarch64-dis-2.c: Regenerated.
 702         * aarch64-opc-2.c: Regenerated.
 703         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 704         for SVE_Zm4_11_INDEX.
 705         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 706         (fields): Handle SVE_i2h field.
 707         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 708         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 709
 710 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 711
 712         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 713         sve_shift_tsz_bhsd iclass encode.
 714         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 715         sve_shift_tsz_bhsd iclass decode.
 716
 717 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 718
 719         * aarch64-asm-2.c: Regenerated.
 720         * aarch64-dis-2.c: Regenerated.
 721         * aarch64-opc-2.c: Regenerated.
 722         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 723         (aarch64_encode_variant_using_iclass): Handle
 724         sve_shift_tsz_hsd iclass encode.
 725         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 726         sve_shift_tsz_hsd iclass decode.
 727         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 728         for SVE_SHRIMM_UNPRED_22.
 729         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 730         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 731         operand.
 732
 733 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 734
 735         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 736         sve_size_013 iclass encode.
 737         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 738         sve_size_013 iclass decode.
 739
 740 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 741
 742         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 743         sve_size_bh iclass encode.
 744         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 745         sve_size_bh iclass decode.
 746
 747 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 748
 749         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 750         sve_size_sd2 iclass encode.
 751         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 752         sve_size_sd2 iclass decode.
 753         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 754         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 755
 756 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 757
 758         * aarch64-asm-2.c: Regenerated.
 759         * aarch64-dis-2.c: Regenerated.
 760         * aarch64-opc-2.c: Regenerated.
 761         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 762         for SVE_ADDR_ZX.
 763         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 764         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 765
 766 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 767
 768         * aarch64-asm-2.c: Regenerated.
 769         * aarch64-dis-2.c: Regenerated.
 770         * aarch64-opc-2.c: Regenerated.
 771         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 772         for SVE_Zm3_11_INDEX.
 773         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 774         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 775         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 776         fields.
 777         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 778
 779 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 780
 781         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 782         sve_size_hsd2 iclass encode.
 783         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 784         sve_size_hsd2 iclass decode.
 785         * aarch64-opc.c (fields): Handle SVE_size field.
 786         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 787
 788 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 789
 790         * aarch64-asm-2.c: Regenerated.
 791         * aarch64-dis-2.c: Regenerated.
 792         * aarch64-opc-2.c: Regenerated.
 793         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 794         for SVE_IMM_ROT3.
 795         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 796         (fields): Handle SVE_rot3 field.
 797         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 798         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 799
 800 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 801
 802         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 803         instructions.
 804
 805 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 806
 807         * aarch64-tbl.h
 808         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 809         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 810         aarch64_feature_sve2bitperm): New feature sets.
 811         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 812         for feature set addresses.
 813         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 814         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 815
 816 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 817             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 818
 819         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 820         argument and set ASE_EVA_R6 appropriately.
 821         (set_default_mips_dis_options): Pass ISA to above.
 822         (parse_mips_dis_option): Likewise.
 823         * mips-opc.c (EVAR6): New macro.
 824         (mips_builtin_opcodes): Add llwpe, scwpe.
 825
 826 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 827
 828         * aarch64-asm-2.c: Regenerated.
 829         * aarch64-dis-2.c: Regenerated.
 830         * aarch64-opc-2.c: Regenerated.
 831         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 832         AARCH64_OPND_TME_UIMM16.
 833         (aarch64_print_operand): Likewise.
 834         * aarch64-tbl.h (QL_IMM_NIL): New.
 835         (TME): New.
 836         (_TME_INSN): New.
 837         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 838
 839 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 840
 841         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 842
 843 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 844             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 845
 846         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 847
 848 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 849
 850         * s12z-opc.h: Add extern "C" bracketing to help
 851         users who wish to use this interface in c++ code.
 852
 853 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 854
 855         * s12z-opc.c (bm_decode): Handle bit map operations with the
 856         "reserved0" mode.
 857
 858 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 859
 860         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 861         specifier.  Add entries for VLDR and VSTR of system registers.
 862         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 863         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 864         of %J and %K format specifier.
 865
 866 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 867
 868         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 869         Add new entries for VSCCLRM instruction.
 870         (print_insn_coprocessor): Handle new %C format control code.
 871
 872 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 873
 874         * arm-dis.c (enum isa): New enum.
 875         (struct sopcode32): New structure.
 876         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 877         set isa field of all current entries to ANY.
 878         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 879         Only match an entry if its isa field allows the current mode.
 880
 881 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 882
 883         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 884         CLRM.
 885         (print_insn_thumb32): Add logic to print %n CLRM register list.
 886
 887 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 888
 889         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 890         and %Q patterns.
 891
 892 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 893
 894         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 895         (print_insn_thumb32): Edit the switch case for %Z.
 896
 897 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 898
 899         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 900
 901 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 902
 903         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 904
 905 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 906
 907         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 908
 909 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 910
 911         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 912         Arm register with r13 and r15 unpredictable.
 913         (thumb32_opcodes): New instructions for bfx and bflx.
 914
 915 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 916
 917         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 918
 919 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 920
 921         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 922
 923 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 924
 925         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 926
 927 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 928
 929         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 930
 931 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 932
 933         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 934         "optr". ("operator" is a reserved word in c++).
 935
 936 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 937
 938         * aarch64-opc.c (aarch64_print_operand): Add case for
 939         AARCH64_OPND_Rt_SP.
 940         (verify_constraints): Likewise.
 941         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 942         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 943         to accept Rt|SP as first operand.
 944         (AARCH64_OPERANDS): Add new Rt_SP.
 945         * aarch64-asm-2.c: Regenerated.
 946         * aarch64-dis-2.c: Regenerated.
 947         * aarch64-opc-2.c: Regenerated.
 948
 949 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 950
 951         * aarch64-asm-2.c: Regenerated.
 952         * aarch64-dis-2.c: Likewise.
 953         * aarch64-opc-2.c: Likewise.
 954         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 955
 956 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 957
 958         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 959
 960 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 961
 962         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 963         * i386-init.h: Regenerated.
 964
 965 2019-04-07  Alan Modra  <amodra@gmail.com>
 966
 967         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 968         op_separator to control printing of spaces, comma and parens
 969         rather than need_comma, need_paren and spaces vars.
 970
 971 2019-04-07  Alan Modra  <amodra@gmail.com>
 972
 973         PR 24421
 974         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 975         (print_insn_neon, print_insn_arm): Likewise.
 976
 977 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 978
 979         * i386-dis-evex.h (evex_table): Updated to support BF16
 980         instructions.
 981         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 982         and EVEX_W_0F3872_P_3.
 983         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 984         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 985         * i386-opc.h (enum): Add CpuAVX512_BF16.
 986         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 987         * i386-opc.tbl: Add AVX512 BF16 instructions.
 988         * i386-init.h: Regenerated.
 989         * i386-tbl.h: Likewise.
 990
 991 2019-04-05  Alan Modra  <amodra@gmail.com>
 992
 993         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 994         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 995         to favour printing of "-" branch hint when using the "y" bit.
 996         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 997
 998 2019-04-05  Alan Modra  <amodra@gmail.com>
 999
1000         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1001         opcode until first operand is output.
1002
1003 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1004
1005         PR gas/24349
1006         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1007         (valid_bo_post_v2): Add support for 'at' branch hints.
1008         (insert_bo): Only error on branch on ctr.
1009         (get_bo_hint_mask): New function.
1010         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1011         for inserting 'at' branch hints.
1012         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1013         for extracting 'at' branch hints.
1014         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1015         (BOE): Delete operand.
1016         (BOM, BOP): New operands.
1017         (RM): Update value.
1018         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1019         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1020         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1021         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1022         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1023         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1024         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1025         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1026         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1027         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1028         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1029         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1030         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1031         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1032         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1033         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1034         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1035         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1036         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1037         bttarl+>: New extended mnemonics.
1038
1039 2019-03-28  Alan Modra  <amodra@gmail.com>
1040
1041         PR 24390
1042         * ppc-opc.c (BTF): Define.
1043         (powerpc_opcodes): Use for mtfsb*.
1044         * ppc-dis.c (print_insn_powerpc): Print fields with both
1045         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1046
1047 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1048
1049         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1050         (mapping_symbol_for_insn): Implement new algorithm.
1051         (print_insn): Remove duplicate code.
1052
1053 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1054
1055         * aarch64-dis.c (print_insn_aarch64):
1056         Implement override.
1057
1058 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1059
1060         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1061         order.
1062
1063 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1064
1065         * aarch64-dis.c (last_stop_offset): New.
1066         (print_insn_aarch64): Use stop_offset.
1067
1068 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1069
1070         PR gas/24359
1071         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1072         CPU_ANY_AVX2_FLAGS.
1073         * i386-init.h: Regenerated.
1074
1075 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1076
1077         PR gas/24348
1078         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1079         vmovdqu16, vmovdqu32 and vmovdqu64.
1080         * i386-tbl.h: Regenerated.
1081
1082 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1083
1084         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1085         from vstrszb, vstrszh, and vstrszf.
1086
1087 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1088
1089         * s390-opc.txt: Add instruction descriptions.
1090
1091 2019-02-08  Jim Wilson  <jimw@sifive.com>
1092
1093         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1094         <bne>: Likewise.
1095
1096 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1097
1098         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1099
1100 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1101
1102         PR binutils/23212
1103         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1104         * aarch64-opc.c (verify_elem_sd): New.
1105         (fields): Add FLD_sz entr.
1106         * aarch64-tbl.h (_SIMD_INSN): New.
1107         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1108         fmulx scalar and vector by element isns.
1109
1110 2019-02-07  Nick Clifton  <nickc@redhat.com>
1111
1112         * po/sv.po: Updated Swedish translation.
1113
1114 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1115
1116         * s390-mkopc.c (main): Accept arch13 as cpu string.
1117         * s390-opc.c: Add new instruction formats and instruction opcode
1118         masks.
1119         * s390-opc.txt: Add new arch13 instructions.
1120
1121 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1122
1123         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1124         (aarch64_opcode): Change encoding for stg, stzg
1125         st2g and st2zg.
1126         * aarch64-asm-2.c: Regenerated.
1127         * aarch64-dis-2.c: Regenerated.
1128         * aarch64-opc-2.c: Regenerated.
1129
1130 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1131
1132         * aarch64-asm-2.c: Regenerated.
1133         * aarch64-dis-2.c: Likewise.
1134         * aarch64-opc-2.c: Likewise.
1135         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1136
1137 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1138             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1139
1140         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1141         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1142         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1143         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1144         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1145         case for ldstgv_indexed.
1146         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1147         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1148         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1149         * aarch64-asm-2.c: Regenerated.
1150         * aarch64-dis-2.c: Regenerated.
1151         * aarch64-opc-2.c: Regenerated.
1152
1153 2019-01-23  Nick Clifton  <nickc@redhat.com>
1154
1155         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1156
1157 2019-01-21  Nick Clifton  <nickc@redhat.com>
1158
1159         * po/de.po: Updated German translation.
1160         * po/uk.po: Updated Ukranian translation.
1161
1162 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1163         * mips-dis.c (mips_arch_choices): Fix typo in
1164         gs464, gs464e and gs264e descriptors.
1165
1166 2019-01-19  Nick Clifton  <nickc@redhat.com>
1167
1168         * configure: Regenerate.
1169         * po/opcodes.pot: Regenerate.
1170
1171 2018-06-24  Nick Clifton  <nickc@redhat.com>
1172
1173         2.32 branch created.
1174
1175 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1176
1177         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1178         if it is null.
1179         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1180         zero.
1181
1182 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1183
1184         * configure: Regenerate.
1185
1186 2019-01-07  Alan Modra  <amodra@gmail.com>
1187
1188         * configure: Regenerate.
1189         * po/POTFILES.in: Regenerate.
1190
1191 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1192
1193         * s12z-opc.c: New file.
1194         * s12z-opc.h: New file.
1195         * s12z-dis.c: Removed all code not directly related to display
1196         of instructions.  Used the interface provided by the new files
1197         instead.
1198         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1199         * Makefile.in: Regenerate.
1200         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1201         * configure: Regenerate.
1202
1203 2019-01-01  Alan Modra  <amodra@gmail.com>
1204
1205         Update year range in copyright notice of all files.
1206
1207 For older changes see ChangeLog-2018
1208 \f
1209 Copyright (C) 2019 Free Software Foundation, Inc.
1210
1211 Copying and distribution of this file, with or without modification,
1212 are permitted in any medium without royalty provided the copyright
1213 notice and this notice are preserved.
1214
1215 Local Variables:
1216 mode: change-log
1217 left-margin: 8
1218 fill-column: 74
1219 version-control: never
1220 End: