1 2020-03-26 Alan Modra <amodra@gmail.com>
3 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
5 2020-03-25 Alan Modra <amodra@gmail.com>
7 * z80-dis.c (suffix): Init mybuf.
9 2020-03-22 Alan Modra <amodra@gmail.com>
11 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
12 successflly read from section.
14 2020-03-22 Alan Modra <amodra@gmail.com>
16 * arc-dis.c (find_format): Use ISO C string concatenation rather
17 than line continuation within a string. Don't access needs_limm
18 before testing opcode != NULL.
20 2020-03-22 Alan Modra <amodra@gmail.com>
22 * ns32k-dis.c (print_insn_arg): Update comment.
23 (print_insn_ns32k): Reduce size of index_offset array, and
24 initialize, passing -1 to print_insn_arg for args that are not
25 an index. Don't exit arg loop early. Abort on bad arg number.
27 2020-03-22 Alan Modra <amodra@gmail.com>
29 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
30 * s12z-opc.c: Formatting.
31 (operands_f): Return an int.
32 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
33 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
34 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
35 (exg_sex_discrim): Likewise.
36 (create_immediate_operand, create_bitfield_operand),
37 (create_register_operand_with_size, create_register_all_operand),
38 (create_register_all16_operand, create_simple_memory_operand),
39 (create_memory_operand, create_memory_auto_operand): Don't
40 segfault on malloc failure.
41 (z_ext24_decode): Return an int status, negative on fail, zero
43 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
44 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
45 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
46 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
47 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
48 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
49 (loop_primitive_decode, shift_decode, psh_pul_decode),
50 (bit_field_decode): Similarly.
51 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
52 to return value, update callers.
53 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
54 Don't segfault on NULL operand.
55 (decode_operation): Return OP_INVALID on first fail.
56 (decode_s12z): Check all reads, returning -1 on fail.
58 2020-03-20 Alan Modra <amodra@gmail.com>
60 * metag-dis.c (print_insn_metag): Don't ignore status from
63 2020-03-20 Alan Modra <amodra@gmail.com>
65 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
66 Initialize parts of buffer not written when handling a possible
67 2-byte insn at end of section. Don't attempt decoding of such
68 an insn by the 4-byte machinery.
70 2020-03-20 Alan Modra <amodra@gmail.com>
72 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
73 partially filled buffer. Prevent lookup of 4-byte insns when
74 only VLE 2-byte insns are possible due to section size. Print
75 ".word" rather than ".long" for 2-byte leftovers.
77 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
80 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
82 2020-03-13 Jan Beulich <jbeulich@suse.com>
84 * i386-dis.c (X86_64_0D): Rename to ...
85 (X86_64_0E): ... this.
87 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
89 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
90 * Makefile.in: Regenerated.
92 2020-03-09 Jan Beulich <jbeulich@suse.com>
94 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
96 * i386-tbl.h: Re-generate.
98 2020-03-09 Jan Beulich <jbeulich@suse.com>
100 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
101 vprot*, vpsha*, and vpshl*.
102 * i386-tbl.h: Re-generate.
104 2020-03-09 Jan Beulich <jbeulich@suse.com>
106 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
107 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
108 * i386-tbl.h: Re-generate.
110 2020-03-09 Jan Beulich <jbeulich@suse.com>
112 * i386-gen.c (set_bitfield): Ignore zero-length field names.
113 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
114 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
115 * i386-tbl.h: Re-generate.
117 2020-03-09 Jan Beulich <jbeulich@suse.com>
119 * i386-gen.c (struct template_arg, struct template_instance,
120 struct template_param, struct template, templates,
121 parse_template, expand_templates): New.
122 (process_i386_opcodes): Various local variables moved to
123 expand_templates. Call parse_template and expand_templates.
124 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
125 * i386-tbl.h: Re-generate.
127 2020-03-06 Jan Beulich <jbeulich@suse.com>
129 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
130 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
131 register and memory source templates. Replace VexW= by VexW*
133 * i386-tbl.h: Re-generate.
135 2020-03-06 Jan Beulich <jbeulich@suse.com>
137 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
138 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
139 * i386-tbl.h: Re-generate.
141 2020-03-06 Jan Beulich <jbeulich@suse.com>
143 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
144 * i386-tbl.h: Re-generate.
146 2020-03-06 Jan Beulich <jbeulich@suse.com>
148 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
149 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
150 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
151 VexW0 on SSE2AVX variants.
152 (vmovq): Drop NoRex64 from XMM/XMM variants.
153 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
154 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
155 applicable use VexW0.
156 * i386-tbl.h: Re-generate.
158 2020-03-06 Jan Beulich <jbeulich@suse.com>
160 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
161 * i386-opc.h (Rex64): Delete.
162 (struct i386_opcode_modifier): Remove rex64 field.
163 * i386-opc.tbl (crc32): Drop Rex64.
164 Replace Rex64 with Size64 everywhere else.
165 * i386-tbl.h: Re-generate.
167 2020-03-06 Jan Beulich <jbeulich@suse.com>
169 * i386-dis.c (OP_E_memory): Exclude recording of used address
170 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
171 addressed memory operands for MPX insns.
173 2020-03-06 Jan Beulich <jbeulich@suse.com>
175 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
176 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
177 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
178 (ptwrite): Split into non-64-bit and 64-bit forms.
179 * i386-tbl.h: Re-generate.
181 2020-03-06 Jan Beulich <jbeulich@suse.com>
183 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
185 * i386-tbl.h: Re-generate.
187 2020-03-04 Jan Beulich <jbeulich@suse.com>
189 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
190 (prefix_table): Move vmmcall here. Add vmgexit.
191 (rm_table): Replace vmmcall entry by prefix_table[] escape.
192 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
193 (cpu_flags): Add CpuSEV_ES entry.
194 * i386-opc.h (CpuSEV_ES): New.
195 (union i386_cpu_flags): Add cpusev_es field.
196 * i386-opc.tbl (vmgexit): New.
197 * i386-init.h, i386-tbl.h: Re-generate.
199 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
201 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
203 * i386-opc.h (IGNORESIZE): New.
204 (DEFAULTSIZE): Likewise.
205 (IgnoreSize): Removed.
206 (DefaultSize): Likewise.
208 (i386_opcode_modifier): Replace ignoresize/defaultsize with
210 * i386-opc.tbl (IgnoreSize): New.
211 (DefaultSize): Likewise.
212 * i386-tbl.h: Regenerated.
214 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
217 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
220 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
223 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
224 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
225 * i386-tbl.h: Regenerated.
227 2020-02-26 Alan Modra <amodra@gmail.com>
229 * aarch64-asm.c: Indent labels correctly.
230 * aarch64-dis.c: Likewise.
231 * aarch64-gen.c: Likewise.
232 * aarch64-opc.c: Likewise.
233 * alpha-dis.c: Likewise.
234 * i386-dis.c: Likewise.
235 * nds32-asm.c: Likewise.
236 * nfp-dis.c: Likewise.
237 * visium-dis.c: Likewise.
239 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
241 * arc-regs.h (int_vector_base): Make it available for all ARC
244 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
246 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
249 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
251 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
252 c.mv/c.li if rs1 is zero.
254 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
256 * i386-gen.c (cpu_flag_init): Replace CpuABM with
257 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
259 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
260 * i386-opc.h (CpuABM): Removed.
262 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
263 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
264 popcnt. Remove CpuABM from lzcnt.
265 * i386-init.h: Regenerated.
266 * i386-tbl.h: Likewise.
268 2020-02-17 Jan Beulich <jbeulich@suse.com>
270 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
271 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
272 VexW1 instead of open-coding them.
273 * i386-tbl.h: Re-generate.
275 2020-02-17 Jan Beulich <jbeulich@suse.com>
277 * i386-opc.tbl (AddrPrefixOpReg): Define.
278 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
279 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
280 templates. Drop NoRex64.
281 * i386-tbl.h: Re-generate.
283 2020-02-17 Jan Beulich <jbeulich@suse.com>
286 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
287 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
288 into Intel syntax instance (with Unpsecified) and AT&T one
290 (vcvtneps2bf16): Likewise, along with folding the two so far
292 * i386-tbl.h: Re-generate.
294 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
296 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
299 2020-02-17 Alan Modra <amodra@gmail.com>
301 * i386-gen.c (cpu_flag_init): Correct last change.
303 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
305 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
308 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
310 * i386-opc.tbl (movsx): Remove Intel syntax comments.
313 2020-02-14 Jan Beulich <jbeulich@suse.com>
316 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
317 destination for Cpu64-only variant.
318 (movzx): Fold patterns.
319 * i386-tbl.h: Re-generate.
321 2020-02-13 Jan Beulich <jbeulich@suse.com>
323 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
324 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
325 CPU_ANY_SSE4_FLAGS entry.
326 * i386-init.h: Re-generate.
328 2020-02-12 Jan Beulich <jbeulich@suse.com>
330 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
331 with Unspecified, making the present one AT&T syntax only.
332 * i386-tbl.h: Re-generate.
334 2020-02-12 Jan Beulich <jbeulich@suse.com>
336 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
337 * i386-tbl.h: Re-generate.
339 2020-02-12 Jan Beulich <jbeulich@suse.com>
342 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
343 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
344 Amd64 and Intel64 templates.
345 (call, jmp): Likewise for far indirect variants. Dro
347 * i386-tbl.h: Re-generate.
349 2020-02-11 Jan Beulich <jbeulich@suse.com>
351 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
352 * i386-opc.h (ShortForm): Delete.
353 (struct i386_opcode_modifier): Remove shortform field.
354 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
355 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
356 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
357 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
359 * i386-tbl.h: Re-generate.
361 2020-02-11 Jan Beulich <jbeulich@suse.com>
363 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
364 fucompi): Drop ShortForm from operand-less templates.
365 * i386-tbl.h: Re-generate.
367 2020-02-11 Alan Modra <amodra@gmail.com>
369 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
370 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
371 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
372 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
373 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
375 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
377 * arm-dis.c (print_insn_cde): Define 'V' parse character.
378 (cde_opcodes): Add VCX* instructions.
380 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
381 Matthew Malcomson <matthew.malcomson@arm.com>
383 * arm-dis.c (struct cdeopcode32): New.
384 (CDE_OPCODE): New macro.
385 (cde_opcodes): New disassembly table.
386 (regnames): New option to table.
387 (cde_coprocs): New global variable.
388 (print_insn_cde): New
389 (print_insn_thumb32): Use print_insn_cde.
390 (parse_arm_disassembler_options): Parse coprocN args.
392 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
395 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
397 * i386-opc.h (AMD64): Removed.
401 (INTEL64ONLY): Likewise.
402 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
403 * i386-opc.tbl (Amd64): New.
405 (Intel64Only): Likewise.
406 Replace AMD64 with Amd64. Update sysenter/sysenter with
407 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
408 * i386-tbl.h: Regenerated.
410 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
413 * z80-dis.c: Add support for GBZ80 opcodes.
415 2020-02-04 Alan Modra <amodra@gmail.com>
417 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
419 2020-02-03 Alan Modra <amodra@gmail.com>
421 * m32c-ibld.c: Regenerate.
423 2020-02-01 Alan Modra <amodra@gmail.com>
425 * frv-ibld.c: Regenerate.
427 2020-01-31 Jan Beulich <jbeulich@suse.com>
429 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
430 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
431 (OP_E_memory): Replace xmm_mdq_mode case label by
432 vex_scalar_w_dq_mode one.
433 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
435 2020-01-31 Jan Beulich <jbeulich@suse.com>
437 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
438 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
439 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
440 (intel_operand_size): Drop vex_w_dq_mode case label.
442 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
444 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
445 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
447 2020-01-30 Alan Modra <amodra@gmail.com>
449 * m32c-ibld.c: Regenerate.
451 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
453 * bpf-opc.c: Regenerate.
455 2020-01-30 Jan Beulich <jbeulich@suse.com>
457 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
458 (dis386): Use them to replace C2/C3 table entries.
459 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
460 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
461 ones. Use Size64 instead of DefaultSize on Intel64 ones.
462 * i386-tbl.h: Re-generate.
464 2020-01-30 Jan Beulich <jbeulich@suse.com>
466 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
468 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
470 * i386-tbl.h: Re-generate.
472 2020-01-30 Alan Modra <amodra@gmail.com>
474 * tic4x-dis.c (tic4x_dp): Make unsigned.
476 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
477 Jan Beulich <jbeulich@suse.com>
480 * i386-dis.c (MOVSXD_Fixup): New function.
481 (movsxd_mode): New enum.
482 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
483 (intel_operand_size): Handle movsxd_mode.
484 (OP_E_register): Likewise.
486 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
487 register on movsxd. Add movsxd with 16-bit destination register
488 for AMD64 and Intel64 ISAs.
489 * i386-tbl.h: Regenerated.
491 2020-01-27 Tamar Christina <tamar.christina@arm.com>
494 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
495 * aarch64-asm-2.c: Regenerate
496 * aarch64-dis-2.c: Likewise.
497 * aarch64-opc-2.c: Likewise.
499 2020-01-21 Jan Beulich <jbeulich@suse.com>
501 * i386-opc.tbl (sysret): Drop DefaultSize.
502 * i386-tbl.h: Re-generate.
504 2020-01-21 Jan Beulich <jbeulich@suse.com>
506 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
508 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
509 * i386-tbl.h: Re-generate.
511 2020-01-20 Nick Clifton <nickc@redhat.com>
513 * po/de.po: Updated German translation.
514 * po/pt_BR.po: Updated Brazilian Portuguese translation.
515 * po/uk.po: Updated Ukranian translation.
517 2020-01-20 Alan Modra <amodra@gmail.com>
519 * hppa-dis.c (fput_const): Remove useless cast.
521 2020-01-20 Alan Modra <amodra@gmail.com>
523 * arm-dis.c (print_insn_arm): Wrap 'T' value.
525 2020-01-18 Nick Clifton <nickc@redhat.com>
527 * configure: Regenerate.
528 * po/opcodes.pot: Regenerate.
530 2020-01-18 Nick Clifton <nickc@redhat.com>
532 Binutils 2.34 branch created.
534 2020-01-17 Christian Biesinger <cbiesinger@google.com>
536 * opintl.h: Fix spelling error (seperate).
538 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
540 * i386-opc.tbl: Add {vex} pseudo prefix.
541 * i386-tbl.h: Regenerated.
543 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
546 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
547 (neon_opcodes): Likewise.
548 (select_arm_features): Make sure we enable MVE bits when selecting
549 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
552 2020-01-16 Jan Beulich <jbeulich@suse.com>
554 * i386-opc.tbl: Drop stale comment from XOP section.
556 2020-01-16 Jan Beulich <jbeulich@suse.com>
558 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
559 (extractps): Add VexWIG to SSE2AVX forms.
560 * i386-tbl.h: Re-generate.
562 2020-01-16 Jan Beulich <jbeulich@suse.com>
564 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
565 Size64 from and use VexW1 on SSE2AVX forms.
566 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
567 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
568 * i386-tbl.h: Re-generate.
570 2020-01-15 Alan Modra <amodra@gmail.com>
572 * tic4x-dis.c (tic4x_version): Make unsigned long.
573 (optab, optab_special, registernames): New file scope vars.
574 (tic4x_print_register): Set up registernames rather than
575 malloc'd registertable.
576 (tic4x_disassemble): Delete optable and optable_special. Use
577 optab and optab_special instead. Throw away old optab,
578 optab_special and registernames when info->mach changes.
580 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
583 * z80-dis.c (suffix): Use .db instruction to generate double
586 2020-01-14 Alan Modra <amodra@gmail.com>
588 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
589 values to unsigned before shifting.
591 2020-01-13 Thomas Troeger <tstroege@gmx.de>
593 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
595 (print_insn_thumb16, print_insn_thumb32): Likewise.
596 (print_insn): Initialize the insn info.
597 * i386-dis.c (print_insn): Initialize the insn info fields, and
600 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
602 * arc-opc.c (C_NE): Make it required.
604 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
606 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
607 reserved register name.
609 2020-01-13 Alan Modra <amodra@gmail.com>
611 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
612 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
614 2020-01-13 Alan Modra <amodra@gmail.com>
616 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
617 result of wasm_read_leb128 in a uint64_t and check that bits
618 are not lost when copying to other locals. Use uint32_t for
619 most locals. Use PRId64 when printing int64_t.
621 2020-01-13 Alan Modra <amodra@gmail.com>
623 * score-dis.c: Formatting.
624 * score7-dis.c: Formatting.
626 2020-01-13 Alan Modra <amodra@gmail.com>
628 * score-dis.c (print_insn_score48): Use unsigned variables for
629 unsigned values. Don't left shift negative values.
630 (print_insn_score32): Likewise.
631 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
633 2020-01-13 Alan Modra <amodra@gmail.com>
635 * tic4x-dis.c (tic4x_print_register): Remove dead code.
637 2020-01-13 Alan Modra <amodra@gmail.com>
639 * fr30-ibld.c: Regenerate.
641 2020-01-13 Alan Modra <amodra@gmail.com>
643 * xgate-dis.c (print_insn): Don't left shift signed value.
644 (ripBits): Formatting, use 1u.
646 2020-01-10 Alan Modra <amodra@gmail.com>
648 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
649 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
651 2020-01-10 Alan Modra <amodra@gmail.com>
653 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
654 and XRREG value earlier to avoid a shift with negative exponent.
655 * m10200-dis.c (disassemble): Similarly.
657 2020-01-09 Nick Clifton <nickc@redhat.com>
660 * z80-dis.c (ld_ii_ii): Use correct cast.
662 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
665 * z80-dis.c (ld_ii_ii): Use character constant when checking
668 2020-01-09 Jan Beulich <jbeulich@suse.com>
670 * i386-dis.c (SEP_Fixup): New.
672 (dis386_twobyte): Use it for sysenter/sysexit.
673 (enum x86_64_isa): Change amd64 enumerator to value 1.
674 (OP_J): Compare isa64 against intel64 instead of amd64.
675 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
677 * i386-tbl.h: Re-generate.
679 2020-01-08 Alan Modra <amodra@gmail.com>
681 * z8k-dis.c: Include libiberty.h
682 (instr_data_s): Make max_fetched unsigned.
683 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
684 Don't exceed byte_info bounds.
685 (output_instr): Make num_bytes unsigned.
686 (unpack_instr): Likewise for nibl_count and loop.
687 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
689 * z8k-opc.h: Regenerate.
691 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
693 * arc-tbl.h (llock): Use 'LLOCK' as class.
695 (scond): Use 'SCOND' as class.
697 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
700 2020-01-06 Alan Modra <amodra@gmail.com>
702 * m32c-ibld.c: Regenerate.
704 2020-01-06 Alan Modra <amodra@gmail.com>
707 * z80-dis.c (suffix): Don't use a local struct buffer copy.
708 Peek at next byte to prevent recursion on repeated prefix bytes.
709 Ensure uninitialised "mybuf" is not accessed.
710 (print_insn_z80): Don't zero n_fetch and n_used here,..
711 (print_insn_z80_buf): ..do it here instead.
713 2020-01-04 Alan Modra <amodra@gmail.com>
715 * m32r-ibld.c: Regenerate.
717 2020-01-04 Alan Modra <amodra@gmail.com>
719 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
721 2020-01-04 Alan Modra <amodra@gmail.com>
723 * crx-dis.c (match_opcode): Avoid shift left of signed value.
725 2020-01-04 Alan Modra <amodra@gmail.com>
727 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
729 2020-01-03 Jan Beulich <jbeulich@suse.com>
731 * aarch64-tbl.h (aarch64_opcode_table): Use
732 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
734 2020-01-03 Jan Beulich <jbeulich@suse.com>
736 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
737 forms of SUDOT and USDOT.
739 2020-01-03 Jan Beulich <jbeulich@suse.com>
741 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
743 * opcodes/aarch64-dis-2.c: Re-generate.
745 2020-01-03 Jan Beulich <jbeulich@suse.com>
747 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
749 * opcodes/aarch64-dis-2.c: Re-generate.
751 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
753 * z80-dis.c: Add support for eZ80 and Z80 instructions.
755 2020-01-01 Alan Modra <amodra@gmail.com>
757 Update year range in copyright notice of all files.
759 For older changes see ChangeLog-2019
761 Copyright (C) 2020 Free Software Foundation, Inc.
763 Copying and distribution of this file, with or without modification,
764 are permitted in any medium without royalty provided the copyright
765 notice and this notice are preserved.
771 version-control: never