1 2017-12-19 Tamar Christina <tamar.christina@arm.com>
4 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
6 2017-12-18 Jan Beulich <jbeulich@suse.com>
8 * i386-gen.c (operand_type_init): Delete OPERAND_TYPE_REGYMM and
9 OPERAND_TYPE_REGZMM entries.
10 * i386-opc.h (enum of opcode modifiers): Extend comment.
11 i386-opc.tbl (vaddpd, vaddps, vaddsubpd, vaddsubps, vandnpd,
12 vandnps, vandpd, vandps, vblendpd, vblendps, vblendvpd,
13 vblendvps, vbroadcastss, vcmpeq_ospd, vcmpeq_osps, vcmpeqpd,
14 vcmpeqps, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uspd, vcmpeq_usps,
15 vcmpfalse_ospd, vcmpfalse_osps, vcmpfalsepd, vcmpfalseps,
16 vcmpge_oqpd, vcmpge_oqps, vcmpgepd, vcmpgeps, vcmpgt_oqpd,
17 vcmpgt_oqps, vcmpgtpd, vcmpgtps, vcmple_oqpd, vcmple_oqps,
18 vcmplepd, vcmpleps, vcmplt_oqpd, vcmplt_oqps, vcmpltpd,
19 vcmpltps, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_ospd,
20 vcmpneq_osps, vcmpneqpd, vcmpneqps, vcmpneq_uspd, vcmpneq_usps,
21 vcmpngepd, vcmpngeps, vcmpnge_uqpd, vcmpnge_uqps, vcmpngtpd,
22 vcmpngtps, vcmpngt_uqpd, vcmpngt_uqps, vcmpnlepd, vcmpnleps,
23 vcmpnle_uqpd, vcmpnle_uqps, vcmpnltpd, vcmpnltps, vcmpnlt_uqpd,
24 vcmpnlt_uqps, vcmpordpd, vcmpordps, vcmpord_spd, vcmpord_sps,
25 vcmppd, vcmpps, vcmptruepd, vcmptrueps, vcmptrue_uspd,
26 vcmptrue_usps, vcmpunordpd, vcmpunordps, vcmpunord_spd,
27 vcmpunord_sps, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps, vcvtps2dq,
28 vcvttpd2dq, vcvttps2dq, vdivpd, vdivps, vdpps, vhaddpd, vhaddps,
29 vhsubpd, vhsubps, vlddqu, vmaskmovpd, vmaskmovps, vmaxpd,
30 vmaxps, vminpd, vminps, vmovapd, vmovaps, vmovdqa, vmovdqu,
31 vmovmskpd, vmovmskps, vmovntdq, vmovntpd, vmovntps, vmovshdup,
32 vmovsldup, vmovupd, vmovups, vmulpd, vmulps, vorpd, vorps,
33 vpermilpd, vpermilps, vptest, vrcpps, vroundpd, vroundps,
34 vrsqrtps, vshufpd, vshufps, vsqrtpd, vsqrtps, vsubpd, vsubps,
35 vtestpd, vtestps, vunpckhpd, vunpckhps, vunpcklpd, vunpcklps,
36 vxorpd, vxorps, vpblendd, vpbroadcastb, vpbroadcastd,
37 vpbroadcastw, vpbroadcastq, vpmaskmovd, vpmaskmovq, vpsllvd,
38 vpsllvq, vpsravd, vpsravq, vpsrlvd, vpsrlvq): Fold 128- and
39 256-bit forms. Use CheckRegSize instead of IgnoreSize where
40 appropriate. Drop Xmmword and Ymmword from the results where
42 * i386-tbl.h: Re-generate.
44 2017-12-18 Jan Beulich <jbeulich@suse.com>
46 * i386-gen.c (operand_type_shorthands): Add RegXMM, RegYMM, and
48 (opcode_modifiers): Drop FirstXmm0.
49 (operand_types): Replace RegXMM, RegYMM, and RegZMM with just
51 * i386-opc.h (enum of opcode modifiers): Drop FirstXmm0.
52 (struct i386_opcode_modifier): Drop firstxmm0.
53 (enum of operand types): Replace RegXMM, RegYMM, and RegZMM with
54 just RegSIMD. Extend comment.
55 (union i386_operand_type): Replace regxmm, regymm, and regzmm
57 * i386-opc.tbl (blendvpd, blendvps, pblendvb, sha256rnds2): Use
59 * i386-reg.tbl (xmm0): Add Acc.
60 * i386-init.h, i386-tbl.h: Re-generate.
62 2017-12-18 Jan Beulich <jbeulich@suse.com>
64 * i386-gen.c (operand_type_shorthands): Add FloatAcc and
66 (operand_types): Drop FloatAcc and FloatReg.
67 * i386-opc.h (enum of operand types): Likewise. Extend comment.
68 (union i386_operand_type): Drop floatacc and floatreg.
69 * i386-reg.tbl (st, st(0)): Replace FloatAcc by Acc.
70 * i386-init.h, i386-tbl.h: Re-generate.
72 2017-12-18 Jan Beulich <jbeulich@suse.com>
74 * i386-gen.c (operand_type_shorthands): New.
75 (opcode_modifiers): Replace Reg<N> with just Reg.
76 (set_bitfield_from_cpu_flag_init): Rename to
77 set_bitfield_from_shorthand. Drop value parameter. Process
78 operand_type_shorthands.
79 (set_bitfield): Adjust call accordingly.
80 * i386-opc.h (enum of operand types): Replace Reg<N> with just
82 (union i386_operand_type): Replace reg<N> with just reg.
83 * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
84 vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
85 separate register and memory forms.
86 * i386-reg.tbl (al): Drop Byte.
90 * i386-init.h, i386-tbl.h: Re-generate.
92 2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
94 * disassemble.c (disassemble_init_for_target): Don't put PRU
95 between powerpc and rs6000 cases.
97 2017-12-15 Jan Beulich <jbeulich@suse.com>
99 * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
100 movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
101 sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
102 stos, sub, test, xor): Drop CheckRegSize from variants not
103 allowing for two (or more) register operands.
104 * i386-tbl.h: Re-generate.
106 2017-12-13 Jim Wilson <jimw@sifive.com>
109 * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
111 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
113 * disassemble.c: Enable disassembler_needs_relocs for PRU.
115 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
116 Renlin Li <renlin.li@arm.com>
118 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
119 (get_sym_code_type): Here.
121 2017-12-03 Alan Modra <amodra@gmail.com>
123 * ppc-opc.c (extract_li20): Rewrite.
125 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
127 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
128 (operand_value_powerpc): Update return and argument type.
129 <value, top>: Update type.
130 (skip_optional_operands): Update argument type.
131 (lookup_powerpc): Likewise.
132 (lookup_vle): Likewise.
133 <table_opcd, table_mask, insn2>: Update type.
134 (lookup_spe2): Update argument type.
135 <table_opcd, table_mask, insn2>: Update type.
136 (print_insn_powerpc) <insn, value>: Update type.
137 Use PPC_INT_FMT for printing instructions and operands.
138 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
139 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
140 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
141 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
142 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
143 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
144 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
145 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
146 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
147 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
148 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
149 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
150 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
151 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
152 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
153 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
154 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
155 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
156 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
157 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
158 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
159 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
160 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
161 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
162 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
163 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
164 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
165 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
166 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
167 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
168 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
169 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
170 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
171 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
172 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
173 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
174 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
176 2017-11-29 Jan Beulich <jbeulich@suse.com>
178 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
180 (output_cpu_flags): Update active_cpu_flags.
181 (process_i386_opcode_modifier): Update active_isstring.
182 (output_operand_type): Rename "macro" parameter to "stage",
184 (process_i386_operand_type): Likewise. Track presence of
185 BaseIndex and emit DispN accordingly.
186 (output_i386_opcode, process_i386_registers,
187 process_i386_initializers): Adjust calls to
188 process_i386_operand_type() for its changed parameter type.
189 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
190 all insns operands having BaseIndex set.
191 * i386-tbl.h: Re-generate.
193 2017-11-29 Jan Beulich <jbeulich@suse.com>
195 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
197 (operand_types): Remove Vec_Disp8 entry.
198 * i386-opc.h (Vec_Disp8): Delete.
199 (union i386_operand_type): Remove vec_disp8.
200 (i386-opc.tbl): Remove Vec_Disp8.
201 * i386-init.h, i386-tbl.h: Re-generate.
203 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
205 * po/Make-in (datadir): Define as @datadir@.
206 (localedir): Define as @localedir@.
207 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
209 2017-11-27 Nick Clifton <nickc@redhat.com>
211 * po/zh_CN.po: Updated simplified Chinese translation.
213 2017-11-24 Jan Beulich <jbeulich@suse.com>
215 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
218 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
220 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
221 * i386-tbl.h: Regenerate.
223 2017-11-23 Jan Beulich <jbeulich@suse.com>
225 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
226 the 16-bit addressing case.
228 2017-11-23 Jan Beulich <jbeulich@suse.com>
230 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
231 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
232 * i386-opc.tbl (ud1, ud2b): Add operands.
234 * i386-tbl.h: Re-generate.
236 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
238 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
239 * i386-tbl.h: Regenerate.
241 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
243 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
244 * i386-tbl.h: Regenerate.
246 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
248 *arc-opc (insert_rhv2): Check h-regs range.
250 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
252 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
253 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
255 2017-11-16 Tamar Christina <tamar.christina@arm.com>
257 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
258 and AARCH64_FEATURE_F16.
260 2017-11-16 Tamar Christina <tamar.christina@arm.com>
262 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
263 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
264 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
265 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
266 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
267 (ldapur, ldapursw, stlur): New.
268 * aarch64-dis-2.c: Regenerate.
270 2017-11-16 Jan Beulich <jbeulich@suse.com>
272 (get_valid_dis386): Never flag bad opcode when
273 vex.register_specifier is beyond 7. Always store all four
274 bits of it. Move 16-/32-bit override in EVEX handling after
275 all to be overridden bits have been set.
276 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
277 Use rex to determine GPR register set.
278 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
279 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
281 2017-11-15 Jan Beulich <jbeulich@suse.com>
283 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
284 determine GPR register set.
286 2017-11-15 Jan Beulich <jbeulich@suse.com>
288 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
289 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
290 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
292 (OP_REG_VexI4): Drop low 4 bits check.
294 2017-11-15 Jan Beulich <jbeulich@suse.com>
296 * i386-reg.tbl (axl): Remove Acc and Byte.
297 * i386-tbl.h: Re-generate.
299 2017-11-14 Jan Beulich <jbeulich@suse.com>
301 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
302 (vex_len_table): Use VPCOM.
304 2017-11-14 Jan Beulich <jbeulich@suse.com>
306 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
307 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
308 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
310 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
311 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
312 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
313 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
315 * i386-tbl.h: Re-generate.
317 2017-11-14 Jan Beulich <jbeulich@suse.com>
319 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
320 smov, ssca, stos, ssto, xlat): Drop Disp*.
321 * i386-tbl.h: Re-generate.
323 2017-11-13 Jan Beulich <jbeulich@suse.com>
325 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
326 xsaveopt64): Add No_qSuf.
327 * i386-tbl.h: Re-generate.
329 2017-11-09 Tamar Christina <tamar.christina@arm.com>
331 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
332 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
333 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
334 sder32_el2, vncr_el2.
335 (aarch64_sys_reg_supported_p): Likewise.
336 (aarch64_pstatefields): Add dit register.
337 (aarch64_pstatefield_supported_p): Likewise.
338 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
339 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
340 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
341 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
342 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
343 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
344 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
346 2017-11-09 Tamar Christina <tamar.christina@arm.com>
348 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
349 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
350 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
351 (QL_STLW, QL_STLX): New.
353 2017-11-09 Tamar Christina <tamar.christina@arm.com>
355 * aarch64-asm.h (ins_addr_offset): New.
356 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
357 (aarch64_ins_addr_offset): New.
358 * aarch64-asm-2.c: Regenerate.
359 * aarch64-dis.h (ext_addr_offset): New.
360 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
361 (aarch64_ext_addr_offset): New.
362 * aarch64-dis-2.c: Regenerate.
363 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
364 FLD_imm4_2 and FLD_SM3_imm2.
365 * aarch64-opc.c (fields): Add FLD_imm6_2,
366 FLD_imm4_2 and FLD_SM3_imm2.
367 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
368 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
369 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
370 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
372 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
374 2017-11-09 Tamar Christina <tamar.christina@arm.com>
377 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
378 (aarch64_feature_sm4, aarch64_feature_sha3): New.
379 (aarch64_feature_fp_16_v8_2): New.
380 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
381 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
382 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
384 2017-11-08 Tamar Christina <tamar.christina@arm.com>
386 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
387 (aarch64_feature_sha2, aarch64_feature_aes): New.
389 (AES_INSN, SHA2_INSN): New.
390 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
391 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
392 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
395 2017-11-08 Jiong Wang <jiong.wang@arm.com>
396 Tamar Christina <tamar.christina@arm.com>
398 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
399 FP16 instructions, including vfmal.f16 and vfmsl.f16.
401 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
403 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
405 2017-11-07 Alan Modra <amodra@gmail.com>
407 * opintl.h: Formatting, comment fixes.
408 (gettext, ngettext): Redefine when ENABLE_NLS.
409 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
410 (_): Define using gettext.
411 (textdomain, bindtextdomain): Use safer "do nothing".
413 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
415 * arc-dis.c (print_hex): New variable.
416 (parse_option): Check for hex option.
417 (print_insn_arc): Use hexadecimal representation for short
418 immediate values when requested.
419 (print_arc_disassembler_options): Add hex option to the list.
421 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
423 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
424 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
425 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
426 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
427 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
428 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
429 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
430 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
431 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
432 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
433 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
434 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
435 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
436 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
437 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
438 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
439 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
440 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
441 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
443 (prealloc, prefetch*): Place them before ld instruction.
444 * arc-opc.c (skip_this_opcode): Add ARITH class.
446 2017-10-25 Alan Modra <amodra@gmail.com>
449 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
450 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
451 (imm4flag, size_changed): Likewise.
452 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
453 (words, allWords, processing_argument_number): Likewise.
454 (cst4flag, size_changed): Likewise.
455 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
456 (crx_cst4_maps): Rename from cst4_maps.
457 (crx_no_op_insn): Rename from no_op_insn.
459 2017-10-24 Andrew Waterman <andrew@sifive.com>
461 * riscv-opc.c (match_c_addi16sp) : New function.
462 (match_c_addi4spn): New function.
463 (match_c_lui): Don't allow 0-immediate encodings.
464 (riscv_opcodes) <addi>: Use the above functions.
466 <c.addi4spn>: Likewise.
467 <c.addi16sp>: Likewise.
469 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
471 * i386-init.h: Regenerate
472 * i386-tbl.h: Likewise
474 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
476 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
477 (enum): Add EVEX_W_0F3854_P_2.
478 * i386-dis-evex.h (evex_table): Updated.
479 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
480 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
481 (cpu_flags): Add CpuAVX512_BITALG.
482 * i386-opc.h (enum): Add CpuAVX512_BITALG.
483 (i386_cpu_flags): Add cpuavx512_bitalg..
484 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
485 * i386-init.h: Regenerate.
486 * i386-tbl.h: Likewise.
488 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
490 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
491 * i386-dis-evex.h (evex_table): Updated.
492 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
493 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
494 (cpu_flags): Add CpuAVX512_VNNI.
495 * i386-opc.h (enum): Add CpuAVX512_VNNI.
496 (i386_cpu_flags): Add cpuavx512_vnni.
497 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
498 * i386-init.h: Regenerate.
499 * i386-tbl.h: Likewise.
501 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
503 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
504 (enum): Remove VEX_LEN_0F3A44_P_2.
505 (vex_len_table): Ditto.
506 (enum): Remove VEX_W_0F3A44_P_2.
507 (vew_w_table): Ditto.
508 (prefix_table): Adjust instructions (see prefixes above).
509 * i386-dis-evex.h (evex_table):
510 Add new instructions (see prefixes above).
511 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
512 (bitfield_cpu_flags): Ditto.
513 * i386-opc.h (enum): Ditto.
514 (i386_cpu_flags): Ditto.
515 (CpuUnused): Comment out to avoid zero-width field problem.
516 * i386-opc.tbl (vpclmulqdq): New instruction.
517 * i386-init.h: Regenerate.
520 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
522 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
523 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
524 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
525 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
526 (vex_len_table): Ditto.
527 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
528 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
529 (vew_w_table): Ditto.
530 (prefix_table): Adjust instructions (see prefixes above).
531 * i386-dis-evex.h (evex_table):
532 Add new instructions (see prefixes above).
533 * i386-gen.c (cpu_flag_init): Add VAES.
534 (bitfield_cpu_flags): Ditto.
535 * i386-opc.h (enum): Ditto.
536 (i386_cpu_flags): Ditto.
537 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
538 * i386-init.h: Regenerate.
541 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
543 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
544 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
545 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
546 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
547 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
548 (prefix_table): Updated (see prefixes above).
549 (three_byte_table): Likewise.
550 (vex_w_table): Likewise.
551 * i386-dis-evex.h: Likewise.
552 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
553 (cpu_flags): Add CpuGFNI.
554 * i386-opc.h (enum): Add CpuGFNI.
555 (i386_cpu_flags): Add cpugfni.
556 * i386-opc.tbl: Add Intel GFNI instructions.
557 * i386-init.h: Regenerate.
558 * i386-tbl.h: Likewise.
560 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
562 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
563 Define EXbScalar and EXwScalar for OP_EX.
564 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
565 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
566 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
567 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
568 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
569 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
570 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
571 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
572 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
573 (OP_E_memory): Likewise.
574 * i386-dis-evex.h: Updated.
575 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
576 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
577 (cpu_flags): Add CpuAVX512_VBMI2.
578 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
579 (i386_cpu_flags): Add cpuavx512_vbmi2.
580 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
581 * i386-init.h: Regenerate.
582 * i386-tbl.h: Likewise.
584 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
586 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
588 2017-10-12 James Bowman <james.bowman@ftdichip.com>
590 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
591 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
592 K15. Add jmpix pattern.
594 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
596 * s390-opc.txt (prno, tpei, irbm): New instructions added.
598 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
600 * s390-opc.c (INSTR_SI_RD): New macro.
601 (INSTR_S_RD): Adjust example instruction.
602 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
605 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
607 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
608 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
609 VLE multimple load/store instructions. Old e_ldm* variants are
611 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
613 2017-09-27 Nick Clifton <nickc@redhat.com>
616 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
617 names for the fmv.x.s and fmv.s.x instructions respectively.
619 2017-09-26 do <do@nerilex.org>
622 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
623 be used on CPUs that have emacs support.
625 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
627 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
629 2017-09-09 Kamil Rytarowski <n54@gmx.com>
631 * nds32-asm.c: Rename __BIT() to N32_BIT().
632 * nds32-asm.h: Likewise.
633 * nds32-dis.c: Likewise.
635 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
637 * i386-dis.c (last_active_prefix): Removed.
638 (ckprefix): Don't set last_active_prefix.
639 (NOTRACK_Fixup): Don't check last_active_prefix.
641 2017-08-31 Nick Clifton <nickc@redhat.com>
643 * po/fr.po: Updated French translation.
645 2017-08-31 James Bowman <james.bowman@ftdichip.com>
647 * ft32-dis.c (print_insn_ft32): Correct display of non-address
650 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
651 Edmar Wienskoski <edmar.wienskoski@nxp.com>
653 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
654 PPC_OPCODE_EFS2 flag to "e200z4" entry.
655 New entries efs2 and spe2.
656 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
657 (SPE2_OPCD_SEGS): New macro.
658 (spe2_opcd_indices): New.
659 (disassemble_init_powerpc): Handle SPE2 opcodes.
660 (lookup_spe2): New function.
661 (print_insn_powerpc): call lookup_spe2.
662 * ppc-opc.c (insert_evuimm1_ex0): New function.
663 (extract_evuimm1_ex0): Likewise.
664 (insert_evuimm_lt8): Likewise.
665 (extract_evuimm_lt8): Likewise.
666 (insert_off_spe2): Likewise.
667 (extract_off_spe2): Likewise.
668 (insert_Ddd): Likewise.
669 (extract_Ddd): Likewise.
671 (EVUIMM_LT8): Likewise.
672 (EVUIMM_LT16): Adjust.
674 (EVUIMM_1): Likewise.
675 (EVUIMM_1_EX0): Likewise.
678 (VX_OFF_SPE2): Likewise.
681 (VX_MASK_DDD): New mask.
683 (VX_RA_CONST): New macro.
684 (VX_RA_CONST_MASK): Likewise.
685 (VX_RB_CONST): Likewise.
686 (VX_RB_CONST_MASK): Likewise.
687 (VX_OFF_SPE2_MASK): Likewise.
688 (VX_SPE_CRFD): Likewise.
689 (VX_SPE_CRFD_MASK VX): Likewise.
690 (VX_SPE2_CLR): Likewise.
691 (VX_SPE2_CLR_MASK): Likewise.
692 (VX_SPE2_SPLATB): Likewise.
693 (VX_SPE2_SPLATB_MASK): Likewise.
694 (VX_SPE2_OCTET): Likewise.
695 (VX_SPE2_OCTET_MASK): Likewise.
696 (VX_SPE2_DDHH): Likewise.
697 (VX_SPE2_DDHH_MASK): Likewise.
698 (VX_SPE2_HH): Likewise.
699 (VX_SPE2_HH_MASK): Likewise.
700 (VX_SPE2_EVMAR): Likewise.
701 (VX_SPE2_EVMAR_MASK): Likewise.
704 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
705 (powerpc_macros): Map old SPE instructions have new names
706 with the same opcodes. Add SPE2 instructions which just are
708 (spe2_opcodes): Add SPE2 opcodes.
710 2017-08-23 Alan Modra <amodra@gmail.com>
712 * ppc-opc.c: Formatting and comment fixes. Move insert and
713 extract functions earlier, deleting forward declarations.
714 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
717 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
719 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
721 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
722 Edmar Wienskoski <edmar.wienskoski@nxp.com>
724 * ppc-opc.c (insert_evuimm2_ex0): New function.
725 (extract_evuimm2_ex0): Likewise.
726 (insert_evuimm4_ex0): Likewise.
727 (extract_evuimm4_ex0): Likewise.
728 (insert_evuimm8_ex0): Likewise.
729 (extract_evuimm8_ex0): Likewise.
730 (insert_evuimm_lt16): Likewise.
731 (extract_evuimm_lt16): Likewise.
732 (insert_rD_rS_even): Likewise.
733 (extract_rD_rS_even): Likewise.
734 (insert_off_lsp): Likewise.
735 (extract_off_lsp): Likewise.
736 (RD_EVEN): New operand.
739 (EVUIMM_LT16): New operand.
741 (EVUIMM_2_EX0): New operand.
743 (EVUIMM_4_EX0): New operand.
745 (EVUIMM_8_EX0): New operand.
747 (VX_OFF): New operand.
749 (VX_LSP_MASK): Likewise.
750 (VX_LSP_OFF_MASK): Likewise.
751 (PPC_OPCODE_LSP): Likewise.
752 (vle_opcodes): Add LSP opcodes.
753 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
755 2017-08-09 Jiong Wang <jiong.wang@arm.com>
757 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
758 register operands in CRC instructions.
759 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
762 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
764 * disassemble.c (disassembler): Mark big and mach with
767 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
769 * disassemble.c (disassembler): Remove arch/mach/endian
772 2017-07-25 Nick Clifton <nickc@redhat.com>
775 * arc-opc.c (insert_rhv2): Use lower case first letter in error
777 (insert_r0): Likewise.
778 (insert_r1): Likewise.
779 (insert_r2): Likewise.
780 (insert_r3): Likewise.
781 (insert_sp): Likewise.
782 (insert_gp): Likewise.
783 (insert_pcl): Likewise.
784 (insert_blink): Likewise.
785 (insert_ilink1): Likewise.
786 (insert_ilink2): Likewise.
787 (insert_ras): Likewise.
788 (insert_rbs): Likewise.
789 (insert_rcs): Likewise.
790 (insert_simm3s): Likewise.
791 (insert_rrange): Likewise.
792 (insert_r13el): Likewise.
793 (insert_fpel): Likewise.
794 (insert_blinkel): Likewise.
795 (insert_pclel): Likewise.
796 (insert_nps_bitop_size_2b): Likewise.
797 (insert_nps_imm_offset): Likewise.
798 (insert_nps_imm_entry): Likewise.
799 (insert_nps_size_16bit): Likewise.
800 (insert_nps_##NAME##_pos): Likewise.
801 (insert_nps_##NAME): Likewise.
802 (insert_nps_bitop_ins_ext): Likewise.
803 (insert_nps_##NAME): Likewise.
804 (insert_nps_min_hofs): Likewise.
805 (insert_nps_##NAME): Likewise.
806 (insert_nps_rbdouble_64): Likewise.
807 (insert_nps_misc_imm_offset): Likewise.
808 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
811 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
812 Jiong Wang <jiong.wang@arm.com>
814 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
816 * aarch64-dis-2.c: Regenerated.
818 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
820 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
823 2017-07-20 Nick Clifton <nickc@redhat.com>
825 * po/de.po: Updated German translation.
827 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
829 * arc-regs.h (sec_stat): New aux register.
830 (aux_kernel_sp): Likewise.
831 (aux_sec_u_sp): Likewise.
832 (aux_sec_k_sp): Likewise.
833 (sec_vecbase_build): Likewise.
834 (nsc_table_top): Likewise.
835 (nsc_table_base): Likewise.
836 (ersec_stat): Likewise.
837 (aux_sec_except): Likewise.
839 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
841 * arc-opc.c (extract_uimm12_20): New function.
842 (UIMM12_20): New operand.
844 * arc-tbl.h (sjli): Add new instruction.
846 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
847 John Eric Martin <John.Martin@emmicro-us.com>
849 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
850 (UIMM3_23): Adjust accordingly.
851 * arc-regs.h: Add/correct jli_base register.
852 * arc-tbl.h (jli_s): Likewise.
854 2017-07-18 Nick Clifton <nickc@redhat.com>
857 * aarch64-opc.c: Fix spelling typos.
858 * i386-dis.c: Likewise.
860 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
862 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
863 max_addr_offset and octets variables to size_t.
865 2017-07-12 Alan Modra <amodra@gmail.com>
867 * po/da.po: Update from translationproject.org/latest/opcodes/.
868 * po/de.po: Likewise.
869 * po/es.po: Likewise.
870 * po/fi.po: Likewise.
871 * po/fr.po: Likewise.
872 * po/id.po: Likewise.
873 * po/it.po: Likewise.
874 * po/nl.po: Likewise.
875 * po/pt_BR.po: Likewise.
876 * po/ro.po: Likewise.
877 * po/sv.po: Likewise.
878 * po/tr.po: Likewise.
879 * po/uk.po: Likewise.
880 * po/vi.po: Likewise.
881 * po/zh_CN.po: Likewise.
883 2017-07-11 Yao Qi <yao.qi@linaro.org>
884 Alan Modra <amodra@gmail.com>
886 * cgen.sh: Mark generated files read-only.
887 * epiphany-asm.c: Regenerate.
888 * epiphany-desc.c: Regenerate.
889 * epiphany-desc.h: Regenerate.
890 * epiphany-dis.c: Regenerate.
891 * epiphany-ibld.c: Regenerate.
892 * epiphany-opc.c: Regenerate.
893 * epiphany-opc.h: Regenerate.
894 * fr30-asm.c: Regenerate.
895 * fr30-desc.c: Regenerate.
896 * fr30-desc.h: Regenerate.
897 * fr30-dis.c: Regenerate.
898 * fr30-ibld.c: Regenerate.
899 * fr30-opc.c: Regenerate.
900 * fr30-opc.h: Regenerate.
901 * frv-asm.c: Regenerate.
902 * frv-desc.c: Regenerate.
903 * frv-desc.h: Regenerate.
904 * frv-dis.c: Regenerate.
905 * frv-ibld.c: Regenerate.
906 * frv-opc.c: Regenerate.
907 * frv-opc.h: Regenerate.
908 * ip2k-asm.c: Regenerate.
909 * ip2k-desc.c: Regenerate.
910 * ip2k-desc.h: Regenerate.
911 * ip2k-dis.c: Regenerate.
912 * ip2k-ibld.c: Regenerate.
913 * ip2k-opc.c: Regenerate.
914 * ip2k-opc.h: Regenerate.
915 * iq2000-asm.c: Regenerate.
916 * iq2000-desc.c: Regenerate.
917 * iq2000-desc.h: Regenerate.
918 * iq2000-dis.c: Regenerate.
919 * iq2000-ibld.c: Regenerate.
920 * iq2000-opc.c: Regenerate.
921 * iq2000-opc.h: Regenerate.
922 * lm32-asm.c: Regenerate.
923 * lm32-desc.c: Regenerate.
924 * lm32-desc.h: Regenerate.
925 * lm32-dis.c: Regenerate.
926 * lm32-ibld.c: Regenerate.
927 * lm32-opc.c: Regenerate.
928 * lm32-opc.h: Regenerate.
929 * lm32-opinst.c: Regenerate.
930 * m32c-asm.c: Regenerate.
931 * m32c-desc.c: Regenerate.
932 * m32c-desc.h: Regenerate.
933 * m32c-dis.c: Regenerate.
934 * m32c-ibld.c: Regenerate.
935 * m32c-opc.c: Regenerate.
936 * m32c-opc.h: Regenerate.
937 * m32r-asm.c: Regenerate.
938 * m32r-desc.c: Regenerate.
939 * m32r-desc.h: Regenerate.
940 * m32r-dis.c: Regenerate.
941 * m32r-ibld.c: Regenerate.
942 * m32r-opc.c: Regenerate.
943 * m32r-opc.h: Regenerate.
944 * m32r-opinst.c: Regenerate.
945 * mep-asm.c: Regenerate.
946 * mep-desc.c: Regenerate.
947 * mep-desc.h: Regenerate.
948 * mep-dis.c: Regenerate.
949 * mep-ibld.c: Regenerate.
950 * mep-opc.c: Regenerate.
951 * mep-opc.h: Regenerate.
952 * mt-asm.c: Regenerate.
953 * mt-desc.c: Regenerate.
954 * mt-desc.h: Regenerate.
955 * mt-dis.c: Regenerate.
956 * mt-ibld.c: Regenerate.
957 * mt-opc.c: Regenerate.
958 * mt-opc.h: Regenerate.
959 * or1k-asm.c: Regenerate.
960 * or1k-desc.c: Regenerate.
961 * or1k-desc.h: Regenerate.
962 * or1k-dis.c: Regenerate.
963 * or1k-ibld.c: Regenerate.
964 * or1k-opc.c: Regenerate.
965 * or1k-opc.h: Regenerate.
966 * or1k-opinst.c: Regenerate.
967 * xc16x-asm.c: Regenerate.
968 * xc16x-desc.c: Regenerate.
969 * xc16x-desc.h: Regenerate.
970 * xc16x-dis.c: Regenerate.
971 * xc16x-ibld.c: Regenerate.
972 * xc16x-opc.c: Regenerate.
973 * xc16x-opc.h: Regenerate.
974 * xstormy16-asm.c: Regenerate.
975 * xstormy16-desc.c: Regenerate.
976 * xstormy16-desc.h: Regenerate.
977 * xstormy16-dis.c: Regenerate.
978 * xstormy16-ibld.c: Regenerate.
979 * xstormy16-opc.c: Regenerate.
980 * xstormy16-opc.h: Regenerate.
982 2017-07-07 Alan Modra <amodra@gmail.com>
984 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
985 * m32c-dis.c: Regenerate.
986 * mep-dis.c: Regenerate.
988 2017-07-05 Borislav Petkov <bp@suse.de>
990 * i386-dis.c: Enable ModRM.reg /6 aliases.
992 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
994 * opcodes/arm-dis.c: Support MVFR2 in disassembly
997 2017-07-04 Tristan Gingold <gingold@adacore.com>
999 * configure: Regenerate.
1001 2017-07-03 Tristan Gingold <gingold@adacore.com>
1003 * po/opcodes.pot: Regenerate.
1005 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
1007 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
1008 entries to the MSA ASE instruction block.
1010 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
1011 Maciej W. Rozycki <macro@imgtec.com>
1013 * micromips-opc.c (XPA, XPAVZ): New macros.
1014 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
1017 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
1018 Maciej W. Rozycki <macro@imgtec.com>
1020 * micromips-opc.c (I36): New macro.
1021 (micromips_opcodes): Add "eretnc".
1023 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
1024 Andrew Bennett <andrew.bennett@imgtec.com>
1026 * mips-dis.c (mips_calculate_combination_ases): Handle the
1028 (parse_mips_ase_option): New function.
1029 (parse_mips_dis_option): Factor out ASE option handling to the
1030 new function. Call `mips_calculate_combination_ases'.
1031 * mips-opc.c (XPAVZ): New macro.
1032 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
1033 "mfhgc0", "mthc0" and "mthgc0".
1035 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
1037 * mips-dis.c (mips_calculate_combination_ases): New function.
1038 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
1039 calculation to the new function.
1040 (set_default_mips_dis_options): Call the new function.
1042 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1044 * arc-dis.c (parse_disassembler_options): Use
1045 FOR_EACH_DISASSEMBLER_OPTION.
1047 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1049 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
1050 disassembler option strings.
1051 (parse_cpu_option): Likewise.
1053 2017-06-28 Tamar Christina <tamar.christina@arm.com>
1055 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
1056 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
1057 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
1058 (aarch64_feature_dotprod, DOT_INSN): New.
1060 * aarch64-dis-2.c: Regenerated.
1062 2017-06-28 Jiong Wang <jiong.wang@arm.com>
1064 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
1066 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
1067 Matthew Fortune <matthew.fortune@imgtec.com>
1068 Andrew Bennett <andrew.bennett@imgtec.com>
1070 * mips-formats.h (INT_BIAS): New macro.
1071 (INT_ADJ): Redefine in INT_BIAS terms.
1072 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
1073 (mips_print_save_restore): New function.
1074 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
1075 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
1077 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
1078 (print_mips16_insn_arg): Call `mips_print_save_restore' for
1079 OP_SAVE_RESTORE_LIST handling, factored out from here.
1080 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
1081 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
1082 (mips_builtin_opcodes): Add "restore" and "save" entries.
1083 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
1085 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
1087 2017-06-23 Andrew Waterman <andrew@sifive.com>
1089 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
1090 alias; do not mark SLTI instruction as an alias.
1092 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1094 * i386-dis.c (RM_0FAE_REG_5): Removed.
1095 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1096 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1097 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1098 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
1099 PREFIX_MOD_3_0F01_REG_5_RM_0.
1100 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
1101 PREFIX_MOD_3_0FAE_REG_5.
1102 (mod_table): Update MOD_0FAE_REG_5.
1103 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
1104 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1105 * i386-tbl.h: Regenerated.
1107 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1109 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1110 * i386-opc.tbl: Likewise.
1111 * i386-tbl.h: Regenerated.
1113 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1115 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1117 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1120 2017-06-19 Nick Clifton <nickc@redhat.com>
1123 * score-dis.c (score_opcodes): Add sentinel.
1125 2017-06-16 Alan Modra <amodra@gmail.com>
1127 * rx-decode.c: Regenerate.
1129 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1132 * i386-dis.c (OP_E_register): Check valid bnd register.
1135 2017-06-15 Nick Clifton <nickc@redhat.com>
1138 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1141 2017-06-15 Nick Clifton <nickc@redhat.com>
1144 * rl78-decode.opc (OP_BUF_LEN): Define.
1145 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1146 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1148 * rl78-decode.c: Regenerate.
1150 2017-06-15 Nick Clifton <nickc@redhat.com>
1153 * bfin-dis.c (gregs): Clip index to prevent overflow.
1155 (regs_lo): Likewise.
1156 (regs_hi): Likewise.
1158 2017-06-14 Nick Clifton <nickc@redhat.com>
1161 * score7-dis.c (score_opcodes): Add sentinel.
1163 2017-06-14 Yao Qi <yao.qi@linaro.org>
1165 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1166 * arm-dis.c: Likewise.
1167 * ia64-dis.c: Likewise.
1168 * mips-dis.c: Likewise.
1169 * spu-dis.c: Likewise.
1170 * disassemble.h (print_insn_aarch64): New declaration, moved from
1172 (print_insn_big_arm, print_insn_big_mips): Likewise.
1173 (print_insn_i386, print_insn_ia64): Likewise.
1174 (print_insn_little_arm, print_insn_little_mips): Likewise.
1176 2017-06-14 Nick Clifton <nickc@redhat.com>
1179 * rx-decode.opc: Include libiberty.h
1180 (GET_SCALE): New macro - validates access to SCALE array.
1181 (GET_PSCALE): New macro - validates access to PSCALE array.
1182 (DIs, SIs, S2Is, rx_disp): Use new macros.
1183 * rx-decode.c: Regenerate.
1185 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1187 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1189 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1191 * arc-dis.c (enforced_isa_mask): Declare.
1192 (cpu_types): Likewise.
1193 (parse_cpu_option): New function.
1194 (parse_disassembler_options): Use it.
1195 (print_insn_arc): Use enforced_isa_mask.
1196 (print_arc_disassembler_options): Document new options.
1198 2017-05-24 Yao Qi <yao.qi@linaro.org>
1200 * alpha-dis.c: Include disassemble.h, don't include
1202 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1203 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1204 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1205 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1206 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1207 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1208 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1209 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1210 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1211 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1212 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1213 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1214 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1215 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1216 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1217 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1218 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1219 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1220 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1221 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1222 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1223 * z80-dis.c, z8k-dis.c: Likewise.
1224 * disassemble.h: New file.
1226 2017-05-24 Yao Qi <yao.qi@linaro.org>
1228 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1229 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1231 2017-05-24 Yao Qi <yao.qi@linaro.org>
1233 * disassemble.c (disassembler): Add arguments a, big and mach.
1236 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1238 * i386-dis.c (NOTRACK_Fixup): New.
1239 (NOTRACK): Likewise.
1240 (NOTRACK_PREFIX): Likewise.
1241 (last_active_prefix): Likewise.
1242 (reg_table): Use NOTRACK on indirect call and jmp.
1243 (ckprefix): Set last_active_prefix.
1244 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1245 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1246 * i386-opc.h (NoTrackPrefixOk): New.
1247 (i386_opcode_modifier): Add notrackprefixok.
1248 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1250 * i386-tbl.h: Regenerated.
1252 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1254 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1256 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1257 bfd_mach_sparc_v9m8.
1258 (print_insn_sparc): Handle new operand types.
1259 * sparc-opc.c (MASK_M8): Define.
1261 (v6notlet): Likewise.
1272 (v9andleon): Likewise.
1275 (HWS2_VM8): Likewise.
1276 (sparc_opcode_archs): Add entry for "m8".
1277 (sparc_opcodes): Add OSA2017 and M8 instructions
1278 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1280 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1281 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1282 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1283 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1284 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1285 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1286 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1287 ASI_CORE_SELECT_COMMIT_NHT.
1289 2017-05-18 Alan Modra <amodra@gmail.com>
1291 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1292 * aarch64-dis.c: Likewise.
1293 * aarch64-gen.c: Likewise.
1294 * aarch64-opc.c: Likewise.
1296 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1297 Matthew Fortune <matthew.fortune@imgtec.com>
1299 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1300 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1301 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1302 (print_insn_arg) <OP_REG28>: Add handler.
1303 (validate_insn_args) <OP_REG28>: Handle.
1304 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1305 32-bit encoding and 9-bit immediates.
1306 (print_insn_mips16): Handle MIPS16 instructions that require
1307 32-bit encoding and MFC0/MTC0 operand decoding.
1308 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1309 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1310 (RD_C0, WR_C0, E2, E2MT): New macros.
1311 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1312 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1313 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1314 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1315 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1316 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1317 instructions, "swl", "swr", "sync" and its "sync_acquire",
1318 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1319 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1320 regular/extended entries for original MIPS16 ISA revision
1321 instructions whose extended forms are subdecoded in the MIPS16e2
1322 ISA revision: "li", "sll" and "srl".
1324 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1326 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1327 reference in CP0 move operand decoding.
1329 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1331 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1332 type to hexadecimal.
1333 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1335 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1337 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1338 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1339 "sync_rmb" and "sync_wmb" as aliases.
1340 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1341 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1343 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1345 * arc-dis.c (parse_option): Update quarkse_em option..
1346 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1348 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1350 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1352 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1354 2017-05-01 Michael Clark <michaeljclark@mac.com>
1356 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1359 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1361 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1362 and branches and not synthetic data instructions.
1364 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1366 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1368 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1370 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1371 * arc-opc.c (insert_r13el): New function.
1373 * arc-tbl.h: Add new enter/leave variants.
1375 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1377 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1379 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1381 * mips-dis.c (print_mips_disassembler_options): Add
1384 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1386 * mips16-opc.c (AL): New macro.
1387 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1388 of "ld" and "lw" as aliases.
1390 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1392 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1395 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1396 Alan Modra <amodra@gmail.com>
1398 * ppc-opc.c (ELEV): Define.
1399 (vle_opcodes): Add se_rfgi and e_sc.
1400 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1403 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1405 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1407 2017-04-21 Nick Clifton <nickc@redhat.com>
1410 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1413 2017-04-13 Alan Modra <amodra@gmail.com>
1415 * epiphany-desc.c: Regenerate.
1416 * fr30-desc.c: Regenerate.
1417 * frv-desc.c: Regenerate.
1418 * ip2k-desc.c: Regenerate.
1419 * iq2000-desc.c: Regenerate.
1420 * lm32-desc.c: Regenerate.
1421 * m32c-desc.c: Regenerate.
1422 * m32r-desc.c: Regenerate.
1423 * mep-desc.c: Regenerate.
1424 * mt-desc.c: Regenerate.
1425 * or1k-desc.c: Regenerate.
1426 * xc16x-desc.c: Regenerate.
1427 * xstormy16-desc.c: Regenerate.
1429 2017-04-11 Alan Modra <amodra@gmail.com>
1431 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1432 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1433 PPC_OPCODE_TMR for e6500.
1434 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1435 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1436 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1437 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1438 (PPCHTM): Define as PPC_OPCODE_POWER8.
1439 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1441 2017-04-10 Alan Modra <amodra@gmail.com>
1443 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1444 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1445 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1446 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1448 2017-04-09 Pip Cet <pipcet@gmail.com>
1450 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1451 appropriate floating-point precision directly.
1453 2017-04-07 Alan Modra <amodra@gmail.com>
1455 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1456 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1457 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1458 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1459 vector instructions with E6500 not PPCVEC2.
1461 2017-04-06 Pip Cet <pipcet@gmail.com>
1463 * Makefile.am: Add wasm32-dis.c.
1464 * configure.ac: Add wasm32-dis.c to wasm32 target.
1465 * disassemble.c: Add wasm32 disassembler code.
1466 * wasm32-dis.c: New file.
1467 * Makefile.in: Regenerate.
1468 * configure: Regenerate.
1469 * po/POTFILES.in: Regenerate.
1470 * po/opcodes.pot: Regenerate.
1472 2017-04-05 Pedro Alves <palves@redhat.com>
1474 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1475 * arm-dis.c (parse_arm_disassembler_options): Constify.
1476 * ppc-dis.c (powerpc_init_dialect): Constify local.
1477 * vax-dis.c (parse_disassembler_options): Constify.
1479 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1481 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1484 2017-03-30 Pip Cet <pipcet@gmail.com>
1486 * configure.ac: Add (empty) bfd_wasm32_arch target.
1487 * configure: Regenerate
1488 * po/opcodes.pot: Regenerate.
1490 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1492 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1494 * opcodes/sparc-opc.c (asi_table): New ASIs.
1496 2017-03-29 Alan Modra <amodra@gmail.com>
1498 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1500 (lookup_powerpc): Don't special case -1 dialect. Handle
1502 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1503 lookup_powerpc call, pass it on second.
1505 2017-03-27 Alan Modra <amodra@gmail.com>
1508 * ppc-dis.c (struct ppc_mopt): Comment.
1509 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1511 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1513 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1514 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1515 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1516 (insert_nps_misc_imm_offset): New function.
1517 (extract_nps_misc imm_offset): New function.
1518 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1519 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1521 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1523 * s390-mkopc.c (main): Remove vx2 check.
1524 * s390-opc.txt: Remove vx2 instruction flags.
1526 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1528 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1529 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1530 (insert_nps_imm_offset): New function.
1531 (extract_nps_imm_offset): New function.
1532 (insert_nps_imm_entry): New function.
1533 (extract_nps_imm_entry): New function.
1535 2017-03-17 Alan Modra <amodra@gmail.com>
1538 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1539 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1540 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1542 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1544 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1548 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1550 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1552 2017-03-13 Andrew Waterman <andrew@sifive.com>
1554 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1559 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1561 * i386-gen.c (opcode_modifiers): Replace S with Load.
1562 * i386-opc.h (S): Removed.
1564 (i386_opcode_modifier): Replace s with load.
1565 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1566 and {evex}. Replace S with Load.
1567 * i386-tbl.h: Regenerated.
1569 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1571 * i386-opc.tbl: Use CpuCET on rdsspq.
1572 * i386-tbl.h: Regenerated.
1574 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1576 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1577 <vsx>: Do not use PPC_OPCODE_VSX3;
1579 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1581 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1583 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1585 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1586 (MOD_0F1E_PREFIX_1): Likewise.
1587 (MOD_0F38F5_PREFIX_2): Likewise.
1588 (MOD_0F38F6_PREFIX_0): Likewise.
1589 (RM_0F1E_MOD_3_REG_7): Likewise.
1590 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1591 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1592 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1593 (PREFIX_0F1E): Likewise.
1594 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1595 (PREFIX_0F38F5): Likewise.
1596 (dis386_twobyte): Use PREFIX_0F1E.
1597 (reg_table): Add REG_0F1E_MOD_3.
1598 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1599 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1600 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1601 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1602 (three_byte_table): Use PREFIX_0F38F5.
1603 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1604 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1605 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1606 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1607 PREFIX_MOD_3_0F01_REG_5_RM_2.
1608 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1609 (cpu_flags): Add CpuCET.
1610 * i386-opc.h (CpuCET): New enum.
1611 (CpuUnused): Commented out.
1612 (i386_cpu_flags): Add cpucet.
1613 * i386-opc.tbl: Add Intel CET instructions.
1614 * i386-init.h: Regenerated.
1615 * i386-tbl.h: Likewise.
1617 2017-03-06 Alan Modra <amodra@gmail.com>
1620 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1621 (extract_raq, extract_ras, extract_rbx): New functions.
1622 (powerpc_operands): Use opposite corresponding insert function.
1624 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1625 register restriction.
1627 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1629 * disassemble.c Include "safe-ctype.h".
1630 (disassemble_init_for_target): Handle s390 init.
1631 (remove_whitespace_and_extra_commas): New function.
1632 (disassembler_options_cmp): Likewise.
1633 * arm-dis.c: Include "libiberty.h".
1635 (regnames): Use long disassembler style names.
1636 Add force-thumb and no-force-thumb options.
1637 (NUM_ARM_REGNAMES): Rename from this...
1638 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1639 (get_arm_regname_num_options): Delete.
1640 (set_arm_regname_option): Likewise.
1641 (get_arm_regnames): Likewise.
1642 (parse_disassembler_options): Likewise.
1643 (parse_arm_disassembler_option): Rename from this...
1644 (parse_arm_disassembler_options): ...to this. Make static.
1645 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1646 (print_insn): Use parse_arm_disassembler_options.
1647 (disassembler_options_arm): New function.
1648 (print_arm_disassembler_options): Handle updated regnames.
1649 * ppc-dis.c: Include "libiberty.h".
1650 (ppc_opts): Add "32" and "64" entries.
1651 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1652 (powerpc_init_dialect): Add break to switch statement.
1653 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1654 (disassembler_options_powerpc): New function.
1655 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1656 Remove printing of "32" and "64".
1657 * s390-dis.c: Include "libiberty.h".
1658 (init_flag): Remove unneeded variable.
1659 (struct s390_options_t): New structure type.
1660 (options): New structure.
1661 (init_disasm): Rename from this...
1662 (disassemble_init_s390): ...to this. Add initializations for
1663 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1664 (print_insn_s390): Delete call to init_disasm.
1665 (disassembler_options_s390): New function.
1666 (print_s390_disassembler_options): Print using information from
1668 * po/opcodes.pot: Regenerate.
1670 2017-02-28 Jan Beulich <jbeulich@suse.com>
1672 * i386-dis.c (PCMPESTR_Fixup): New.
1673 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1674 (prefix_table): Use PCMPESTR_Fixup.
1675 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1677 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1678 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1679 Split 64-bit and non-64-bit variants.
1680 * opcodes/i386-tbl.h: Re-generate.
1682 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1684 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1685 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1686 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1687 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1688 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1689 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1690 (OP_SVE_V_HSD): New macros.
1691 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1692 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1693 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1694 (aarch64_opcode_table): Add new SVE instructions.
1695 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1696 for rotation operands. Add new SVE operands.
1697 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1698 (ins_sve_quad_index): Likewise.
1699 (ins_imm_rotate): Split into...
1700 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1701 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1702 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1704 (aarch64_ins_sve_addr_ri_s4): New function.
1705 (aarch64_ins_sve_quad_index): Likewise.
1706 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1707 * aarch64-asm-2.c: Regenerate.
1708 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1709 (ext_sve_quad_index): Likewise.
1710 (ext_imm_rotate): Split into...
1711 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1712 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1713 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1715 (aarch64_ext_sve_addr_ri_s4): New function.
1716 (aarch64_ext_sve_quad_index): Likewise.
1717 (aarch64_ext_sve_index): Allow quad indices.
1718 (do_misc_decoding): Likewise.
1719 * aarch64-dis-2.c: Regenerate.
1720 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1721 aarch64_field_kinds.
1722 (OPD_F_OD_MASK): Widen by one bit.
1723 (OPD_F_NO_ZR): Bump accordingly.
1724 (get_operand_field_width): New function.
1725 * aarch64-opc.c (fields): Add new SVE fields.
1726 (operand_general_constraint_met_p): Handle new SVE operands.
1727 (aarch64_print_operand): Likewise.
1728 * aarch64-opc-2.c: Regenerate.
1730 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1732 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1733 (aarch64_feature_compnum): ...this.
1734 (SIMD_V8_3): Replace with...
1736 (CNUM_INSN): New macro.
1737 (aarch64_opcode_table): Use it for the complex number instructions.
1739 2017-02-24 Jan Beulich <jbeulich@suse.com>
1741 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1743 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1745 Add support for associating SPARC ASIs with an architecture level.
1746 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1747 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1748 decoding of SPARC ASIs.
1750 2017-02-23 Jan Beulich <jbeulich@suse.com>
1752 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1753 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1755 2017-02-21 Jan Beulich <jbeulich@suse.com>
1757 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1758 1 (instead of to itself). Correct typo.
1760 2017-02-14 Andrew Waterman <andrew@sifive.com>
1762 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1765 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1767 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1768 (aarch64_sys_reg_supported_p): Handle them.
1770 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1772 * arc-opc.c (UIMM6_20R): Define.
1773 (SIMM12_20): Use above.
1774 (SIMM12_20R): Define.
1775 (SIMM3_5_S): Use above.
1776 (UIMM7_A32_11R_S): Define.
1777 (UIMM7_9_S): Use above.
1778 (UIMM3_13R_S): Define.
1779 (SIMM11_A32_7_S): Use above.
1781 (UIMM10_A32_8_S): Use above.
1782 (UIMM8_8R_S): Define.
1784 (arc_relax_opcodes): Use all above defines.
1786 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1788 * arc-regs.h: Distinguish some of the registers different on
1789 ARC700 and HS38 cpus.
1791 2017-02-14 Alan Modra <amodra@gmail.com>
1794 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1795 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1797 2017-02-11 Stafford Horne <shorne@gmail.com>
1798 Alan Modra <amodra@gmail.com>
1800 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1801 Use insn_bytes_value and insn_int_value directly instead. Don't
1802 free allocated memory until function exit.
1804 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1806 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1808 2017-02-03 Nick Clifton <nickc@redhat.com>
1811 * aarch64-opc.c (print_register_list): Ensure that the register
1812 list index will fir into the tb buffer.
1813 (print_register_offset_address): Likewise.
1814 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1816 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1819 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1820 instructions when the previous fetch packet ends with a 32-bit
1823 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1825 * pru-opc.c: Remove vague reference to a future GDB port.
1827 2017-01-20 Nick Clifton <nickc@redhat.com>
1829 * po/ga.po: Updated Irish translation.
1831 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1833 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1835 2017-01-13 Yao Qi <yao.qi@linaro.org>
1837 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1838 if FETCH_DATA returns 0.
1839 (m68k_scan_mask): Likewise.
1840 (print_insn_m68k): Update code to handle -1 return value.
1842 2017-01-13 Yao Qi <yao.qi@linaro.org>
1844 * m68k-dis.c (enum print_insn_arg_error): New.
1845 (NEXTBYTE): Replace -3 with
1846 PRINT_INSN_ARG_MEMORY_ERROR.
1847 (NEXTULONG): Likewise.
1848 (NEXTSINGLE): Likewise.
1849 (NEXTDOUBLE): Likewise.
1850 (NEXTDOUBLE): Likewise.
1851 (NEXTPACKED): Likewise.
1852 (FETCH_ARG): Likewise.
1853 (FETCH_DATA): Update comments.
1854 (print_insn_arg): Update comments. Replace magic numbers with
1856 (match_insn_m68k): Likewise.
1858 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1860 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1861 * i386-dis-evex.h (evex_table): Updated.
1862 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1863 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1864 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1865 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1866 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1867 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1868 * i386-init.h: Regenerate.
1869 * i386-tbl.h: Ditto.
1871 2017-01-12 Yao Qi <yao.qi@linaro.org>
1873 * msp430-dis.c (msp430_singleoperand): Return -1 if
1874 msp430dis_opcode_signed returns false.
1875 (msp430_doubleoperand): Likewise.
1876 (msp430_branchinstr): Return -1 if
1877 msp430dis_opcode_unsigned returns false.
1878 (msp430x_calla_instr): Likewise.
1879 (print_insn_msp430): Likewise.
1881 2017-01-05 Nick Clifton <nickc@redhat.com>
1884 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1885 could not be matched.
1886 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1889 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1891 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1892 (aarch64_opcode_table): Use RCPC_INSN.
1894 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1896 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1898 * riscv-opcodes/all-opcodes: Likewise.
1900 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1902 * riscv-dis.c (print_insn_args): Add fall through comment.
1904 2017-01-03 Nick Clifton <nickc@redhat.com>
1906 * po/sr.po: New Serbian translation.
1907 * configure.ac (ALL_LINGUAS): Add sr.
1908 * configure: Regenerate.
1910 2017-01-02 Alan Modra <amodra@gmail.com>
1912 * epiphany-desc.h: Regenerate.
1913 * epiphany-opc.h: Regenerate.
1914 * fr30-desc.h: Regenerate.
1915 * fr30-opc.h: Regenerate.
1916 * frv-desc.h: Regenerate.
1917 * frv-opc.h: Regenerate.
1918 * ip2k-desc.h: Regenerate.
1919 * ip2k-opc.h: Regenerate.
1920 * iq2000-desc.h: Regenerate.
1921 * iq2000-opc.h: Regenerate.
1922 * lm32-desc.h: Regenerate.
1923 * lm32-opc.h: Regenerate.
1924 * m32c-desc.h: Regenerate.
1925 * m32c-opc.h: Regenerate.
1926 * m32r-desc.h: Regenerate.
1927 * m32r-opc.h: Regenerate.
1928 * mep-desc.h: Regenerate.
1929 * mep-opc.h: Regenerate.
1930 * mt-desc.h: Regenerate.
1931 * mt-opc.h: Regenerate.
1932 * or1k-desc.h: Regenerate.
1933 * or1k-opc.h: Regenerate.
1934 * xc16x-desc.h: Regenerate.
1935 * xc16x-opc.h: Regenerate.
1936 * xstormy16-desc.h: Regenerate.
1937 * xstormy16-opc.h: Regenerate.
1939 2017-01-02 Alan Modra <amodra@gmail.com>
1941 Update year range in copyright notice of all files.
1943 For older changes see ChangeLog-2016
1945 Copyright (C) 2017 Free Software Foundation, Inc.
1947 Copying and distribution of this file, with or without modification,
1948 are permitted in any medium without royalty provided the copyright
1949 notice and this notice are preserved.
1955 version-control: never