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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2017-12-19 Tamar Christina <tamar.christina@arm.com>
2
3 PR gas/22559
4 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
5 AARCH64_OPND_QLF_S_4B
6 * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
7 AARCH64_OPND_QLF_S_4B
8 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
9 * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
10
11 2017-12-19 Tamar Christina <tamar.christina@arm.com>
12
13 PR gas/22529
14 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
15
16 2017-12-18 Jan Beulich <jbeulich@suse.com>
17
18 * i386-gen.c (operand_type_init): Delete OPERAND_TYPE_REGYMM and
19 OPERAND_TYPE_REGZMM entries.
20 * i386-opc.h (enum of opcode modifiers): Extend comment.
21 i386-opc.tbl (vaddpd, vaddps, vaddsubpd, vaddsubps, vandnpd,
22 vandnps, vandpd, vandps, vblendpd, vblendps, vblendvpd,
23 vblendvps, vbroadcastss, vcmpeq_ospd, vcmpeq_osps, vcmpeqpd,
24 vcmpeqps, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uspd, vcmpeq_usps,
25 vcmpfalse_ospd, vcmpfalse_osps, vcmpfalsepd, vcmpfalseps,
26 vcmpge_oqpd, vcmpge_oqps, vcmpgepd, vcmpgeps, vcmpgt_oqpd,
27 vcmpgt_oqps, vcmpgtpd, vcmpgtps, vcmple_oqpd, vcmple_oqps,
28 vcmplepd, vcmpleps, vcmplt_oqpd, vcmplt_oqps, vcmpltpd,
29 vcmpltps, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_ospd,
30 vcmpneq_osps, vcmpneqpd, vcmpneqps, vcmpneq_uspd, vcmpneq_usps,
31 vcmpngepd, vcmpngeps, vcmpnge_uqpd, vcmpnge_uqps, vcmpngtpd,
32 vcmpngtps, vcmpngt_uqpd, vcmpngt_uqps, vcmpnlepd, vcmpnleps,
33 vcmpnle_uqpd, vcmpnle_uqps, vcmpnltpd, vcmpnltps, vcmpnlt_uqpd,
34 vcmpnlt_uqps, vcmpordpd, vcmpordps, vcmpord_spd, vcmpord_sps,
35 vcmppd, vcmpps, vcmptruepd, vcmptrueps, vcmptrue_uspd,
36 vcmptrue_usps, vcmpunordpd, vcmpunordps, vcmpunord_spd,
37 vcmpunord_sps, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps, vcvtps2dq,
38 vcvttpd2dq, vcvttps2dq, vdivpd, vdivps, vdpps, vhaddpd, vhaddps,
39 vhsubpd, vhsubps, vlddqu, vmaskmovpd, vmaskmovps, vmaxpd,
40 vmaxps, vminpd, vminps, vmovapd, vmovaps, vmovdqa, vmovdqu,
41 vmovmskpd, vmovmskps, vmovntdq, vmovntpd, vmovntps, vmovshdup,
42 vmovsldup, vmovupd, vmovups, vmulpd, vmulps, vorpd, vorps,
43 vpermilpd, vpermilps, vptest, vrcpps, vroundpd, vroundps,
44 vrsqrtps, vshufpd, vshufps, vsqrtpd, vsqrtps, vsubpd, vsubps,
45 vtestpd, vtestps, vunpckhpd, vunpckhps, vunpcklpd, vunpcklps,
46 vxorpd, vxorps, vpblendd, vpbroadcastb, vpbroadcastd,
47 vpbroadcastw, vpbroadcastq, vpmaskmovd, vpmaskmovq, vpsllvd,
48 vpsllvq, vpsravd, vpsravq, vpsrlvd, vpsrlvq): Fold 128- and
49 256-bit forms. Use CheckRegSize instead of IgnoreSize where
50 appropriate. Drop Xmmword and Ymmword from the results where
51 possible.
52 * i386-tbl.h: Re-generate.
53
54 2017-12-18 Jan Beulich <jbeulich@suse.com>
55
56 * i386-gen.c (operand_type_shorthands): Add RegXMM, RegYMM, and
57 RegZMM.
58 (opcode_modifiers): Drop FirstXmm0.
59 (operand_types): Replace RegXMM, RegYMM, and RegZMM with just
60 RegSIMD.
61 * i386-opc.h (enum of opcode modifiers): Drop FirstXmm0.
62 (struct i386_opcode_modifier): Drop firstxmm0.
63 (enum of operand types): Replace RegXMM, RegYMM, and RegZMM with
64 just RegSIMD. Extend comment.
65 (union i386_operand_type): Replace regxmm, regymm, and regzmm
66 with just regsimd.
67 * i386-opc.tbl (blendvpd, blendvps, pblendvb, sha256rnds2): Use
68 Acc|Xmmword.
69 * i386-reg.tbl (xmm0): Add Acc.
70 * i386-init.h, i386-tbl.h: Re-generate.
71
72 2017-12-18 Jan Beulich <jbeulich@suse.com>
73
74 * i386-gen.c (operand_type_shorthands): Add FloatAcc and
75 FloatReg.
76 (operand_types): Drop FloatAcc and FloatReg.
77 * i386-opc.h (enum of operand types): Likewise. Extend comment.
78 (union i386_operand_type): Drop floatacc and floatreg.
79 * i386-reg.tbl (st, st(0)): Replace FloatAcc by Acc.
80 * i386-init.h, i386-tbl.h: Re-generate.
81
82 2017-12-18 Jan Beulich <jbeulich@suse.com>
83
84 * i386-gen.c (operand_type_shorthands): New.
85 (opcode_modifiers): Replace Reg<N> with just Reg.
86 (set_bitfield_from_cpu_flag_init): Rename to
87 set_bitfield_from_shorthand. Drop value parameter. Process
88 operand_type_shorthands.
89 (set_bitfield): Adjust call accordingly.
90 * i386-opc.h (enum of operand types): Replace Reg<N> with just
91 Reg.
92 (union i386_operand_type): Replace reg<N> with just reg.
93 * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
94 vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
95 separate register and memory forms.
96 * i386-reg.tbl (al): Drop Byte.
97 (ax): Drop Word.
98 (eax): Drop Dword.
99 (rax): Drop Qword.
100 * i386-init.h, i386-tbl.h: Re-generate.
101
102 2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
103
104 * disassemble.c (disassemble_init_for_target): Don't put PRU
105 between powerpc and rs6000 cases.
106
107 2017-12-15 Jan Beulich <jbeulich@suse.com>
108
109 * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
110 movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
111 sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
112 stos, sub, test, xor): Drop CheckRegSize from variants not
113 allowing for two (or more) register operands.
114 * i386-tbl.h: Re-generate.
115
116 2017-12-13 Jim Wilson <jimw@sifive.com>
117
118 PR 22599
119 * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
120
121 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
122
123 * disassemble.c: Enable disassembler_needs_relocs for PRU.
124
125 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
126 Renlin Li <renlin.li@arm.com>
127
128 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
129 (get_sym_code_type): Here.
130
131 2017-12-03 Alan Modra <amodra@gmail.com>
132
133 * ppc-opc.c (extract_li20): Rewrite.
134
135 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
136
137 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
138 (operand_value_powerpc): Update return and argument type.
139 <value, top>: Update type.
140 (skip_optional_operands): Update argument type.
141 (lookup_powerpc): Likewise.
142 (lookup_vle): Likewise.
143 <table_opcd, table_mask, insn2>: Update type.
144 (lookup_spe2): Update argument type.
145 <table_opcd, table_mask, insn2>: Update type.
146 (print_insn_powerpc) <insn, value>: Update type.
147 Use PPC_INT_FMT for printing instructions and operands.
148 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
149 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
150 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
151 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
152 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
153 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
154 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
155 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
156 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
157 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
158 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
159 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
160 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
161 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
162 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
163 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
164 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
165 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
166 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
167 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
168 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
169 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
170 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
171 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
172 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
173 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
174 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
175 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
176 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
177 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
178 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
179 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
180 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
181 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
182 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
183 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
184 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
185
186 2017-11-29 Jan Beulich <jbeulich@suse.com>
187
188 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
189 New.
190 (output_cpu_flags): Update active_cpu_flags.
191 (process_i386_opcode_modifier): Update active_isstring.
192 (output_operand_type): Rename "macro" parameter to "stage",
193 changing its type.
194 (process_i386_operand_type): Likewise. Track presence of
195 BaseIndex and emit DispN accordingly.
196 (output_i386_opcode, process_i386_registers,
197 process_i386_initializers): Adjust calls to
198 process_i386_operand_type() for its changed parameter type.
199 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
200 all insns operands having BaseIndex set.
201 * i386-tbl.h: Re-generate.
202
203 2017-11-29 Jan Beulich <jbeulich@suse.com>
204
205 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
206 entry.
207 (operand_types): Remove Vec_Disp8 entry.
208 * i386-opc.h (Vec_Disp8): Delete.
209 (union i386_operand_type): Remove vec_disp8.
210 (i386-opc.tbl): Remove Vec_Disp8.
211 * i386-init.h, i386-tbl.h: Re-generate.
212
213 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
214
215 * po/Make-in (datadir): Define as @datadir@.
216 (localedir): Define as @localedir@.
217 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
218
219 2017-11-27 Nick Clifton <nickc@redhat.com>
220
221 * po/zh_CN.po: Updated simplified Chinese translation.
222
223 2017-11-24 Jan Beulich <jbeulich@suse.com>
224
225 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
226 "df" groups.
227
228 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
229
230 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
231 * i386-tbl.h: Regenerate.
232
233 2017-11-23 Jan Beulich <jbeulich@suse.com>
234
235 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
236 the 16-bit addressing case.
237
238 2017-11-23 Jan Beulich <jbeulich@suse.com>
239
240 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
241 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
242 * i386-opc.tbl (ud1, ud2b): Add operands.
243 (ud0): New.
244 * i386-tbl.h: Re-generate.
245
246 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
247
248 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
249 * i386-tbl.h: Regenerate.
250
251 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
252
253 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
254 * i386-tbl.h: Regenerate.
255
256 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
257
258 *arc-opc (insert_rhv2): Check h-regs range.
259
260 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
261
262 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
263 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
264
265 2017-11-16 Tamar Christina <tamar.christina@arm.com>
266
267 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
268 and AARCH64_FEATURE_F16.
269
270 2017-11-16 Tamar Christina <tamar.christina@arm.com>
271
272 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
273 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
274 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
275 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
276 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
277 (ldapur, ldapursw, stlur): New.
278 * aarch64-dis-2.c: Regenerate.
279
280 2017-11-16 Jan Beulich <jbeulich@suse.com>
281
282 (get_valid_dis386): Never flag bad opcode when
283 vex.register_specifier is beyond 7. Always store all four
284 bits of it. Move 16-/32-bit override in EVEX handling after
285 all to be overridden bits have been set.
286 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
287 Use rex to determine GPR register set.
288 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
289 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
290
291 2017-11-15 Jan Beulich <jbeulich@suse.com>
292
293 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
294 determine GPR register set.
295
296 2017-11-15 Jan Beulich <jbeulich@suse.com>
297
298 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
299 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
300 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
301 pass.
302 (OP_REG_VexI4): Drop low 4 bits check.
303
304 2017-11-15 Jan Beulich <jbeulich@suse.com>
305
306 * i386-reg.tbl (axl): Remove Acc and Byte.
307 * i386-tbl.h: Re-generate.
308
309 2017-11-14 Jan Beulich <jbeulich@suse.com>
310
311 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
312 (vex_len_table): Use VPCOM.
313
314 2017-11-14 Jan Beulich <jbeulich@suse.com>
315
316 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
317 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
318 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
319 vpcmpw): Move up.
320 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
321 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
322 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
323 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
324 vpcmpnltuw): New.
325 * i386-tbl.h: Re-generate.
326
327 2017-11-14 Jan Beulich <jbeulich@suse.com>
328
329 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
330 smov, ssca, stos, ssto, xlat): Drop Disp*.
331 * i386-tbl.h: Re-generate.
332
333 2017-11-13 Jan Beulich <jbeulich@suse.com>
334
335 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
336 xsaveopt64): Add No_qSuf.
337 * i386-tbl.h: Re-generate.
338
339 2017-11-09 Tamar Christina <tamar.christina@arm.com>
340
341 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
342 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
343 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
344 sder32_el2, vncr_el2.
345 (aarch64_sys_reg_supported_p): Likewise.
346 (aarch64_pstatefields): Add dit register.
347 (aarch64_pstatefield_supported_p): Likewise.
348 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
349 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
350 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
351 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
352 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
353 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
354 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
355
356 2017-11-09 Tamar Christina <tamar.christina@arm.com>
357
358 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
359 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
360 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
361 (QL_STLW, QL_STLX): New.
362
363 2017-11-09 Tamar Christina <tamar.christina@arm.com>
364
365 * aarch64-asm.h (ins_addr_offset): New.
366 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
367 (aarch64_ins_addr_offset): New.
368 * aarch64-asm-2.c: Regenerate.
369 * aarch64-dis.h (ext_addr_offset): New.
370 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
371 (aarch64_ext_addr_offset): New.
372 * aarch64-dis-2.c: Regenerate.
373 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
374 FLD_imm4_2 and FLD_SM3_imm2.
375 * aarch64-opc.c (fields): Add FLD_imm6_2,
376 FLD_imm4_2 and FLD_SM3_imm2.
377 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
378 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
379 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
380 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
381 * aarch64-tbl.h
382 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
383
384 2017-11-09 Tamar Christina <tamar.christina@arm.com>
385
386 * aarch64-tbl.h
387 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
388 (aarch64_feature_sm4, aarch64_feature_sha3): New.
389 (aarch64_feature_fp_16_v8_2): New.
390 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
391 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
392 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
393
394 2017-11-08 Tamar Christina <tamar.christina@arm.com>
395
396 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
397 (aarch64_feature_sha2, aarch64_feature_aes): New.
398 (SHA2, AES): New.
399 (AES_INSN, SHA2_INSN): New.
400 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
401 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
402 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
403 Change to SHA2_INS.
404
405 2017-11-08 Jiong Wang <jiong.wang@arm.com>
406 Tamar Christina <tamar.christina@arm.com>
407
408 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
409 FP16 instructions, including vfmal.f16 and vfmsl.f16.
410
411 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
412
413 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
414
415 2017-11-07 Alan Modra <amodra@gmail.com>
416
417 * opintl.h: Formatting, comment fixes.
418 (gettext, ngettext): Redefine when ENABLE_NLS.
419 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
420 (_): Define using gettext.
421 (textdomain, bindtextdomain): Use safer "do nothing".
422
423 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
424
425 * arc-dis.c (print_hex): New variable.
426 (parse_option): Check for hex option.
427 (print_insn_arc): Use hexadecimal representation for short
428 immediate values when requested.
429 (print_arc_disassembler_options): Add hex option to the list.
430
431 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
432
433 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
434 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
435 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
436 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
437 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
438 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
439 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
440 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
441 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
442 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
443 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
444 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
445 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
446 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
447 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
448 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
449 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
450 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
451 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
452 Changed opcodes.
453 (prealloc, prefetch*): Place them before ld instruction.
454 * arc-opc.c (skip_this_opcode): Add ARITH class.
455
456 2017-10-25 Alan Modra <amodra@gmail.com>
457
458 PR 22348
459 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
460 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
461 (imm4flag, size_changed): Likewise.
462 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
463 (words, allWords, processing_argument_number): Likewise.
464 (cst4flag, size_changed): Likewise.
465 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
466 (crx_cst4_maps): Rename from cst4_maps.
467 (crx_no_op_insn): Rename from no_op_insn.
468
469 2017-10-24 Andrew Waterman <andrew@sifive.com>
470
471 * riscv-opc.c (match_c_addi16sp) : New function.
472 (match_c_addi4spn): New function.
473 (match_c_lui): Don't allow 0-immediate encodings.
474 (riscv_opcodes) <addi>: Use the above functions.
475 <add>: Likewise.
476 <c.addi4spn>: Likewise.
477 <c.addi16sp>: Likewise.
478
479 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
480
481 * i386-init.h: Regenerate
482 * i386-tbl.h: Likewise
483
484 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
485
486 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
487 (enum): Add EVEX_W_0F3854_P_2.
488 * i386-dis-evex.h (evex_table): Updated.
489 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
490 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
491 (cpu_flags): Add CpuAVX512_BITALG.
492 * i386-opc.h (enum): Add CpuAVX512_BITALG.
493 (i386_cpu_flags): Add cpuavx512_bitalg..
494 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
495 * i386-init.h: Regenerate.
496 * i386-tbl.h: Likewise.
497
498 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
499
500 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
501 * i386-dis-evex.h (evex_table): Updated.
502 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
503 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
504 (cpu_flags): Add CpuAVX512_VNNI.
505 * i386-opc.h (enum): Add CpuAVX512_VNNI.
506 (i386_cpu_flags): Add cpuavx512_vnni.
507 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
508 * i386-init.h: Regenerate.
509 * i386-tbl.h: Likewise.
510
511 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
512
513 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
514 (enum): Remove VEX_LEN_0F3A44_P_2.
515 (vex_len_table): Ditto.
516 (enum): Remove VEX_W_0F3A44_P_2.
517 (vew_w_table): Ditto.
518 (prefix_table): Adjust instructions (see prefixes above).
519 * i386-dis-evex.h (evex_table):
520 Add new instructions (see prefixes above).
521 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
522 (bitfield_cpu_flags): Ditto.
523 * i386-opc.h (enum): Ditto.
524 (i386_cpu_flags): Ditto.
525 (CpuUnused): Comment out to avoid zero-width field problem.
526 * i386-opc.tbl (vpclmulqdq): New instruction.
527 * i386-init.h: Regenerate.
528 * i386-tbl.h: Ditto.
529
530 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
531
532 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
533 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
534 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
535 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
536 (vex_len_table): Ditto.
537 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
538 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
539 (vew_w_table): Ditto.
540 (prefix_table): Adjust instructions (see prefixes above).
541 * i386-dis-evex.h (evex_table):
542 Add new instructions (see prefixes above).
543 * i386-gen.c (cpu_flag_init): Add VAES.
544 (bitfield_cpu_flags): Ditto.
545 * i386-opc.h (enum): Ditto.
546 (i386_cpu_flags): Ditto.
547 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
548 * i386-init.h: Regenerate.
549 * i386-tbl.h: Ditto.
550
551 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
552
553 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
554 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
555 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
556 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
557 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
558 (prefix_table): Updated (see prefixes above).
559 (three_byte_table): Likewise.
560 (vex_w_table): Likewise.
561 * i386-dis-evex.h: Likewise.
562 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
563 (cpu_flags): Add CpuGFNI.
564 * i386-opc.h (enum): Add CpuGFNI.
565 (i386_cpu_flags): Add cpugfni.
566 * i386-opc.tbl: Add Intel GFNI instructions.
567 * i386-init.h: Regenerate.
568 * i386-tbl.h: Likewise.
569
570 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
571
572 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
573 Define EXbScalar and EXwScalar for OP_EX.
574 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
575 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
576 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
577 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
578 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
579 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
580 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
581 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
582 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
583 (OP_E_memory): Likewise.
584 * i386-dis-evex.h: Updated.
585 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
586 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
587 (cpu_flags): Add CpuAVX512_VBMI2.
588 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
589 (i386_cpu_flags): Add cpuavx512_vbmi2.
590 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
591 * i386-init.h: Regenerate.
592 * i386-tbl.h: Likewise.
593
594 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
595
596 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
597
598 2017-10-12 James Bowman <james.bowman@ftdichip.com>
599
600 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
601 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
602 K15. Add jmpix pattern.
603
604 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
605
606 * s390-opc.txt (prno, tpei, irbm): New instructions added.
607
608 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
609
610 * s390-opc.c (INSTR_SI_RD): New macro.
611 (INSTR_S_RD): Adjust example instruction.
612 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
613 SI_RD.
614
615 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
616
617 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
618 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
619 VLE multimple load/store instructions. Old e_ldm* variants are
620 kept as aliases.
621 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
622
623 2017-09-27 Nick Clifton <nickc@redhat.com>
624
625 PR 22179
626 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
627 names for the fmv.x.s and fmv.s.x instructions respectively.
628
629 2017-09-26 do <do@nerilex.org>
630
631 PR 22123
632 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
633 be used on CPUs that have emacs support.
634
635 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
636
637 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
638
639 2017-09-09 Kamil Rytarowski <n54@gmx.com>
640
641 * nds32-asm.c: Rename __BIT() to N32_BIT().
642 * nds32-asm.h: Likewise.
643 * nds32-dis.c: Likewise.
644
645 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
646
647 * i386-dis.c (last_active_prefix): Removed.
648 (ckprefix): Don't set last_active_prefix.
649 (NOTRACK_Fixup): Don't check last_active_prefix.
650
651 2017-08-31 Nick Clifton <nickc@redhat.com>
652
653 * po/fr.po: Updated French translation.
654
655 2017-08-31 James Bowman <james.bowman@ftdichip.com>
656
657 * ft32-dis.c (print_insn_ft32): Correct display of non-address
658 fields.
659
660 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
661 Edmar Wienskoski <edmar.wienskoski@nxp.com>
662
663 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
664 PPC_OPCODE_EFS2 flag to "e200z4" entry.
665 New entries efs2 and spe2.
666 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
667 (SPE2_OPCD_SEGS): New macro.
668 (spe2_opcd_indices): New.
669 (disassemble_init_powerpc): Handle SPE2 opcodes.
670 (lookup_spe2): New function.
671 (print_insn_powerpc): call lookup_spe2.
672 * ppc-opc.c (insert_evuimm1_ex0): New function.
673 (extract_evuimm1_ex0): Likewise.
674 (insert_evuimm_lt8): Likewise.
675 (extract_evuimm_lt8): Likewise.
676 (insert_off_spe2): Likewise.
677 (extract_off_spe2): Likewise.
678 (insert_Ddd): Likewise.
679 (extract_Ddd): Likewise.
680 (DD): New operand.
681 (EVUIMM_LT8): Likewise.
682 (EVUIMM_LT16): Adjust.
683 (MMMM): New operand.
684 (EVUIMM_1): Likewise.
685 (EVUIMM_1_EX0): Likewise.
686 (EVUIMM_2): Adjust.
687 (NNN): New operand.
688 (VX_OFF_SPE2): Likewise.
689 (BBB): Likewise.
690 (DDD): Likewise.
691 (VX_MASK_DDD): New mask.
692 (HH): New operand.
693 (VX_RA_CONST): New macro.
694 (VX_RA_CONST_MASK): Likewise.
695 (VX_RB_CONST): Likewise.
696 (VX_RB_CONST_MASK): Likewise.
697 (VX_OFF_SPE2_MASK): Likewise.
698 (VX_SPE_CRFD): Likewise.
699 (VX_SPE_CRFD_MASK VX): Likewise.
700 (VX_SPE2_CLR): Likewise.
701 (VX_SPE2_CLR_MASK): Likewise.
702 (VX_SPE2_SPLATB): Likewise.
703 (VX_SPE2_SPLATB_MASK): Likewise.
704 (VX_SPE2_OCTET): Likewise.
705 (VX_SPE2_OCTET_MASK): Likewise.
706 (VX_SPE2_DDHH): Likewise.
707 (VX_SPE2_DDHH_MASK): Likewise.
708 (VX_SPE2_HH): Likewise.
709 (VX_SPE2_HH_MASK): Likewise.
710 (VX_SPE2_EVMAR): Likewise.
711 (VX_SPE2_EVMAR_MASK): Likewise.
712 (PPCSPE2): Likewise.
713 (PPCEFS2): Likewise.
714 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
715 (powerpc_macros): Map old SPE instructions have new names
716 with the same opcodes. Add SPE2 instructions which just are
717 mapped to SPE2.
718 (spe2_opcodes): Add SPE2 opcodes.
719
720 2017-08-23 Alan Modra <amodra@gmail.com>
721
722 * ppc-opc.c: Formatting and comment fixes. Move insert and
723 extract functions earlier, deleting forward declarations.
724 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
725 RA_MASK.
726
727 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
728
729 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
730
731 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
732 Edmar Wienskoski <edmar.wienskoski@nxp.com>
733
734 * ppc-opc.c (insert_evuimm2_ex0): New function.
735 (extract_evuimm2_ex0): Likewise.
736 (insert_evuimm4_ex0): Likewise.
737 (extract_evuimm4_ex0): Likewise.
738 (insert_evuimm8_ex0): Likewise.
739 (extract_evuimm8_ex0): Likewise.
740 (insert_evuimm_lt16): Likewise.
741 (extract_evuimm_lt16): Likewise.
742 (insert_rD_rS_even): Likewise.
743 (extract_rD_rS_even): Likewise.
744 (insert_off_lsp): Likewise.
745 (extract_off_lsp): Likewise.
746 (RD_EVEN): New operand.
747 (RS_EVEN): Likewise.
748 (RSQ): Adjust.
749 (EVUIMM_LT16): New operand.
750 (HTM_SI): Adjust.
751 (EVUIMM_2_EX0): New operand.
752 (EVUIMM_4): Adjust.
753 (EVUIMM_4_EX0): New operand.
754 (EVUIMM_8): Adjust.
755 (EVUIMM_8_EX0): New operand.
756 (WS): Adjust.
757 (VX_OFF): New operand.
758 (VX_LSP): New macro.
759 (VX_LSP_MASK): Likewise.
760 (VX_LSP_OFF_MASK): Likewise.
761 (PPC_OPCODE_LSP): Likewise.
762 (vle_opcodes): Add LSP opcodes.
763 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
764
765 2017-08-09 Jiong Wang <jiong.wang@arm.com>
766
767 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
768 register operands in CRC instructions.
769 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
770 comments.
771
772 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
773
774 * disassemble.c (disassembler): Mark big and mach with
775 ATTRIBUTE_UNUSED.
776
777 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
778
779 * disassemble.c (disassembler): Remove arch/mach/endian
780 assertions.
781
782 2017-07-25 Nick Clifton <nickc@redhat.com>
783
784 PR 21739
785 * arc-opc.c (insert_rhv2): Use lower case first letter in error
786 message.
787 (insert_r0): Likewise.
788 (insert_r1): Likewise.
789 (insert_r2): Likewise.
790 (insert_r3): Likewise.
791 (insert_sp): Likewise.
792 (insert_gp): Likewise.
793 (insert_pcl): Likewise.
794 (insert_blink): Likewise.
795 (insert_ilink1): Likewise.
796 (insert_ilink2): Likewise.
797 (insert_ras): Likewise.
798 (insert_rbs): Likewise.
799 (insert_rcs): Likewise.
800 (insert_simm3s): Likewise.
801 (insert_rrange): Likewise.
802 (insert_r13el): Likewise.
803 (insert_fpel): Likewise.
804 (insert_blinkel): Likewise.
805 (insert_pclel): Likewise.
806 (insert_nps_bitop_size_2b): Likewise.
807 (insert_nps_imm_offset): Likewise.
808 (insert_nps_imm_entry): Likewise.
809 (insert_nps_size_16bit): Likewise.
810 (insert_nps_##NAME##_pos): Likewise.
811 (insert_nps_##NAME): Likewise.
812 (insert_nps_bitop_ins_ext): Likewise.
813 (insert_nps_##NAME): Likewise.
814 (insert_nps_min_hofs): Likewise.
815 (insert_nps_##NAME): Likewise.
816 (insert_nps_rbdouble_64): Likewise.
817 (insert_nps_misc_imm_offset): Likewise.
818 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
819 option description.
820
821 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
822 Jiong Wang <jiong.wang@arm.com>
823
824 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
825 correct the print.
826 * aarch64-dis-2.c: Regenerated.
827
828 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
829
830 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
831 table.
832
833 2017-07-20 Nick Clifton <nickc@redhat.com>
834
835 * po/de.po: Updated German translation.
836
837 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
838
839 * arc-regs.h (sec_stat): New aux register.
840 (aux_kernel_sp): Likewise.
841 (aux_sec_u_sp): Likewise.
842 (aux_sec_k_sp): Likewise.
843 (sec_vecbase_build): Likewise.
844 (nsc_table_top): Likewise.
845 (nsc_table_base): Likewise.
846 (ersec_stat): Likewise.
847 (aux_sec_except): Likewise.
848
849 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
850
851 * arc-opc.c (extract_uimm12_20): New function.
852 (UIMM12_20): New operand.
853 (SIMM3_5_S): Adjust.
854 * arc-tbl.h (sjli): Add new instruction.
855
856 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
857 John Eric Martin <John.Martin@emmicro-us.com>
858
859 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
860 (UIMM3_23): Adjust accordingly.
861 * arc-regs.h: Add/correct jli_base register.
862 * arc-tbl.h (jli_s): Likewise.
863
864 2017-07-18 Nick Clifton <nickc@redhat.com>
865
866 PR 21775
867 * aarch64-opc.c: Fix spelling typos.
868 * i386-dis.c: Likewise.
869
870 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
871
872 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
873 max_addr_offset and octets variables to size_t.
874
875 2017-07-12 Alan Modra <amodra@gmail.com>
876
877 * po/da.po: Update from translationproject.org/latest/opcodes/.
878 * po/de.po: Likewise.
879 * po/es.po: Likewise.
880 * po/fi.po: Likewise.
881 * po/fr.po: Likewise.
882 * po/id.po: Likewise.
883 * po/it.po: Likewise.
884 * po/nl.po: Likewise.
885 * po/pt_BR.po: Likewise.
886 * po/ro.po: Likewise.
887 * po/sv.po: Likewise.
888 * po/tr.po: Likewise.
889 * po/uk.po: Likewise.
890 * po/vi.po: Likewise.
891 * po/zh_CN.po: Likewise.
892
893 2017-07-11 Yao Qi <yao.qi@linaro.org>
894 Alan Modra <amodra@gmail.com>
895
896 * cgen.sh: Mark generated files read-only.
897 * epiphany-asm.c: Regenerate.
898 * epiphany-desc.c: Regenerate.
899 * epiphany-desc.h: Regenerate.
900 * epiphany-dis.c: Regenerate.
901 * epiphany-ibld.c: Regenerate.
902 * epiphany-opc.c: Regenerate.
903 * epiphany-opc.h: Regenerate.
904 * fr30-asm.c: Regenerate.
905 * fr30-desc.c: Regenerate.
906 * fr30-desc.h: Regenerate.
907 * fr30-dis.c: Regenerate.
908 * fr30-ibld.c: Regenerate.
909 * fr30-opc.c: Regenerate.
910 * fr30-opc.h: Regenerate.
911 * frv-asm.c: Regenerate.
912 * frv-desc.c: Regenerate.
913 * frv-desc.h: Regenerate.
914 * frv-dis.c: Regenerate.
915 * frv-ibld.c: Regenerate.
916 * frv-opc.c: Regenerate.
917 * frv-opc.h: Regenerate.
918 * ip2k-asm.c: Regenerate.
919 * ip2k-desc.c: Regenerate.
920 * ip2k-desc.h: Regenerate.
921 * ip2k-dis.c: Regenerate.
922 * ip2k-ibld.c: Regenerate.
923 * ip2k-opc.c: Regenerate.
924 * ip2k-opc.h: Regenerate.
925 * iq2000-asm.c: Regenerate.
926 * iq2000-desc.c: Regenerate.
927 * iq2000-desc.h: Regenerate.
928 * iq2000-dis.c: Regenerate.
929 * iq2000-ibld.c: Regenerate.
930 * iq2000-opc.c: Regenerate.
931 * iq2000-opc.h: Regenerate.
932 * lm32-asm.c: Regenerate.
933 * lm32-desc.c: Regenerate.
934 * lm32-desc.h: Regenerate.
935 * lm32-dis.c: Regenerate.
936 * lm32-ibld.c: Regenerate.
937 * lm32-opc.c: Regenerate.
938 * lm32-opc.h: Regenerate.
939 * lm32-opinst.c: Regenerate.
940 * m32c-asm.c: Regenerate.
941 * m32c-desc.c: Regenerate.
942 * m32c-desc.h: Regenerate.
943 * m32c-dis.c: Regenerate.
944 * m32c-ibld.c: Regenerate.
945 * m32c-opc.c: Regenerate.
946 * m32c-opc.h: Regenerate.
947 * m32r-asm.c: Regenerate.
948 * m32r-desc.c: Regenerate.
949 * m32r-desc.h: Regenerate.
950 * m32r-dis.c: Regenerate.
951 * m32r-ibld.c: Regenerate.
952 * m32r-opc.c: Regenerate.
953 * m32r-opc.h: Regenerate.
954 * m32r-opinst.c: Regenerate.
955 * mep-asm.c: Regenerate.
956 * mep-desc.c: Regenerate.
957 * mep-desc.h: Regenerate.
958 * mep-dis.c: Regenerate.
959 * mep-ibld.c: Regenerate.
960 * mep-opc.c: Regenerate.
961 * mep-opc.h: Regenerate.
962 * mt-asm.c: Regenerate.
963 * mt-desc.c: Regenerate.
964 * mt-desc.h: Regenerate.
965 * mt-dis.c: Regenerate.
966 * mt-ibld.c: Regenerate.
967 * mt-opc.c: Regenerate.
968 * mt-opc.h: Regenerate.
969 * or1k-asm.c: Regenerate.
970 * or1k-desc.c: Regenerate.
971 * or1k-desc.h: Regenerate.
972 * or1k-dis.c: Regenerate.
973 * or1k-ibld.c: Regenerate.
974 * or1k-opc.c: Regenerate.
975 * or1k-opc.h: Regenerate.
976 * or1k-opinst.c: Regenerate.
977 * xc16x-asm.c: Regenerate.
978 * xc16x-desc.c: Regenerate.
979 * xc16x-desc.h: Regenerate.
980 * xc16x-dis.c: Regenerate.
981 * xc16x-ibld.c: Regenerate.
982 * xc16x-opc.c: Regenerate.
983 * xc16x-opc.h: Regenerate.
984 * xstormy16-asm.c: Regenerate.
985 * xstormy16-desc.c: Regenerate.
986 * xstormy16-desc.h: Regenerate.
987 * xstormy16-dis.c: Regenerate.
988 * xstormy16-ibld.c: Regenerate.
989 * xstormy16-opc.c: Regenerate.
990 * xstormy16-opc.h: Regenerate.
991
992 2017-07-07 Alan Modra <amodra@gmail.com>
993
994 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
995 * m32c-dis.c: Regenerate.
996 * mep-dis.c: Regenerate.
997
998 2017-07-05 Borislav Petkov <bp@suse.de>
999
1000 * i386-dis.c: Enable ModRM.reg /6 aliases.
1001
1002 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1003
1004 * opcodes/arm-dis.c: Support MVFR2 in disassembly
1005 with vmrs and vmsr.
1006
1007 2017-07-04 Tristan Gingold <gingold@adacore.com>
1008
1009 * configure: Regenerate.
1010
1011 2017-07-03 Tristan Gingold <gingold@adacore.com>
1012
1013 * po/opcodes.pot: Regenerate.
1014
1015 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
1016
1017 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
1018 entries to the MSA ASE instruction block.
1019
1020 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
1021 Maciej W. Rozycki <macro@imgtec.com>
1022
1023 * micromips-opc.c (XPA, XPAVZ): New macros.
1024 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
1025 "mthgc0".
1026
1027 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
1028 Maciej W. Rozycki <macro@imgtec.com>
1029
1030 * micromips-opc.c (I36): New macro.
1031 (micromips_opcodes): Add "eretnc".
1032
1033 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
1034 Andrew Bennett <andrew.bennett@imgtec.com>
1035
1036 * mips-dis.c (mips_calculate_combination_ases): Handle the
1037 ASE_XPA_VIRT flag.
1038 (parse_mips_ase_option): New function.
1039 (parse_mips_dis_option): Factor out ASE option handling to the
1040 new function. Call `mips_calculate_combination_ases'.
1041 * mips-opc.c (XPAVZ): New macro.
1042 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
1043 "mfhgc0", "mthc0" and "mthgc0".
1044
1045 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
1046
1047 * mips-dis.c (mips_calculate_combination_ases): New function.
1048 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
1049 calculation to the new function.
1050 (set_default_mips_dis_options): Call the new function.
1051
1052 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1053
1054 * arc-dis.c (parse_disassembler_options): Use
1055 FOR_EACH_DISASSEMBLER_OPTION.
1056
1057 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1058
1059 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
1060 disassembler option strings.
1061 (parse_cpu_option): Likewise.
1062
1063 2017-06-28 Tamar Christina <tamar.christina@arm.com>
1064
1065 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
1066 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
1067 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
1068 (aarch64_feature_dotprod, DOT_INSN): New.
1069 (udot, sdot): New.
1070 * aarch64-dis-2.c: Regenerated.
1071
1072 2017-06-28 Jiong Wang <jiong.wang@arm.com>
1073
1074 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
1075
1076 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
1077 Matthew Fortune <matthew.fortune@imgtec.com>
1078 Andrew Bennett <andrew.bennett@imgtec.com>
1079
1080 * mips-formats.h (INT_BIAS): New macro.
1081 (INT_ADJ): Redefine in INT_BIAS terms.
1082 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
1083 (mips_print_save_restore): New function.
1084 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
1085 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
1086 call.
1087 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
1088 (print_mips16_insn_arg): Call `mips_print_save_restore' for
1089 OP_SAVE_RESTORE_LIST handling, factored out from here.
1090 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
1091 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
1092 (mips_builtin_opcodes): Add "restore" and "save" entries.
1093 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
1094 (IAMR2): New macro.
1095 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
1096
1097 2017-06-23 Andrew Waterman <andrew@sifive.com>
1098
1099 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
1100 alias; do not mark SLTI instruction as an alias.
1101
1102 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1103
1104 * i386-dis.c (RM_0FAE_REG_5): Removed.
1105 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1106 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1107 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1108 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
1109 PREFIX_MOD_3_0F01_REG_5_RM_0.
1110 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
1111 PREFIX_MOD_3_0FAE_REG_5.
1112 (mod_table): Update MOD_0FAE_REG_5.
1113 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
1114 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1115 * i386-tbl.h: Regenerated.
1116
1117 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1118
1119 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1120 * i386-opc.tbl: Likewise.
1121 * i386-tbl.h: Regenerated.
1122
1123 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1124
1125 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1126 and "jmp{&|}".
1127 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1128 prefix.
1129
1130 2017-06-19 Nick Clifton <nickc@redhat.com>
1131
1132 PR binutils/21614
1133 * score-dis.c (score_opcodes): Add sentinel.
1134
1135 2017-06-16 Alan Modra <amodra@gmail.com>
1136
1137 * rx-decode.c: Regenerate.
1138
1139 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1140
1141 PR binutils/21594
1142 * i386-dis.c (OP_E_register): Check valid bnd register.
1143 (OP_G): Likewise.
1144
1145 2017-06-15 Nick Clifton <nickc@redhat.com>
1146
1147 PR binutils/21595
1148 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1149 range value.
1150
1151 2017-06-15 Nick Clifton <nickc@redhat.com>
1152
1153 PR binutils/21588
1154 * rl78-decode.opc (OP_BUF_LEN): Define.
1155 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1156 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1157 array.
1158 * rl78-decode.c: Regenerate.
1159
1160 2017-06-15 Nick Clifton <nickc@redhat.com>
1161
1162 PR binutils/21586
1163 * bfin-dis.c (gregs): Clip index to prevent overflow.
1164 (regs): Likewise.
1165 (regs_lo): Likewise.
1166 (regs_hi): Likewise.
1167
1168 2017-06-14 Nick Clifton <nickc@redhat.com>
1169
1170 PR binutils/21576
1171 * score7-dis.c (score_opcodes): Add sentinel.
1172
1173 2017-06-14 Yao Qi <yao.qi@linaro.org>
1174
1175 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1176 * arm-dis.c: Likewise.
1177 * ia64-dis.c: Likewise.
1178 * mips-dis.c: Likewise.
1179 * spu-dis.c: Likewise.
1180 * disassemble.h (print_insn_aarch64): New declaration, moved from
1181 include/dis-asm.h.
1182 (print_insn_big_arm, print_insn_big_mips): Likewise.
1183 (print_insn_i386, print_insn_ia64): Likewise.
1184 (print_insn_little_arm, print_insn_little_mips): Likewise.
1185
1186 2017-06-14 Nick Clifton <nickc@redhat.com>
1187
1188 PR binutils/21587
1189 * rx-decode.opc: Include libiberty.h
1190 (GET_SCALE): New macro - validates access to SCALE array.
1191 (GET_PSCALE): New macro - validates access to PSCALE array.
1192 (DIs, SIs, S2Is, rx_disp): Use new macros.
1193 * rx-decode.c: Regenerate.
1194
1195 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1196
1197 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1198
1199 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1200
1201 * arc-dis.c (enforced_isa_mask): Declare.
1202 (cpu_types): Likewise.
1203 (parse_cpu_option): New function.
1204 (parse_disassembler_options): Use it.
1205 (print_insn_arc): Use enforced_isa_mask.
1206 (print_arc_disassembler_options): Document new options.
1207
1208 2017-05-24 Yao Qi <yao.qi@linaro.org>
1209
1210 * alpha-dis.c: Include disassemble.h, don't include
1211 dis-asm.h.
1212 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1213 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1214 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1215 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1216 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1217 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1218 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1219 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1220 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1221 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1222 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1223 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1224 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1225 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1226 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1227 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1228 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1229 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1230 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1231 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1232 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1233 * z80-dis.c, z8k-dis.c: Likewise.
1234 * disassemble.h: New file.
1235
1236 2017-05-24 Yao Qi <yao.qi@linaro.org>
1237
1238 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1239 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1240
1241 2017-05-24 Yao Qi <yao.qi@linaro.org>
1242
1243 * disassemble.c (disassembler): Add arguments a, big and mach.
1244 Use them.
1245
1246 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1247
1248 * i386-dis.c (NOTRACK_Fixup): New.
1249 (NOTRACK): Likewise.
1250 (NOTRACK_PREFIX): Likewise.
1251 (last_active_prefix): Likewise.
1252 (reg_table): Use NOTRACK on indirect call and jmp.
1253 (ckprefix): Set last_active_prefix.
1254 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1255 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1256 * i386-opc.h (NoTrackPrefixOk): New.
1257 (i386_opcode_modifier): Add notrackprefixok.
1258 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1259 Add notrack.
1260 * i386-tbl.h: Regenerated.
1261
1262 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1263
1264 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1265 (X_IMM2): Define.
1266 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1267 bfd_mach_sparc_v9m8.
1268 (print_insn_sparc): Handle new operand types.
1269 * sparc-opc.c (MASK_M8): Define.
1270 (v6): Add MASK_M8.
1271 (v6notlet): Likewise.
1272 (v7): Likewise.
1273 (v8): Likewise.
1274 (v9): Likewise.
1275 (v9a): Likewise.
1276 (v9b): Likewise.
1277 (v9c): Likewise.
1278 (v9d): Likewise.
1279 (v9e): Likewise.
1280 (v9v): Likewise.
1281 (v9m): Likewise.
1282 (v9andleon): Likewise.
1283 (m8): Define.
1284 (HWS_VM8): Define.
1285 (HWS2_VM8): Likewise.
1286 (sparc_opcode_archs): Add entry for "m8".
1287 (sparc_opcodes): Add OSA2017 and M8 instructions
1288 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1289 fpx{ll,ra,rl}64x,
1290 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1291 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1292 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1293 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1294 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1295 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1296 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1297 ASI_CORE_SELECT_COMMIT_NHT.
1298
1299 2017-05-18 Alan Modra <amodra@gmail.com>
1300
1301 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1302 * aarch64-dis.c: Likewise.
1303 * aarch64-gen.c: Likewise.
1304 * aarch64-opc.c: Likewise.
1305
1306 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1307 Matthew Fortune <matthew.fortune@imgtec.com>
1308
1309 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1310 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1311 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1312 (print_insn_arg) <OP_REG28>: Add handler.
1313 (validate_insn_args) <OP_REG28>: Handle.
1314 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1315 32-bit encoding and 9-bit immediates.
1316 (print_insn_mips16): Handle MIPS16 instructions that require
1317 32-bit encoding and MFC0/MTC0 operand decoding.
1318 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1319 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1320 (RD_C0, WR_C0, E2, E2MT): New macros.
1321 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1322 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1323 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1324 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1325 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1326 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1327 instructions, "swl", "swr", "sync" and its "sync_acquire",
1328 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1329 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1330 regular/extended entries for original MIPS16 ISA revision
1331 instructions whose extended forms are subdecoded in the MIPS16e2
1332 ISA revision: "li", "sll" and "srl".
1333
1334 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1335
1336 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1337 reference in CP0 move operand decoding.
1338
1339 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1340
1341 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1342 type to hexadecimal.
1343 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1344
1345 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1346
1347 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1348 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1349 "sync_rmb" and "sync_wmb" as aliases.
1350 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1351 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1352
1353 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1354
1355 * arc-dis.c (parse_option): Update quarkse_em option..
1356 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1357 QUARKSE1.
1358 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1359
1360 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1361
1362 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1363
1364 2017-05-01 Michael Clark <michaeljclark@mac.com>
1365
1366 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1367 register.
1368
1369 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1370
1371 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1372 and branches and not synthetic data instructions.
1373
1374 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1375
1376 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1377
1378 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1379
1380 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1381 * arc-opc.c (insert_r13el): New function.
1382 (R13_EL): Define.
1383 * arc-tbl.h: Add new enter/leave variants.
1384
1385 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1386
1387 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1388
1389 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1390
1391 * mips-dis.c (print_mips_disassembler_options): Add
1392 `no-aliases'.
1393
1394 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1395
1396 * mips16-opc.c (AL): New macro.
1397 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1398 of "ld" and "lw" as aliases.
1399
1400 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1401
1402 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1403 arguments.
1404
1405 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1406 Alan Modra <amodra@gmail.com>
1407
1408 * ppc-opc.c (ELEV): Define.
1409 (vle_opcodes): Add se_rfgi and e_sc.
1410 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1411 for E200Z4.
1412
1413 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1414
1415 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1416
1417 2017-04-21 Nick Clifton <nickc@redhat.com>
1418
1419 PR binutils/21380
1420 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1421 LD3R and LD4R.
1422
1423 2017-04-13 Alan Modra <amodra@gmail.com>
1424
1425 * epiphany-desc.c: Regenerate.
1426 * fr30-desc.c: Regenerate.
1427 * frv-desc.c: Regenerate.
1428 * ip2k-desc.c: Regenerate.
1429 * iq2000-desc.c: Regenerate.
1430 * lm32-desc.c: Regenerate.
1431 * m32c-desc.c: Regenerate.
1432 * m32r-desc.c: Regenerate.
1433 * mep-desc.c: Regenerate.
1434 * mt-desc.c: Regenerate.
1435 * or1k-desc.c: Regenerate.
1436 * xc16x-desc.c: Regenerate.
1437 * xstormy16-desc.c: Regenerate.
1438
1439 2017-04-11 Alan Modra <amodra@gmail.com>
1440
1441 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1442 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1443 PPC_OPCODE_TMR for e6500.
1444 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1445 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1446 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1447 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1448 (PPCHTM): Define as PPC_OPCODE_POWER8.
1449 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1450
1451 2017-04-10 Alan Modra <amodra@gmail.com>
1452
1453 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1454 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1455 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1456 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1457
1458 2017-04-09 Pip Cet <pipcet@gmail.com>
1459
1460 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1461 appropriate floating-point precision directly.
1462
1463 2017-04-07 Alan Modra <amodra@gmail.com>
1464
1465 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1466 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1467 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1468 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1469 vector instructions with E6500 not PPCVEC2.
1470
1471 2017-04-06 Pip Cet <pipcet@gmail.com>
1472
1473 * Makefile.am: Add wasm32-dis.c.
1474 * configure.ac: Add wasm32-dis.c to wasm32 target.
1475 * disassemble.c: Add wasm32 disassembler code.
1476 * wasm32-dis.c: New file.
1477 * Makefile.in: Regenerate.
1478 * configure: Regenerate.
1479 * po/POTFILES.in: Regenerate.
1480 * po/opcodes.pot: Regenerate.
1481
1482 2017-04-05 Pedro Alves <palves@redhat.com>
1483
1484 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1485 * arm-dis.c (parse_arm_disassembler_options): Constify.
1486 * ppc-dis.c (powerpc_init_dialect): Constify local.
1487 * vax-dis.c (parse_disassembler_options): Constify.
1488
1489 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1490
1491 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1492 RISCV_GP_SYMBOL.
1493
1494 2017-03-30 Pip Cet <pipcet@gmail.com>
1495
1496 * configure.ac: Add (empty) bfd_wasm32_arch target.
1497 * configure: Regenerate
1498 * po/opcodes.pot: Regenerate.
1499
1500 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1501
1502 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1503 OSA2015.
1504 * opcodes/sparc-opc.c (asi_table): New ASIs.
1505
1506 2017-03-29 Alan Modra <amodra@gmail.com>
1507
1508 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1509 "raw" option.
1510 (lookup_powerpc): Don't special case -1 dialect. Handle
1511 PPC_OPCODE_RAW.
1512 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1513 lookup_powerpc call, pass it on second.
1514
1515 2017-03-27 Alan Modra <amodra@gmail.com>
1516
1517 PR 21303
1518 * ppc-dis.c (struct ppc_mopt): Comment.
1519 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1520
1521 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1522
1523 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1524 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1525 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1526 (insert_nps_misc_imm_offset): New function.
1527 (extract_nps_misc imm_offset): New function.
1528 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1529 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1530
1531 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1532
1533 * s390-mkopc.c (main): Remove vx2 check.
1534 * s390-opc.txt: Remove vx2 instruction flags.
1535
1536 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1537
1538 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1539 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1540 (insert_nps_imm_offset): New function.
1541 (extract_nps_imm_offset): New function.
1542 (insert_nps_imm_entry): New function.
1543 (extract_nps_imm_entry): New function.
1544
1545 2017-03-17 Alan Modra <amodra@gmail.com>
1546
1547 PR 21248
1548 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1549 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1550 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1551
1552 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1553
1554 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1555 <c.andi>: Likewise.
1556 <c.addiw> Likewise.
1557
1558 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1559
1560 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1561
1562 2017-03-13 Andrew Waterman <andrew@sifive.com>
1563
1564 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1565 <srl> Likewise.
1566 <srai> Likewise.
1567 <sra> Likewise.
1568
1569 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1570
1571 * i386-gen.c (opcode_modifiers): Replace S with Load.
1572 * i386-opc.h (S): Removed.
1573 (Load): New.
1574 (i386_opcode_modifier): Replace s with load.
1575 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1576 and {evex}. Replace S with Load.
1577 * i386-tbl.h: Regenerated.
1578
1579 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1580
1581 * i386-opc.tbl: Use CpuCET on rdsspq.
1582 * i386-tbl.h: Regenerated.
1583
1584 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1585
1586 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1587 <vsx>: Do not use PPC_OPCODE_VSX3;
1588
1589 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1590
1591 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1592
1593 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1594
1595 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1596 (MOD_0F1E_PREFIX_1): Likewise.
1597 (MOD_0F38F5_PREFIX_2): Likewise.
1598 (MOD_0F38F6_PREFIX_0): Likewise.
1599 (RM_0F1E_MOD_3_REG_7): Likewise.
1600 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1601 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1602 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1603 (PREFIX_0F1E): Likewise.
1604 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1605 (PREFIX_0F38F5): Likewise.
1606 (dis386_twobyte): Use PREFIX_0F1E.
1607 (reg_table): Add REG_0F1E_MOD_3.
1608 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1609 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1610 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1611 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1612 (three_byte_table): Use PREFIX_0F38F5.
1613 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1614 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1615 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1616 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1617 PREFIX_MOD_3_0F01_REG_5_RM_2.
1618 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1619 (cpu_flags): Add CpuCET.
1620 * i386-opc.h (CpuCET): New enum.
1621 (CpuUnused): Commented out.
1622 (i386_cpu_flags): Add cpucet.
1623 * i386-opc.tbl: Add Intel CET instructions.
1624 * i386-init.h: Regenerated.
1625 * i386-tbl.h: Likewise.
1626
1627 2017-03-06 Alan Modra <amodra@gmail.com>
1628
1629 PR 21124
1630 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1631 (extract_raq, extract_ras, extract_rbx): New functions.
1632 (powerpc_operands): Use opposite corresponding insert function.
1633 (Q_MASK): Define.
1634 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1635 register restriction.
1636
1637 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1638
1639 * disassemble.c Include "safe-ctype.h".
1640 (disassemble_init_for_target): Handle s390 init.
1641 (remove_whitespace_and_extra_commas): New function.
1642 (disassembler_options_cmp): Likewise.
1643 * arm-dis.c: Include "libiberty.h".
1644 (NUM_ELEM): Delete.
1645 (regnames): Use long disassembler style names.
1646 Add force-thumb and no-force-thumb options.
1647 (NUM_ARM_REGNAMES): Rename from this...
1648 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1649 (get_arm_regname_num_options): Delete.
1650 (set_arm_regname_option): Likewise.
1651 (get_arm_regnames): Likewise.
1652 (parse_disassembler_options): Likewise.
1653 (parse_arm_disassembler_option): Rename from this...
1654 (parse_arm_disassembler_options): ...to this. Make static.
1655 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1656 (print_insn): Use parse_arm_disassembler_options.
1657 (disassembler_options_arm): New function.
1658 (print_arm_disassembler_options): Handle updated regnames.
1659 * ppc-dis.c: Include "libiberty.h".
1660 (ppc_opts): Add "32" and "64" entries.
1661 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1662 (powerpc_init_dialect): Add break to switch statement.
1663 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1664 (disassembler_options_powerpc): New function.
1665 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1666 Remove printing of "32" and "64".
1667 * s390-dis.c: Include "libiberty.h".
1668 (init_flag): Remove unneeded variable.
1669 (struct s390_options_t): New structure type.
1670 (options): New structure.
1671 (init_disasm): Rename from this...
1672 (disassemble_init_s390): ...to this. Add initializations for
1673 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1674 (print_insn_s390): Delete call to init_disasm.
1675 (disassembler_options_s390): New function.
1676 (print_s390_disassembler_options): Print using information from
1677 struct 'options'.
1678 * po/opcodes.pot: Regenerate.
1679
1680 2017-02-28 Jan Beulich <jbeulich@suse.com>
1681
1682 * i386-dis.c (PCMPESTR_Fixup): New.
1683 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1684 (prefix_table): Use PCMPESTR_Fixup.
1685 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1686 PCMPESTR_Fixup.
1687 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1688 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1689 Split 64-bit and non-64-bit variants.
1690 * opcodes/i386-tbl.h: Re-generate.
1691
1692 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1693
1694 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1695 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1696 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1697 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1698 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1699 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1700 (OP_SVE_V_HSD): New macros.
1701 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1702 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1703 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1704 (aarch64_opcode_table): Add new SVE instructions.
1705 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1706 for rotation operands. Add new SVE operands.
1707 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1708 (ins_sve_quad_index): Likewise.
1709 (ins_imm_rotate): Split into...
1710 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1711 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1712 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1713 functions.
1714 (aarch64_ins_sve_addr_ri_s4): New function.
1715 (aarch64_ins_sve_quad_index): Likewise.
1716 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1717 * aarch64-asm-2.c: Regenerate.
1718 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1719 (ext_sve_quad_index): Likewise.
1720 (ext_imm_rotate): Split into...
1721 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1722 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1723 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1724 functions.
1725 (aarch64_ext_sve_addr_ri_s4): New function.
1726 (aarch64_ext_sve_quad_index): Likewise.
1727 (aarch64_ext_sve_index): Allow quad indices.
1728 (do_misc_decoding): Likewise.
1729 * aarch64-dis-2.c: Regenerate.
1730 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1731 aarch64_field_kinds.
1732 (OPD_F_OD_MASK): Widen by one bit.
1733 (OPD_F_NO_ZR): Bump accordingly.
1734 (get_operand_field_width): New function.
1735 * aarch64-opc.c (fields): Add new SVE fields.
1736 (operand_general_constraint_met_p): Handle new SVE operands.
1737 (aarch64_print_operand): Likewise.
1738 * aarch64-opc-2.c: Regenerate.
1739
1740 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1741
1742 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1743 (aarch64_feature_compnum): ...this.
1744 (SIMD_V8_3): Replace with...
1745 (COMPNUM): ...this.
1746 (CNUM_INSN): New macro.
1747 (aarch64_opcode_table): Use it for the complex number instructions.
1748
1749 2017-02-24 Jan Beulich <jbeulich@suse.com>
1750
1751 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1752
1753 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1754
1755 Add support for associating SPARC ASIs with an architecture level.
1756 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1757 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1758 decoding of SPARC ASIs.
1759
1760 2017-02-23 Jan Beulich <jbeulich@suse.com>
1761
1762 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1763 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1764
1765 2017-02-21 Jan Beulich <jbeulich@suse.com>
1766
1767 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1768 1 (instead of to itself). Correct typo.
1769
1770 2017-02-14 Andrew Waterman <andrew@sifive.com>
1771
1772 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1773 pseudoinstructions.
1774
1775 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1776
1777 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1778 (aarch64_sys_reg_supported_p): Handle them.
1779
1780 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1781
1782 * arc-opc.c (UIMM6_20R): Define.
1783 (SIMM12_20): Use above.
1784 (SIMM12_20R): Define.
1785 (SIMM3_5_S): Use above.
1786 (UIMM7_A32_11R_S): Define.
1787 (UIMM7_9_S): Use above.
1788 (UIMM3_13R_S): Define.
1789 (SIMM11_A32_7_S): Use above.
1790 (SIMM9_8R): Define.
1791 (UIMM10_A32_8_S): Use above.
1792 (UIMM8_8R_S): Define.
1793 (W6): Use above.
1794 (arc_relax_opcodes): Use all above defines.
1795
1796 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1797
1798 * arc-regs.h: Distinguish some of the registers different on
1799 ARC700 and HS38 cpus.
1800
1801 2017-02-14 Alan Modra <amodra@gmail.com>
1802
1803 PR 21118
1804 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1805 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1806
1807 2017-02-11 Stafford Horne <shorne@gmail.com>
1808 Alan Modra <amodra@gmail.com>
1809
1810 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1811 Use insn_bytes_value and insn_int_value directly instead. Don't
1812 free allocated memory until function exit.
1813
1814 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1815
1816 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1817
1818 2017-02-03 Nick Clifton <nickc@redhat.com>
1819
1820 PR 21096
1821 * aarch64-opc.c (print_register_list): Ensure that the register
1822 list index will fir into the tb buffer.
1823 (print_register_offset_address): Likewise.
1824 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1825
1826 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1827
1828 PR 21056
1829 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1830 instructions when the previous fetch packet ends with a 32-bit
1831 instruction.
1832
1833 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1834
1835 * pru-opc.c: Remove vague reference to a future GDB port.
1836
1837 2017-01-20 Nick Clifton <nickc@redhat.com>
1838
1839 * po/ga.po: Updated Irish translation.
1840
1841 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1842
1843 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1844
1845 2017-01-13 Yao Qi <yao.qi@linaro.org>
1846
1847 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1848 if FETCH_DATA returns 0.
1849 (m68k_scan_mask): Likewise.
1850 (print_insn_m68k): Update code to handle -1 return value.
1851
1852 2017-01-13 Yao Qi <yao.qi@linaro.org>
1853
1854 * m68k-dis.c (enum print_insn_arg_error): New.
1855 (NEXTBYTE): Replace -3 with
1856 PRINT_INSN_ARG_MEMORY_ERROR.
1857 (NEXTULONG): Likewise.
1858 (NEXTSINGLE): Likewise.
1859 (NEXTDOUBLE): Likewise.
1860 (NEXTDOUBLE): Likewise.
1861 (NEXTPACKED): Likewise.
1862 (FETCH_ARG): Likewise.
1863 (FETCH_DATA): Update comments.
1864 (print_insn_arg): Update comments. Replace magic numbers with
1865 enum.
1866 (match_insn_m68k): Likewise.
1867
1868 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1869
1870 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1871 * i386-dis-evex.h (evex_table): Updated.
1872 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1873 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1874 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1875 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1876 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1877 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1878 * i386-init.h: Regenerate.
1879 * i386-tbl.h: Ditto.
1880
1881 2017-01-12 Yao Qi <yao.qi@linaro.org>
1882
1883 * msp430-dis.c (msp430_singleoperand): Return -1 if
1884 msp430dis_opcode_signed returns false.
1885 (msp430_doubleoperand): Likewise.
1886 (msp430_branchinstr): Return -1 if
1887 msp430dis_opcode_unsigned returns false.
1888 (msp430x_calla_instr): Likewise.
1889 (print_insn_msp430): Likewise.
1890
1891 2017-01-05 Nick Clifton <nickc@redhat.com>
1892
1893 PR 20946
1894 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1895 could not be matched.
1896 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1897 NULL.
1898
1899 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1900
1901 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1902 (aarch64_opcode_table): Use RCPC_INSN.
1903
1904 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1905
1906 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1907 extension.
1908 * riscv-opcodes/all-opcodes: Likewise.
1909
1910 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1911
1912 * riscv-dis.c (print_insn_args): Add fall through comment.
1913
1914 2017-01-03 Nick Clifton <nickc@redhat.com>
1915
1916 * po/sr.po: New Serbian translation.
1917 * configure.ac (ALL_LINGUAS): Add sr.
1918 * configure: Regenerate.
1919
1920 2017-01-02 Alan Modra <amodra@gmail.com>
1921
1922 * epiphany-desc.h: Regenerate.
1923 * epiphany-opc.h: Regenerate.
1924 * fr30-desc.h: Regenerate.
1925 * fr30-opc.h: Regenerate.
1926 * frv-desc.h: Regenerate.
1927 * frv-opc.h: Regenerate.
1928 * ip2k-desc.h: Regenerate.
1929 * ip2k-opc.h: Regenerate.
1930 * iq2000-desc.h: Regenerate.
1931 * iq2000-opc.h: Regenerate.
1932 * lm32-desc.h: Regenerate.
1933 * lm32-opc.h: Regenerate.
1934 * m32c-desc.h: Regenerate.
1935 * m32c-opc.h: Regenerate.
1936 * m32r-desc.h: Regenerate.
1937 * m32r-opc.h: Regenerate.
1938 * mep-desc.h: Regenerate.
1939 * mep-opc.h: Regenerate.
1940 * mt-desc.h: Regenerate.
1941 * mt-opc.h: Regenerate.
1942 * or1k-desc.h: Regenerate.
1943 * or1k-opc.h: Regenerate.
1944 * xc16x-desc.h: Regenerate.
1945 * xc16x-opc.h: Regenerate.
1946 * xstormy16-desc.h: Regenerate.
1947 * xstormy16-opc.h: Regenerate.
1948
1949 2017-01-02 Alan Modra <amodra@gmail.com>
1950
1951 Update year range in copyright notice of all files.
1952
1953 For older changes see ChangeLog-2016
1954 \f
1955 Copyright (C) 2017 Free Software Foundation, Inc.
1956
1957 Copying and distribution of this file, with or without modification,
1958 are permitted in any medium without royalty provided the copyright
1959 notice and this notice are preserved.
1960
1961 Local Variables:
1962 mode: change-log
1963 left-margin: 8
1964 fill-column: 74
1965 version-control: never
1966 End:
GDB Binutils - Deliverables
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