1 2018-10-03 Tamar Christina <tamar.christina@arm.com>
3 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
4 * aarch64-opc.c (verify_ldpsw): Update arguments.
6 2018-10-03 Tamar Christina <tamar.christina@arm.com>
8 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
9 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
11 2018-10-03 Tamar Christina <tamar.christina@arm.com>
13 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
14 * aarch64-dis.c (insn_sequence): New.
16 2018-10-03 Tamar Christina <tamar.christina@arm.com>
18 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
19 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
20 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
21 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
24 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
26 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
28 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
29 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
30 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
31 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
32 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
33 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
34 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
36 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
38 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
40 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
42 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
43 are used when extracting signed fields and converting them to
44 potentially 64-bit types.
46 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
48 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
49 * Makefile.in: Re-generate.
50 * aclocal.m4: Re-generate.
51 * configure: Re-generate.
52 * configure.ac: Remove check for -Wno-missing-field-initializers.
53 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
54 (csky_v2_opcodes): Likewise.
56 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
58 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
60 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
62 * nds32-asm.c (operand_fields): Remove the unused fields.
63 (nds32_opcodes): Remove the unused instructions.
64 * nds32-dis.c (nds32_ex9_info): Removed.
65 (nds32_parse_opcode): Updated.
66 (print_insn_nds32): Likewise.
67 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
68 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
69 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
70 build_opcode_hash_table): New functions.
71 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
72 nds32_opcode_table): New.
73 (hw_ktabs): Declare it to a pointer rather than an array.
74 (build_hash_table): Removed.
75 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
76 SYN_ROPT and upadte HW_GPR and HW_INT.
77 * nds32-dis.c (keywords): Remove const.
78 (match_field): New function.
79 (nds32_parse_opcode): Updated.
80 * disassemble.c (disassemble_init_for_target):
81 Add disassemble_init_nds32.
82 * nds32-dis.c (eum map_type): New.
83 (nds32_private_data): Likewise.
84 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
85 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
86 (print_insn_nds32): Updated.
87 * nds32-asm.c (parse_aext_reg): Add new parameter.
88 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
91 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
92 (operand_fields): Add new fields.
93 (nds32_opcodes): Add new instructions.
94 (keyword_aridxi_mx): New keyword.
95 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
97 (ALU2_1, ALU2_2, ALU2_3): New macros.
98 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
100 2018-09-17 Kito Cheng <kito@andestech.com>
102 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
104 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
107 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
108 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
109 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
110 (EVEX_LEN_0F7E_P_1): Likewise.
111 (EVEX_LEN_0F7E_P_2): Likewise.
112 (EVEX_LEN_0FD6_P_2): Likewise.
113 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
114 (EVEX_LEN_TABLE): Likewise.
115 (EVEX_LEN_0F6E_P_2): New enum.
116 (EVEX_LEN_0F7E_P_1): Likewise.
117 (EVEX_LEN_0F7E_P_2): Likewise.
118 (EVEX_LEN_0FD6_P_2): Likewise.
119 (evex_len_table): New.
120 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
121 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
122 * i386-tbl.h: Regenerated.
124 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
127 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
128 VEX_LEN_0F7E_P_2 entries.
129 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
130 * i386-tbl.h: Regenerated.
132 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
134 * i386-dis.c (VZERO_Fixup): Removed.
136 (VEX_LEN_0F10_P_1): Likewise.
137 (VEX_LEN_0F10_P_3): Likewise.
138 (VEX_LEN_0F11_P_1): Likewise.
139 (VEX_LEN_0F11_P_3): Likewise.
140 (VEX_LEN_0F2E_P_0): Likewise.
141 (VEX_LEN_0F2E_P_2): Likewise.
142 (VEX_LEN_0F2F_P_0): Likewise.
143 (VEX_LEN_0F2F_P_2): Likewise.
144 (VEX_LEN_0F51_P_1): Likewise.
145 (VEX_LEN_0F51_P_3): Likewise.
146 (VEX_LEN_0F52_P_1): Likewise.
147 (VEX_LEN_0F53_P_1): Likewise.
148 (VEX_LEN_0F58_P_1): Likewise.
149 (VEX_LEN_0F58_P_3): Likewise.
150 (VEX_LEN_0F59_P_1): Likewise.
151 (VEX_LEN_0F59_P_3): Likewise.
152 (VEX_LEN_0F5A_P_1): Likewise.
153 (VEX_LEN_0F5A_P_3): Likewise.
154 (VEX_LEN_0F5C_P_1): Likewise.
155 (VEX_LEN_0F5C_P_3): Likewise.
156 (VEX_LEN_0F5D_P_1): Likewise.
157 (VEX_LEN_0F5D_P_3): Likewise.
158 (VEX_LEN_0F5E_P_1): Likewise.
159 (VEX_LEN_0F5E_P_3): Likewise.
160 (VEX_LEN_0F5F_P_1): Likewise.
161 (VEX_LEN_0F5F_P_3): Likewise.
162 (VEX_LEN_0FC2_P_1): Likewise.
163 (VEX_LEN_0FC2_P_3): Likewise.
164 (VEX_LEN_0F3A0A_P_2): Likewise.
165 (VEX_LEN_0F3A0B_P_2): Likewise.
166 (VEX_W_0F10_P_0): Likewise.
167 (VEX_W_0F10_P_1): Likewise.
168 (VEX_W_0F10_P_2): Likewise.
169 (VEX_W_0F10_P_3): Likewise.
170 (VEX_W_0F11_P_0): Likewise.
171 (VEX_W_0F11_P_1): Likewise.
172 (VEX_W_0F11_P_2): Likewise.
173 (VEX_W_0F11_P_3): Likewise.
174 (VEX_W_0F12_P_0_M_0): Likewise.
175 (VEX_W_0F12_P_0_M_1): Likewise.
176 (VEX_W_0F12_P_1): Likewise.
177 (VEX_W_0F12_P_2): Likewise.
178 (VEX_W_0F12_P_3): Likewise.
179 (VEX_W_0F13_M_0): Likewise.
180 (VEX_W_0F14): Likewise.
181 (VEX_W_0F15): Likewise.
182 (VEX_W_0F16_P_0_M_0): Likewise.
183 (VEX_W_0F16_P_0_M_1): Likewise.
184 (VEX_W_0F16_P_1): Likewise.
185 (VEX_W_0F16_P_2): Likewise.
186 (VEX_W_0F17_M_0): Likewise.
187 (VEX_W_0F28): Likewise.
188 (VEX_W_0F29): Likewise.
189 (VEX_W_0F2B_M_0): Likewise.
190 (VEX_W_0F2E_P_0): Likewise.
191 (VEX_W_0F2E_P_2): Likewise.
192 (VEX_W_0F2F_P_0): Likewise.
193 (VEX_W_0F2F_P_2): Likewise.
194 (VEX_W_0F50_M_0): Likewise.
195 (VEX_W_0F51_P_0): Likewise.
196 (VEX_W_0F51_P_1): Likewise.
197 (VEX_W_0F51_P_2): Likewise.
198 (VEX_W_0F51_P_3): Likewise.
199 (VEX_W_0F52_P_0): Likewise.
200 (VEX_W_0F52_P_1): Likewise.
201 (VEX_W_0F53_P_0): Likewise.
202 (VEX_W_0F53_P_1): Likewise.
203 (VEX_W_0F58_P_0): Likewise.
204 (VEX_W_0F58_P_1): Likewise.
205 (VEX_W_0F58_P_2): Likewise.
206 (VEX_W_0F58_P_3): Likewise.
207 (VEX_W_0F59_P_0): Likewise.
208 (VEX_W_0F59_P_1): Likewise.
209 (VEX_W_0F59_P_2): Likewise.
210 (VEX_W_0F59_P_3): Likewise.
211 (VEX_W_0F5A_P_0): Likewise.
212 (VEX_W_0F5A_P_1): Likewise.
213 (VEX_W_0F5A_P_3): Likewise.
214 (VEX_W_0F5B_P_0): Likewise.
215 (VEX_W_0F5B_P_1): Likewise.
216 (VEX_W_0F5B_P_2): Likewise.
217 (VEX_W_0F5C_P_0): Likewise.
218 (VEX_W_0F5C_P_1): Likewise.
219 (VEX_W_0F5C_P_2): Likewise.
220 (VEX_W_0F5C_P_3): Likewise.
221 (VEX_W_0F5D_P_0): Likewise.
222 (VEX_W_0F5D_P_1): Likewise.
223 (VEX_W_0F5D_P_2): Likewise.
224 (VEX_W_0F5D_P_3): Likewise.
225 (VEX_W_0F5E_P_0): Likewise.
226 (VEX_W_0F5E_P_1): Likewise.
227 (VEX_W_0F5E_P_2): Likewise.
228 (VEX_W_0F5E_P_3): Likewise.
229 (VEX_W_0F5F_P_0): Likewise.
230 (VEX_W_0F5F_P_1): Likewise.
231 (VEX_W_0F5F_P_2): Likewise.
232 (VEX_W_0F5F_P_3): Likewise.
233 (VEX_W_0F60_P_2): Likewise.
234 (VEX_W_0F61_P_2): Likewise.
235 (VEX_W_0F62_P_2): Likewise.
236 (VEX_W_0F63_P_2): Likewise.
237 (VEX_W_0F64_P_2): Likewise.
238 (VEX_W_0F65_P_2): Likewise.
239 (VEX_W_0F66_P_2): Likewise.
240 (VEX_W_0F67_P_2): Likewise.
241 (VEX_W_0F68_P_2): Likewise.
242 (VEX_W_0F69_P_2): Likewise.
243 (VEX_W_0F6A_P_2): Likewise.
244 (VEX_W_0F6B_P_2): Likewise.
245 (VEX_W_0F6C_P_2): Likewise.
246 (VEX_W_0F6D_P_2): Likewise.
247 (VEX_W_0F6F_P_1): Likewise.
248 (VEX_W_0F6F_P_2): Likewise.
249 (VEX_W_0F70_P_1): Likewise.
250 (VEX_W_0F70_P_2): Likewise.
251 (VEX_W_0F70_P_3): Likewise.
252 (VEX_W_0F71_R_2_P_2): Likewise.
253 (VEX_W_0F71_R_4_P_2): Likewise.
254 (VEX_W_0F71_R_6_P_2): Likewise.
255 (VEX_W_0F72_R_2_P_2): Likewise.
256 (VEX_W_0F72_R_4_P_2): Likewise.
257 (VEX_W_0F72_R_6_P_2): Likewise.
258 (VEX_W_0F73_R_2_P_2): Likewise.
259 (VEX_W_0F73_R_3_P_2): Likewise.
260 (VEX_W_0F73_R_6_P_2): Likewise.
261 (VEX_W_0F73_R_7_P_2): Likewise.
262 (VEX_W_0F74_P_2): Likewise.
263 (VEX_W_0F75_P_2): Likewise.
264 (VEX_W_0F76_P_2): Likewise.
265 (VEX_W_0F77_P_0): Likewise.
266 (VEX_W_0F7C_P_2): Likewise.
267 (VEX_W_0F7C_P_3): Likewise.
268 (VEX_W_0F7D_P_2): Likewise.
269 (VEX_W_0F7D_P_3): Likewise.
270 (VEX_W_0F7E_P_1): Likewise.
271 (VEX_W_0F7F_P_1): Likewise.
272 (VEX_W_0F7F_P_2): Likewise.
273 (VEX_W_0FAE_R_2_M_0): Likewise.
274 (VEX_W_0FAE_R_3_M_0): Likewise.
275 (VEX_W_0FC2_P_0): Likewise.
276 (VEX_W_0FC2_P_1): Likewise.
277 (VEX_W_0FC2_P_2): Likewise.
278 (VEX_W_0FC2_P_3): Likewise.
279 (VEX_W_0FD0_P_2): Likewise.
280 (VEX_W_0FD0_P_3): Likewise.
281 (VEX_W_0FD1_P_2): Likewise.
282 (VEX_W_0FD2_P_2): Likewise.
283 (VEX_W_0FD3_P_2): Likewise.
284 (VEX_W_0FD4_P_2): Likewise.
285 (VEX_W_0FD5_P_2): Likewise.
286 (VEX_W_0FD6_P_2): Likewise.
287 (VEX_W_0FD7_P_2_M_1): Likewise.
288 (VEX_W_0FD8_P_2): Likewise.
289 (VEX_W_0FD9_P_2): Likewise.
290 (VEX_W_0FDA_P_2): Likewise.
291 (VEX_W_0FDB_P_2): Likewise.
292 (VEX_W_0FDC_P_2): Likewise.
293 (VEX_W_0FDD_P_2): Likewise.
294 (VEX_W_0FDE_P_2): Likewise.
295 (VEX_W_0FDF_P_2): Likewise.
296 (VEX_W_0FE0_P_2): Likewise.
297 (VEX_W_0FE1_P_2): Likewise.
298 (VEX_W_0FE2_P_2): Likewise.
299 (VEX_W_0FE3_P_2): Likewise.
300 (VEX_W_0FE4_P_2): Likewise.
301 (VEX_W_0FE5_P_2): Likewise.
302 (VEX_W_0FE6_P_1): Likewise.
303 (VEX_W_0FE6_P_2): Likewise.
304 (VEX_W_0FE6_P_3): Likewise.
305 (VEX_W_0FE7_P_2_M_0): Likewise.
306 (VEX_W_0FE8_P_2): Likewise.
307 (VEX_W_0FE9_P_2): Likewise.
308 (VEX_W_0FEA_P_2): Likewise.
309 (VEX_W_0FEB_P_2): Likewise.
310 (VEX_W_0FEC_P_2): Likewise.
311 (VEX_W_0FED_P_2): Likewise.
312 (VEX_W_0FEE_P_2): Likewise.
313 (VEX_W_0FEF_P_2): Likewise.
314 (VEX_W_0FF0_P_3_M_0): Likewise.
315 (VEX_W_0FF1_P_2): Likewise.
316 (VEX_W_0FF2_P_2): Likewise.
317 (VEX_W_0FF3_P_2): Likewise.
318 (VEX_W_0FF4_P_2): Likewise.
319 (VEX_W_0FF5_P_2): Likewise.
320 (VEX_W_0FF6_P_2): Likewise.
321 (VEX_W_0FF7_P_2): Likewise.
322 (VEX_W_0FF8_P_2): Likewise.
323 (VEX_W_0FF9_P_2): Likewise.
324 (VEX_W_0FFA_P_2): Likewise.
325 (VEX_W_0FFB_P_2): Likewise.
326 (VEX_W_0FFC_P_2): Likewise.
327 (VEX_W_0FFD_P_2): Likewise.
328 (VEX_W_0FFE_P_2): Likewise.
329 (VEX_W_0F3800_P_2): Likewise.
330 (VEX_W_0F3801_P_2): Likewise.
331 (VEX_W_0F3802_P_2): Likewise.
332 (VEX_W_0F3803_P_2): Likewise.
333 (VEX_W_0F3804_P_2): Likewise.
334 (VEX_W_0F3805_P_2): Likewise.
335 (VEX_W_0F3806_P_2): Likewise.
336 (VEX_W_0F3807_P_2): Likewise.
337 (VEX_W_0F3808_P_2): Likewise.
338 (VEX_W_0F3809_P_2): Likewise.
339 (VEX_W_0F380A_P_2): Likewise.
340 (VEX_W_0F380B_P_2): Likewise.
341 (VEX_W_0F3817_P_2): Likewise.
342 (VEX_W_0F381C_P_2): Likewise.
343 (VEX_W_0F381D_P_2): Likewise.
344 (VEX_W_0F381E_P_2): Likewise.
345 (VEX_W_0F3820_P_2): Likewise.
346 (VEX_W_0F3821_P_2): Likewise.
347 (VEX_W_0F3822_P_2): Likewise.
348 (VEX_W_0F3823_P_2): Likewise.
349 (VEX_W_0F3824_P_2): Likewise.
350 (VEX_W_0F3825_P_2): Likewise.
351 (VEX_W_0F3828_P_2): Likewise.
352 (VEX_W_0F3829_P_2): Likewise.
353 (VEX_W_0F382A_P_2_M_0): Likewise.
354 (VEX_W_0F382B_P_2): Likewise.
355 (VEX_W_0F3830_P_2): Likewise.
356 (VEX_W_0F3831_P_2): Likewise.
357 (VEX_W_0F3832_P_2): Likewise.
358 (VEX_W_0F3833_P_2): Likewise.
359 (VEX_W_0F3834_P_2): Likewise.
360 (VEX_W_0F3835_P_2): Likewise.
361 (VEX_W_0F3837_P_2): Likewise.
362 (VEX_W_0F3838_P_2): Likewise.
363 (VEX_W_0F3839_P_2): Likewise.
364 (VEX_W_0F383A_P_2): Likewise.
365 (VEX_W_0F383B_P_2): Likewise.
366 (VEX_W_0F383C_P_2): Likewise.
367 (VEX_W_0F383D_P_2): Likewise.
368 (VEX_W_0F383E_P_2): Likewise.
369 (VEX_W_0F383F_P_2): Likewise.
370 (VEX_W_0F3840_P_2): Likewise.
371 (VEX_W_0F3841_P_2): Likewise.
372 (VEX_W_0F38DB_P_2): Likewise.
373 (VEX_W_0F3A08_P_2): Likewise.
374 (VEX_W_0F3A09_P_2): Likewise.
375 (VEX_W_0F3A0A_P_2): Likewise.
376 (VEX_W_0F3A0B_P_2): Likewise.
377 (VEX_W_0F3A0C_P_2): Likewise.
378 (VEX_W_0F3A0D_P_2): Likewise.
379 (VEX_W_0F3A0E_P_2): Likewise.
380 (VEX_W_0F3A0F_P_2): Likewise.
381 (VEX_W_0F3A21_P_2): Likewise.
382 (VEX_W_0F3A40_P_2): Likewise.
383 (VEX_W_0F3A41_P_2): Likewise.
384 (VEX_W_0F3A42_P_2): Likewise.
385 (VEX_W_0F3A62_P_2): Likewise.
386 (VEX_W_0F3A63_P_2): Likewise.
387 (VEX_W_0F3ADF_P_2): Likewise.
388 (VEX_LEN_0F77_P_0): New.
389 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
390 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
391 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
392 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
393 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
394 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
395 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
396 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
397 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
398 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
399 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
400 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
401 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
402 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
403 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
404 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
405 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
406 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
407 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
408 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
409 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
410 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
411 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
412 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
413 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
414 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
415 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
416 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
417 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
418 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
419 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
420 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
421 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
422 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
423 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
424 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
425 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
426 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
427 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
428 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
429 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
430 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
431 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
432 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
433 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
434 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
435 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
436 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
437 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
438 (vex_table): Update VEX 0F28 and 0F29 entries.
439 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
440 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
441 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
442 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
443 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
444 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
445 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
446 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
447 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
448 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
449 VEX_LEN_0F3A0B_P_2 entries.
450 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
451 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
452 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
453 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
454 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
455 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
456 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
457 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
458 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
459 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
460 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
461 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
462 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
463 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
464 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
465 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
466 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
467 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
468 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
469 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
470 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
471 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
472 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
473 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
474 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
475 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
476 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
477 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
478 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
479 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
480 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
481 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
482 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
483 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
484 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
485 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
486 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
487 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
488 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
489 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
490 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
491 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
492 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
493 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
494 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
495 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
496 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
497 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
498 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
499 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
500 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
501 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
502 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
503 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
504 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
505 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
506 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
507 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
508 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
509 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
510 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
511 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
512 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
513 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
514 VEX_W_0F3ADF_P_2 entries.
515 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
516 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
517 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
519 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
521 * i386-opc.tbl (VexWIG): New.
522 Replace VexW=3 with VexWIG.
524 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
526 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
527 * i386-tbl.h: Regenerated.
529 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
532 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
533 VEX_LEN_0FD6_P_2 entries.
534 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
535 * i386-tbl.h: Regenerated.
537 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
540 * i386-opc.h (VEXWIG): New.
541 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
542 * i386-tbl.h: Regenerated.
544 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
547 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
548 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
549 * i386-dis.c (EXxEVexR64): New.
550 (evex_rounding_64_mode): Likewise.
551 (OP_Rounding): Handle evex_rounding_64_mode.
553 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
556 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
557 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
558 * i386-dis.c (Edqa): New.
559 (dqa_mode): Likewise.
560 (intel_operand_size): Handle dqa_mode as m_mode.
561 (OP_E_register): Handle dqa_mode as dq_mode.
562 (OP_E_memory): Set shift for dqa_mode based on address_mode.
564 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
566 * i386-dis.c (OP_E_memory): Reformat.
568 2018-09-14 Jan Beulich <jbeulich@suse.com>
570 * i386-opc.tbl (crc32): Fold byte and word forms.
571 * i386-tbl.h: Re-generate.
573 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
575 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
576 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
577 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
578 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
579 * i386-tbl.h: Regenerated.
581 2018-09-13 Jan Beulich <jbeulich@suse.com>
583 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
585 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
586 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
587 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
588 * i386-tbl.h: Re-generate.
590 2018-09-13 Jan Beulich <jbeulich@suse.com>
592 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
594 * i386-tbl.h: Re-generate.
596 2018-09-13 Jan Beulich <jbeulich@suse.com>
598 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
600 * i386-tbl.h: Re-generate.
602 2018-09-13 Jan Beulich <jbeulich@suse.com>
604 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
606 * i386-tbl.h: Re-generate.
608 2018-09-13 Jan Beulich <jbeulich@suse.com>
610 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
612 * i386-tbl.h: Re-generate.
614 2018-09-13 Jan Beulich <jbeulich@suse.com>
616 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
618 * i386-tbl.h: Re-generate.
620 2018-09-13 Jan Beulich <jbeulich@suse.com>
622 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
624 * i386-tbl.h: Re-generate.
626 2018-09-13 Jan Beulich <jbeulich@suse.com>
628 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
629 * i386-tbl.h: Re-generate.
631 2018-09-13 Jan Beulich <jbeulich@suse.com>
633 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
634 * i386-tbl.h: Re-generate.
636 2018-09-13 Jan Beulich <jbeulich@suse.com>
638 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
640 * i386-tbl.h: Re-generate.
642 2018-09-13 Jan Beulich <jbeulich@suse.com>
644 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
646 * i386-tbl.h: Re-generate.
648 2018-09-13 Jan Beulich <jbeulich@suse.com>
650 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
651 * i386-tbl.h: Re-generate.
653 2018-09-13 Jan Beulich <jbeulich@suse.com>
655 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
656 * i386-tbl.h: Re-generate.
658 2018-09-13 Jan Beulich <jbeulich@suse.com>
660 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
661 * i386-tbl.h: Re-generate.
663 2018-09-13 Jan Beulich <jbeulich@suse.com>
665 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
667 * i386-tbl.h: Re-generate.
669 2018-09-13 Jan Beulich <jbeulich@suse.com>
671 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
673 * i386-tbl.h: Re-generate.
675 2018-09-13 Jan Beulich <jbeulich@suse.com>
677 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
679 * i386-tbl.h: Re-generate.
681 2018-09-13 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
684 * i386-tbl.h: Re-generate.
686 2018-09-13 Jan Beulich <jbeulich@suse.com>
688 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
689 * i386-tbl.h: Re-generate.
691 2018-09-13 Jan Beulich <jbeulich@suse.com>
693 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
694 * i386-tbl.h: Re-generate.
696 2018-09-13 Jan Beulich <jbeulich@suse.com>
698 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
699 (vpbroadcastw, rdpid): Drop NoRex64.
700 * i386-tbl.h: Re-generate.
702 2018-09-13 Jan Beulich <jbeulich@suse.com>
704 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
705 store templates, adding D.
706 * i386-tbl.h: Re-generate.
708 2018-09-13 Jan Beulich <jbeulich@suse.com>
710 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
711 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
712 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
713 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
714 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
715 Fold load and store templates where possible, adding D. Drop
716 IgnoreSize where it was pointlessly present. Drop redundant
718 * i386-tbl.h: Re-generate.
720 2018-09-13 Jan Beulich <jbeulich@suse.com>
722 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
723 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
724 (intel_operand_size): Handle v_bndmk_mode.
725 (OP_E_memory): Likewise. Produce (bad) when also riprel.
727 2018-09-08 John Darrington <john@darrington.wattle.id.au>
729 * disassemble.c (ARCH_s12z): Define if ARCH_all.
731 2018-08-31 Kito Cheng <kito@andestech.com>
733 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
734 compressed floating point instructions.
736 2018-08-30 Kito Cheng <kito@andestech.com>
738 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
739 riscv_opcode.xlen_requirement.
740 * riscv-opc.c (riscv_opcodes): Update for struct change.
742 2018-08-29 Martin Aberg <maberg@gaisler.com>
744 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
745 psr (PWRPSR) instruction.
747 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
749 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
751 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
753 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
755 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
757 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
758 loongson3a as an alias of gs464 for compatibility.
759 * mips-opc.c (mips_opcodes): Change Comments.
761 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
763 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
765 (print_mips_disassembler_options): Document -M loongson-ext.
766 * mips-opc.c (LEXT2): New macro.
767 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
769 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
771 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
773 (parse_mips_ase_option): Handle -M loongson-ext option.
774 (print_mips_disassembler_options): Document -M loongson-ext.
775 * mips-opc.c (IL3A): Delete.
776 * mips-opc.c (LEXT): New macro.
777 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
780 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
782 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
784 (parse_mips_ase_option): Handle -M loongson-cam option.
785 (print_mips_disassembler_options): Document -M loongson-cam.
786 * mips-opc.c (LCAM): New macro.
787 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
790 2018-08-21 Alan Modra <amodra@gmail.com>
792 * ppc-dis.c (operand_value_powerpc): Init "invalid".
793 (skip_optional_operands): Count optional operands, and update
794 ppc_optional_operand_value call.
795 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
796 (extract_vlensi): Likewise.
797 (extract_fxm): Return default value for missing optional operand.
798 (extract_ls, extract_raq, extract_tbr): Likewise.
799 (insert_sxl, extract_sxl): New functions.
800 (insert_esync, extract_esync): Remove Power9 handling and simplify.
801 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
802 flag and extra entry.
803 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
806 2018-08-20 Alan Modra <amodra@gmail.com>
808 * sh-opc.h (MASK): Simplify.
810 2018-08-18 John Darrington <john@darrington.wattle.id.au>
812 * s12z-dis.c (bm_decode): Deal with cases where the mode is
813 BM_RESERVED0 or BM_RESERVED1
814 (bm_rel_decode, bm_n_bytes): Ditto.
816 2018-08-18 John Darrington <john@darrington.wattle.id.au>
820 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
822 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
823 address with the addr32 prefix and without base nor index
826 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
828 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
829 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
830 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
831 (cpu_flags): Add CpuCMOV and CpuFXSR.
832 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
833 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
834 * i386-init.h: Regenerated.
835 * i386-tbl.h: Likewise.
837 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
839 * arc-regs.h: Update auxiliary registers.
841 2018-08-06 Jan Beulich <jbeulich@suse.com>
843 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
844 (RegIP, RegIZ): Define.
845 * i386-reg.tbl: Adjust comments.
846 (rip): Use Qword instead of BaseIndex. Use RegIP.
847 (eip): Use Dword instead of BaseIndex. Use RegIP.
848 (riz): Add Qword. Use RegIZ.
849 (eiz): Add Dword. Use RegIZ.
850 * i386-tbl.h: Re-generate.
852 2018-08-03 Jan Beulich <jbeulich@suse.com>
854 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
855 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
856 vpmovzxdq, vpmovzxwd): Remove NoRex64.
857 * i386-tbl.h: Re-generate.
859 2018-08-03 Jan Beulich <jbeulich@suse.com>
861 * i386-gen.c (operand_types): Remove Mem field.
862 * i386-opc.h (union i386_operand_type): Remove mem field.
863 * i386-init.h, i386-tbl.h: Re-generate.
865 2018-08-01 Alan Modra <amodra@gmail.com>
867 * po/POTFILES.in: Regenerate.
869 2018-07-31 Nick Clifton <nickc@redhat.com>
871 * po/sv.po: Updated Swedish translation.
873 2018-07-31 Jan Beulich <jbeulich@suse.com>
875 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
876 * i386-init.h, i386-tbl.h: Re-generate.
878 2018-07-31 Jan Beulich <jbeulich@suse.com>
880 * i386-opc.h (ZEROING_MASKING) Rename to ...
881 (DYNAMIC_MASKING): ... this. Adjust comment.
882 * i386-opc.tbl (MaskingMorZ): Define.
883 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
884 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
885 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
886 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
887 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
888 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
889 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
890 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
891 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
893 2018-07-31 Jan Beulich <jbeulich@suse.com>
895 * i386-opc.tbl: Use element rather than vector size for AVX512*
896 scatter/gather insns.
897 * i386-tbl.h: Re-generate.
899 2018-07-31 Jan Beulich <jbeulich@suse.com>
901 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
902 (cpu_flags): Drop CpuVREX.
903 * i386-opc.h (CpuVREX): Delete.
904 (union i386_cpu_flags): Remove cpuvrex.
905 * i386-init.h, i386-tbl.h: Re-generate.
907 2018-07-30 Jim Wilson <jimw@sifive.com>
909 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
911 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
913 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
915 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
916 * Makefile.in: Regenerated.
917 * configure.ac: Add C-SKY.
918 * configure: Regenerated.
919 * csky-dis.c: New file.
920 * csky-opc.h: New file.
921 * disassemble.c (ARCH_csky): Define.
922 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
923 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
925 2018-07-27 Alan Modra <amodra@gmail.com>
927 * ppc-opc.c (insert_sprbat): Correct function parameter and
929 (extract_sprbat): Likewise, variable too.
931 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
932 Alan Modra <amodra@gmail.com>
934 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
935 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
936 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
937 support disjointed BAT.
938 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
939 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
940 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
942 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
943 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
945 * i386-gen.c (adjust_broadcast_modifier): New function.
946 (process_i386_opcode_modifier): Add an argument for operands.
947 Adjust the Broadcast value based on operands.
948 (output_i386_opcode): Pass operand_types to
949 process_i386_opcode_modifier.
950 (process_i386_opcodes): Pass NULL as operands to
951 process_i386_opcode_modifier.
952 * i386-opc.h (BYTE_BROADCAST): New.
953 (WORD_BROADCAST): Likewise.
954 (DWORD_BROADCAST): Likewise.
955 (QWORD_BROADCAST): Likewise.
956 (i386_opcode_modifier): Expand broadcast to 3 bits.
957 * i386-tbl.h: Regenerated.
959 2018-07-24 Alan Modra <amodra@gmail.com>
962 * or1k-desc.h: Regenerate.
964 2018-07-24 Jan Beulich <jbeulich@suse.com>
966 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
967 vcvtusi2ss, and vcvtusi2sd.
968 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
969 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
970 * i386-tbl.h: Re-generate.
972 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
974 * arc-opc.c (extract_w6): Fix extending the sign.
976 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
978 * arc-tbl.h (vewt): Allow it for ARC EM family.
980 2018-07-23 Alan Modra <amodra@gmail.com>
983 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
984 opcode variants for mtspr/mfspr encodings.
986 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
987 Maciej W. Rozycki <macro@mips.com>
989 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
990 loongson3a descriptors.
991 (parse_mips_ase_option): Handle -M loongson-mmi option.
992 (print_mips_disassembler_options): Document -M loongson-mmi.
993 * mips-opc.c (LMMI): New macro.
994 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
997 2018-07-19 Jan Beulich <jbeulich@suse.com>
999 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1000 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1001 IgnoreSize and [XYZ]MMword where applicable.
1002 * i386-tbl.h: Re-generate.
1004 2018-07-19 Jan Beulich <jbeulich@suse.com>
1006 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1007 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1008 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1009 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1010 * i386-tbl.h: Re-generate.
1012 2018-07-19 Jan Beulich <jbeulich@suse.com>
1014 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1015 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1016 VPCLMULQDQ templates into their respective AVX512VL counterparts
1017 where possible, using Disp8ShiftVL and CheckRegSize instead of
1018 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1019 * i386-tbl.h: Re-generate.
1021 2018-07-19 Jan Beulich <jbeulich@suse.com>
1023 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1024 AVX512VL counterparts where possible, using Disp8ShiftVL and
1025 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1026 IgnoreSize) as appropriate.
1027 * i386-tbl.h: Re-generate.
1029 2018-07-19 Jan Beulich <jbeulich@suse.com>
1031 * i386-opc.tbl: Fold AVX512BW templates into their respective
1032 AVX512VL counterparts where possible, using Disp8ShiftVL and
1033 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1034 IgnoreSize) as appropriate.
1035 * i386-tbl.h: Re-generate.
1037 2018-07-19 Jan Beulich <jbeulich@suse.com>
1039 * i386-opc.tbl: Fold AVX512CD templates into their respective
1040 AVX512VL counterparts where possible, using Disp8ShiftVL and
1041 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1042 IgnoreSize) as appropriate.
1043 * i386-tbl.h: Re-generate.
1045 2018-07-19 Jan Beulich <jbeulich@suse.com>
1047 * i386-opc.h (DISP8_SHIFT_VL): New.
1048 * i386-opc.tbl (Disp8ShiftVL): Define.
1049 (various): Fold AVX512VL templates into their respective
1050 AVX512F counterparts where possible, using Disp8ShiftVL and
1051 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1052 IgnoreSize) as appropriate.
1053 * i386-tbl.h: Re-generate.
1055 2018-07-19 Jan Beulich <jbeulich@suse.com>
1057 * Makefile.am: Change dependencies and rule for
1058 $(srcdir)/i386-init.h.
1059 * Makefile.in: Re-generate.
1060 * i386-gen.c (process_i386_opcodes): New local variable
1061 "marker". Drop opening of input file. Recognize marker and line
1063 * i386-opc.tbl (OPCODE_I386_H): Define.
1064 (i386-opc.h): Include it.
1067 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1070 * i386-opc.h (Byte): Update comments.
1076 (Xmmword): Likewise.
1077 (Ymmword): Likewise.
1078 (Zmmword): Likewise.
1079 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1081 * i386-tbl.h: Regenerated.
1083 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1085 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1086 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1087 * aarch64-asm-2.c: Regenerate.
1088 * aarch64-dis-2.c: Regenerate.
1089 * aarch64-opc-2.c: Regenerate.
1091 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1094 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1095 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1096 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1097 sqdmulh, sqrdmulh): Use Em16.
1099 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1101 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1102 csdb together with them.
1103 (thumb32_opcodes): Likewise.
1105 2018-07-11 Jan Beulich <jbeulich@suse.com>
1107 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1108 requiring 32-bit registers as operands 2 and 3. Improve
1110 (mwait, mwaitx): Fold templates. Improve comments.
1111 OPERAND_TYPE_INOUTPORTREG.
1112 * i386-tbl.h: Re-generate.
1114 2018-07-11 Jan Beulich <jbeulich@suse.com>
1116 * i386-gen.c (operand_type_init): Remove
1117 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1118 OPERAND_TYPE_INOUTPORTREG.
1119 * i386-init.h: Re-generate.
1121 2018-07-11 Jan Beulich <jbeulich@suse.com>
1123 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1124 (wrssq, wrussq): Add Qword.
1125 * i386-tbl.h: Re-generate.
1127 2018-07-11 Jan Beulich <jbeulich@suse.com>
1129 * i386-opc.h: Rename OTMax to OTNum.
1130 (OTNumOfUints): Adjust calculation.
1131 (OTUnused): Directly alias to OTNum.
1133 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1135 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1137 (lea_reg_xys): Likewise.
1138 (print_insn_loop_primitive): Rename `reg' local variable to
1141 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1144 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1146 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1149 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1150 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1152 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1155 * mips-dis.c (mips_option_arg_t): New enumeration.
1156 (mips_options): New variable.
1157 (disassembler_options_mips): New function.
1158 (print_mips_disassembler_options): Reimplement in terms of
1159 `disassembler_options_mips'.
1160 * arm-dis.c (disassembler_options_arm): Adapt to using the
1161 `disasm_options_and_args_t' structure.
1162 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1163 * s390-dis.c (disassembler_options_s390): Likewise.
1165 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1167 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1169 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1170 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1171 * testsuite/ld-arm/tls-longplt.d: Likewise.
1173 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1176 * aarch64-asm-2.c: Regenerate.
1177 * aarch64-dis-2.c: Likewise.
1178 * aarch64-opc-2.c: Likewise.
1179 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1180 * aarch64-opc.c (operand_general_constraint_met_p,
1181 aarch64_print_operand): Likewise.
1182 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1183 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1185 (AARCH64_OPERANDS): Add Em2.
1187 2018-06-26 Nick Clifton <nickc@redhat.com>
1189 * po/uk.po: Updated Ukranian translation.
1190 * po/de.po: Updated German translation.
1191 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1193 2018-06-26 Nick Clifton <nickc@redhat.com>
1195 * nfp-dis.c: Fix spelling mistake.
1197 2018-06-24 Nick Clifton <nickc@redhat.com>
1199 * configure: Regenerate.
1200 * po/opcodes.pot: Regenerate.
1202 2018-06-24 Nick Clifton <nickc@redhat.com>
1204 2.31 branch created.
1206 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1208 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1209 * aarch64-asm-2.c: Regenerate.
1210 * aarch64-dis-2.c: Likewise.
1212 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1214 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1215 `-M ginv' option description.
1217 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1220 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1223 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1225 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1226 * configure.ac: Remove AC_PREREQ.
1227 * Makefile.in: Re-generate.
1228 * aclocal.m4: Re-generate.
1229 * configure: Re-generate.
1231 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1233 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1234 mips64r6 descriptors.
1235 (parse_mips_ase_option): Handle -Mginv option.
1236 (print_mips_disassembler_options): Document -Mginv.
1237 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1239 (mips_opcodes): Define ginvi and ginvt.
1241 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1242 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1244 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1245 * mips-opc.c (CRC, CRC64): New macros.
1246 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1247 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1250 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1253 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1254 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1256 2018-06-06 Alan Modra <amodra@gmail.com>
1258 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1259 setjmp. Move init for some other vars later too.
1261 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1263 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1264 (dis_private): Add new fields for property section tracking.
1265 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1266 (xtensa_instruction_fits): New functions.
1267 (fetch_data): Bump minimal fetch size to 4.
1268 (print_insn_xtensa): Make struct dis_private static.
1269 Load and prepare property table on section change.
1270 Don't disassemble literals. Don't disassemble instructions that
1271 cross property table boundaries.
1273 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1275 * configure: Regenerated.
1277 2018-06-01 Jan Beulich <jbeulich@suse.com>
1279 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1280 * i386-tbl.h: Re-generate.
1282 2018-06-01 Jan Beulich <jbeulich@suse.com>
1284 * i386-opc.tbl (sldt, str): Add NoRex64.
1285 * i386-tbl.h: Re-generate.
1287 2018-06-01 Jan Beulich <jbeulich@suse.com>
1289 * i386-opc.tbl (invpcid): Add Oword.
1290 * i386-tbl.h: Re-generate.
1292 2018-06-01 Alan Modra <amodra@gmail.com>
1294 * sysdep.h (_bfd_error_handler): Don't declare.
1295 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1296 * rl78-decode.opc: Likewise.
1297 * msp430-decode.c: Regenerate.
1298 * rl78-decode.c: Regenerate.
1300 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1302 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1303 * i386-init.h : Regenerated.
1305 2018-05-25 Alan Modra <amodra@gmail.com>
1307 * Makefile.in: Regenerate.
1308 * po/POTFILES.in: Regenerate.
1310 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1312 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1313 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1314 (insert_bab, extract_bab, insert_btab, extract_btab,
1315 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1316 (BAT, BBA VBA RBS XB6S): Delete macros.
1317 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1318 (BB, BD, RBX, XC6): Update for new macros.
1319 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1320 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1321 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1322 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1324 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1326 * Makefile.am: Add support for s12z architecture.
1327 * configure.ac: Likewise.
1328 * disassemble.c: Likewise.
1329 * disassemble.h: Likewise.
1330 * Makefile.in: Regenerate.
1331 * configure: Regenerate.
1332 * s12z-dis.c: New file.
1335 2018-05-18 Alan Modra <amodra@gmail.com>
1337 * nfp-dis.c: Don't #include libbfd.h.
1338 (init_nfp3200_priv): Use bfd_get_section_contents.
1339 (nit_nfp6000_mecsr_sec): Likewise.
1341 2018-05-17 Nick Clifton <nickc@redhat.com>
1343 * po/zh_CN.po: Updated simplified Chinese translation.
1345 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1348 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1349 * aarch64-dis-2.c: Regenerate.
1351 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1354 * aarch64-asm.c (opintl.h): Include.
1355 (aarch64_ins_sysreg): Enforce read/write constraints.
1356 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1357 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1358 (F_REG_READ, F_REG_WRITE): New.
1359 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1360 AARCH64_OPND_SYSREG.
1361 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1362 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1363 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1364 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1365 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1366 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1367 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1368 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1369 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1370 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1371 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1372 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1373 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1374 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1375 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1376 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1377 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1379 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1382 * aarch64-dis.c (no_notes: New.
1383 (parse_aarch64_dis_option): Support notes.
1384 (aarch64_decode_insn, print_operands): Likewise.
1385 (print_aarch64_disassembler_options): Document notes.
1386 * aarch64-opc.c (aarch64_print_operand): Support notes.
1388 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1391 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1392 and take error struct.
1393 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1394 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1395 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1396 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1397 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1398 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1399 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1400 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1401 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1402 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1403 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1404 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1405 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1406 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1407 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1408 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1409 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1410 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1411 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1412 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1413 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1414 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1415 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1416 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1417 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1418 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1419 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1420 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1421 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1422 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1423 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1424 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1425 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1426 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1427 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1428 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1429 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1430 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1431 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1432 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1433 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1434 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1435 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1436 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1437 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1438 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1439 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1440 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1441 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1442 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1443 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1444 (determine_disassembling_preference, aarch64_decode_insn,
1445 print_insn_aarch64_word, print_insn_data): Take errors struct.
1446 (print_insn_aarch64): Use errors.
1447 * aarch64-asm-2.c: Regenerate.
1448 * aarch64-dis-2.c: Regenerate.
1449 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1450 boolean in aarch64_insert_operan.
1451 (print_operand_extractor): Likewise.
1452 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1454 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1456 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1458 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1460 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1462 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1464 * cr16-opc.c (cr16_instruction): Comment typo fix.
1465 * hppa-dis.c (print_insn_hppa): Likewise.
1467 2018-05-08 Jim Wilson <jimw@sifive.com>
1469 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1470 (match_c_slli64, match_srxi_as_c_srxi): New.
1471 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1472 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1473 <c.slli, c.srli, c.srai>: Use match_s_slli.
1474 <c.slli64, c.srli64, c.srai64>: New.
1476 2018-05-08 Alan Modra <amodra@gmail.com>
1478 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1479 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1480 partition opcode space for index lookup.
1482 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1484 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1485 <insn_length>: ...with this. Update usage.
1486 Remove duplicate call to *info->memory_error_func.
1488 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1489 H.J. Lu <hongjiu.lu@intel.com>
1491 * i386-dis.c (Gva): New.
1492 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1493 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1494 (prefix_table): New instructions (see prefix above).
1495 (mod_table): New instructions (see prefix above).
1496 (OP_G): Handle va_mode.
1497 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1498 CPU_MOVDIR64B_FLAGS.
1499 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1500 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1501 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1502 * i386-opc.tbl: Add movidir{i,64b}.
1503 * i386-init.h: Regenerated.
1504 * i386-tbl.h: Likewise.
1506 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1508 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1510 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1511 (AddrPrefixOpReg): This.
1512 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1513 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1515 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1517 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1518 (vle_num_opcodes): Likewise.
1519 (spe2_num_opcodes): Likewise.
1520 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1521 initialization loop.
1522 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1523 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1526 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1528 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1530 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1532 Makefile.am: Added nfp-dis.c.
1533 configure.ac: Added bfd_nfp_arch.
1534 disassemble.h: Added print_insn_nfp prototype.
1535 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1536 nfp-dis.c: New, for NFP support.
1537 po/POTFILES.in: Added nfp-dis.c to the list.
1538 Makefile.in: Regenerate.
1539 configure: Regenerate.
1541 2018-04-26 Jan Beulich <jbeulich@suse.com>
1543 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1544 templates into their base ones.
1545 * i386-tlb.h: Re-generate.
1547 2018-04-26 Jan Beulich <jbeulich@suse.com>
1549 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1550 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1551 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1552 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1553 * i386-init.h: Re-generate.
1555 2018-04-26 Jan Beulich <jbeulich@suse.com>
1557 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1558 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1559 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1560 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1562 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1564 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1566 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1567 cpuregzmm, and cpuregmask.
1568 * i386-init.h: Re-generate.
1569 * i386-tbl.h: Re-generate.
1571 2018-04-26 Jan Beulich <jbeulich@suse.com>
1573 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1574 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1575 * i386-init.h: Re-generate.
1577 2018-04-26 Jan Beulich <jbeulich@suse.com>
1579 * i386-gen.c (VexImmExt): Delete.
1580 * i386-opc.h (VexImmExt, veximmext): Delete.
1581 * i386-opc.tbl: Drop all VexImmExt uses.
1582 * i386-tlb.h: Re-generate.
1584 2018-04-25 Jan Beulich <jbeulich@suse.com>
1586 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1587 register-only forms.
1588 * i386-tlb.h: Re-generate.
1590 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1592 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1594 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1596 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1598 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1599 (cpu_flags): Add CpuCLDEMOTE.
1600 * i386-init.h: Regenerate.
1601 * i386-opc.h (enum): Add CpuCLDEMOTE,
1602 (i386_cpu_flags): Add cpucldemote.
1603 * i386-opc.tbl: Add cldemote.
1604 * i386-tbl.h: Regenerate.
1606 2018-04-16 Alan Modra <amodra@gmail.com>
1608 * Makefile.am: Remove sh5 and sh64 support.
1609 * configure.ac: Likewise.
1610 * disassemble.c: Likewise.
1611 * disassemble.h: Likewise.
1612 * sh-dis.c: Likewise.
1613 * sh64-dis.c: Delete.
1614 * sh64-opc.c: Delete.
1615 * sh64-opc.h: Delete.
1616 * Makefile.in: Regenerate.
1617 * configure: Regenerate.
1618 * po/POTFILES.in: Regenerate.
1620 2018-04-16 Alan Modra <amodra@gmail.com>
1622 * Makefile.am: Remove w65 support.
1623 * configure.ac: Likewise.
1624 * disassemble.c: Likewise.
1625 * disassemble.h: Likewise.
1626 * w65-dis.c: Delete.
1627 * w65-opc.h: Delete.
1628 * Makefile.in: Regenerate.
1629 * configure: Regenerate.
1630 * po/POTFILES.in: Regenerate.
1632 2018-04-16 Alan Modra <amodra@gmail.com>
1634 * configure.ac: Remove we32k support.
1635 * configure: Regenerate.
1637 2018-04-16 Alan Modra <amodra@gmail.com>
1639 * Makefile.am: Remove m88k support.
1640 * configure.ac: Likewise.
1641 * disassemble.c: Likewise.
1642 * disassemble.h: Likewise.
1643 * m88k-dis.c: Delete.
1644 * Makefile.in: Regenerate.
1645 * configure: Regenerate.
1646 * po/POTFILES.in: Regenerate.
1648 2018-04-16 Alan Modra <amodra@gmail.com>
1650 * Makefile.am: Remove i370 support.
1651 * configure.ac: Likewise.
1652 * disassemble.c: Likewise.
1653 * disassemble.h: Likewise.
1654 * i370-dis.c: Delete.
1655 * i370-opc.c: Delete.
1656 * Makefile.in: Regenerate.
1657 * configure: Regenerate.
1658 * po/POTFILES.in: Regenerate.
1660 2018-04-16 Alan Modra <amodra@gmail.com>
1662 * Makefile.am: Remove h8500 support.
1663 * configure.ac: Likewise.
1664 * disassemble.c: Likewise.
1665 * disassemble.h: Likewise.
1666 * h8500-dis.c: Delete.
1667 * h8500-opc.h: Delete.
1668 * Makefile.in: Regenerate.
1669 * configure: Regenerate.
1670 * po/POTFILES.in: Regenerate.
1672 2018-04-16 Alan Modra <amodra@gmail.com>
1674 * configure.ac: Remove tahoe support.
1675 * configure: Regenerate.
1677 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1679 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1681 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1683 * i386-tbl.h: Regenerated.
1685 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1687 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1688 PREFIX_MOD_1_0FAE_REG_6.
1690 (OP_E_register): Use va_mode.
1691 * i386-dis-evex.h (prefix_table):
1692 New instructions (see prefixes above).
1693 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1694 (cpu_flags): Likewise.
1695 * i386-opc.h (enum): Likewise.
1696 (i386_cpu_flags): Likewise.
1697 * i386-opc.tbl: Add umonitor, umwait, tpause.
1698 * i386-init.h: Regenerate.
1699 * i386-tbl.h: Likewise.
1701 2018-04-11 Alan Modra <amodra@gmail.com>
1703 * opcodes/i860-dis.c: Delete.
1704 * opcodes/i960-dis.c: Delete.
1705 * Makefile.am: Remove i860 and i960 support.
1706 * configure.ac: Likewise.
1707 * disassemble.c: Likewise.
1708 * disassemble.h: Likewise.
1709 * Makefile.in: Regenerate.
1710 * configure: Regenerate.
1711 * po/POTFILES.in: Regenerate.
1713 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1716 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1718 (print_insn): Clear vex instead of vex.evex.
1720 2018-04-04 Nick Clifton <nickc@redhat.com>
1722 * po/es.po: Updated Spanish translation.
1724 2018-03-28 Jan Beulich <jbeulich@suse.com>
1726 * i386-gen.c (opcode_modifiers): Delete VecESize.
1727 * i386-opc.h (VecESize): Delete.
1728 (struct i386_opcode_modifier): Delete vecesize.
1729 * i386-opc.tbl: Drop VecESize.
1730 * i386-tlb.h: Re-generate.
1732 2018-03-28 Jan Beulich <jbeulich@suse.com>
1734 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1735 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1736 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1737 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1738 * i386-tlb.h: Re-generate.
1740 2018-03-28 Jan Beulich <jbeulich@suse.com>
1742 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1744 * i386-tlb.h: Re-generate.
1746 2018-03-28 Jan Beulich <jbeulich@suse.com>
1748 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1749 (vex_len_table): Drop Y for vcvt*2si.
1750 (putop): Replace plain 'Y' handling by abort().
1752 2018-03-28 Nick Clifton <nickc@redhat.com>
1755 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1756 instructions with only a base address register.
1757 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1758 handle AARHC64_OPND_SVE_ADDR_R.
1759 (aarch64_print_operand): Likewise.
1760 * aarch64-asm-2.c: Regenerate.
1761 * aarch64_dis-2.c: Regenerate.
1762 * aarch64-opc-2.c: Regenerate.
1764 2018-03-22 Jan Beulich <jbeulich@suse.com>
1766 * i386-opc.tbl: Drop VecESize from register only insn forms and
1767 memory forms not allowing broadcast.
1768 * i386-tlb.h: Re-generate.
1770 2018-03-22 Jan Beulich <jbeulich@suse.com>
1772 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1773 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1774 sha256*): Drop Disp<N>.
1776 2018-03-22 Jan Beulich <jbeulich@suse.com>
1778 * i386-dis.c (EbndS, bnd_swap_mode): New.
1779 (prefix_table): Use EbndS.
1780 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1781 * i386-opc.tbl (bndmov): Move misplaced Load.
1782 * i386-tlb.h: Re-generate.
1784 2018-03-22 Jan Beulich <jbeulich@suse.com>
1786 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1787 templates allowing memory operands and folded ones for register
1789 * i386-tlb.h: Re-generate.
1791 2018-03-22 Jan Beulich <jbeulich@suse.com>
1793 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1794 256-bit templates. Drop redundant leftover Disp<N>.
1795 * i386-tlb.h: Re-generate.
1797 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1799 * riscv-opc.c (riscv_insn_types): New.
1801 2018-03-13 Nick Clifton <nickc@redhat.com>
1803 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1805 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1807 * i386-opc.tbl: Add Optimize to clr.
1808 * i386-tbl.h: Regenerated.
1810 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1812 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1813 * i386-opc.h (OldGcc): Removed.
1814 (i386_opcode_modifier): Remove oldgcc.
1815 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1816 instructions for old (<= 2.8.1) versions of gcc.
1817 * i386-tbl.h: Regenerated.
1819 2018-03-08 Jan Beulich <jbeulich@suse.com>
1821 * i386-opc.h (EVEXDYN): New.
1822 * i386-opc.tbl: Fold various AVX512VL templates.
1823 * i386-tlb.h: Re-generate.
1825 2018-03-08 Jan Beulich <jbeulich@suse.com>
1827 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1828 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1829 vpexpandd, vpexpandq): Fold AFX512VF templates.
1830 * i386-tlb.h: Re-generate.
1832 2018-03-08 Jan Beulich <jbeulich@suse.com>
1834 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1835 Fold 128- and 256-bit VEX-encoded templates.
1836 * i386-tlb.h: Re-generate.
1838 2018-03-08 Jan Beulich <jbeulich@suse.com>
1840 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1841 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1842 vpexpandd, vpexpandq): Fold AVX512F templates.
1843 * i386-tlb.h: Re-generate.
1845 2018-03-08 Jan Beulich <jbeulich@suse.com>
1847 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1848 64-bit templates. Drop Disp<N>.
1849 * i386-tlb.h: Re-generate.
1851 2018-03-08 Jan Beulich <jbeulich@suse.com>
1853 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1854 and 256-bit templates.
1855 * i386-tlb.h: Re-generate.
1857 2018-03-08 Jan Beulich <jbeulich@suse.com>
1859 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1860 * i386-tlb.h: Re-generate.
1862 2018-03-08 Jan Beulich <jbeulich@suse.com>
1864 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1866 * i386-tlb.h: Re-generate.
1868 2018-03-08 Jan Beulich <jbeulich@suse.com>
1870 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1871 * i386-tlb.h: Re-generate.
1873 2018-03-08 Jan Beulich <jbeulich@suse.com>
1875 * i386-gen.c (opcode_modifiers): Delete FloatD.
1876 * i386-opc.h (FloatD): Delete.
1877 (struct i386_opcode_modifier): Delete floatd.
1878 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1880 * i386-tlb.h: Re-generate.
1882 2018-03-08 Jan Beulich <jbeulich@suse.com>
1884 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1886 2018-03-08 Jan Beulich <jbeulich@suse.com>
1888 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1889 * i386-tlb.h: Re-generate.
1891 2018-03-08 Jan Beulich <jbeulich@suse.com>
1893 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1895 * i386-tlb.h: Re-generate.
1897 2018-03-07 Alan Modra <amodra@gmail.com>
1899 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1901 * disassemble.h (print_insn_rs6000): Delete.
1902 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1903 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1904 (print_insn_rs6000): Delete.
1906 2018-03-03 Alan Modra <amodra@gmail.com>
1908 * sysdep.h (opcodes_error_handler): Define.
1909 (_bfd_error_handler): Declare.
1910 * Makefile.am: Remove stray #.
1911 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1913 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1914 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1915 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1916 opcodes_error_handler to print errors. Standardize error messages.
1917 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1918 and include opintl.h.
1919 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1920 * i386-gen.c: Standardize error messages.
1921 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1922 * Makefile.in: Regenerate.
1923 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1924 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1925 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1926 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1927 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1928 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1929 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1930 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1931 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1932 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1933 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1934 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1935 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1937 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1939 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1940 vpsub[bwdq] instructions.
1941 * i386-tbl.h: Regenerated.
1943 2018-03-01 Alan Modra <amodra@gmail.com>
1945 * configure.ac (ALL_LINGUAS): Sort.
1946 * configure: Regenerate.
1948 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1950 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1951 macro by assignements.
1953 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1956 * i386-gen.c (opcode_modifiers): Add Optimize.
1957 * i386-opc.h (Optimize): New enum.
1958 (i386_opcode_modifier): Add optimize.
1959 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1960 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1961 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1962 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1963 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1965 * i386-tbl.h: Regenerated.
1967 2018-02-26 Alan Modra <amodra@gmail.com>
1969 * crx-dis.c (getregliststring): Allocate a large enough buffer
1970 to silence false positive gcc8 warning.
1972 2018-02-22 Shea Levy <shea@shealevy.com>
1974 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1976 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1978 * i386-opc.tbl: Add {rex},
1979 * i386-tbl.h: Regenerated.
1981 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1983 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1984 (mips16_opcodes): Replace `M' with `m' for "restore".
1986 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1988 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1990 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1992 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1993 variable to `function_index'.
1995 2018-02-13 Nick Clifton <nickc@redhat.com>
1998 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1999 about truncation of printing.
2001 2018-02-12 Henry Wong <henry@stuffedcow.net>
2003 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2005 2018-02-05 Nick Clifton <nickc@redhat.com>
2007 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2009 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2011 * i386-dis.c (enum): Add pconfig.
2012 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2013 (cpu_flags): Add CpuPCONFIG.
2014 * i386-opc.h (enum): Add CpuPCONFIG.
2015 (i386_cpu_flags): Add cpupconfig.
2016 * i386-opc.tbl: Add PCONFIG instruction.
2017 * i386-init.h: Regenerate.
2018 * i386-tbl.h: Likewise.
2020 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2022 * i386-dis.c (enum): Add PREFIX_0F09.
2023 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2024 (cpu_flags): Add CpuWBNOINVD.
2025 * i386-opc.h (enum): Add CpuWBNOINVD.
2026 (i386_cpu_flags): Add cpuwbnoinvd.
2027 * i386-opc.tbl: Add WBNOINVD instruction.
2028 * i386-init.h: Regenerate.
2029 * i386-tbl.h: Likewise.
2031 2018-01-17 Jim Wilson <jimw@sifive.com>
2033 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2035 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2037 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2038 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2039 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2040 (cpu_flags): Add CpuIBT, CpuSHSTK.
2041 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2042 (i386_cpu_flags): Add cpuibt, cpushstk.
2043 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2044 * i386-init.h: Regenerate.
2045 * i386-tbl.h: Likewise.
2047 2018-01-16 Nick Clifton <nickc@redhat.com>
2049 * po/pt_BR.po: Updated Brazilian Portugese translation.
2050 * po/de.po: Updated German translation.
2052 2018-01-15 Jim Wilson <jimw@sifive.com>
2054 * riscv-opc.c (match_c_nop): New.
2055 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2057 2018-01-15 Nick Clifton <nickc@redhat.com>
2059 * po/uk.po: Updated Ukranian translation.
2061 2018-01-13 Nick Clifton <nickc@redhat.com>
2063 * po/opcodes.pot: Regenerated.
2065 2018-01-13 Nick Clifton <nickc@redhat.com>
2067 * configure: Regenerate.
2069 2018-01-13 Nick Clifton <nickc@redhat.com>
2071 2.30 branch created.
2073 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2075 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2076 * i386-tbl.h: Regenerate.
2078 2018-01-10 Jan Beulich <jbeulich@suse.com>
2080 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2081 * i386-tbl.h: Re-generate.
2083 2018-01-10 Jan Beulich <jbeulich@suse.com>
2085 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2086 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2087 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2088 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2089 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2090 Disp8MemShift of AVX512VL forms.
2091 * i386-tbl.h: Re-generate.
2093 2018-01-09 Jim Wilson <jimw@sifive.com>
2095 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2096 then the hi_addr value is zero.
2098 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2100 * arm-dis.c (arm_opcodes): Add csdb.
2101 (thumb32_opcodes): Add csdb.
2103 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2105 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2106 * aarch64-asm-2.c: Regenerate.
2107 * aarch64-dis-2.c: Regenerate.
2108 * aarch64-opc-2.c: Regenerate.
2110 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2113 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2114 Remove AVX512 vmovd with 64-bit operands.
2115 * i386-tbl.h: Regenerated.
2117 2018-01-05 Jim Wilson <jimw@sifive.com>
2119 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2122 2018-01-03 Alan Modra <amodra@gmail.com>
2124 Update year range in copyright notice of all files.
2126 2018-01-02 Jan Beulich <jbeulich@suse.com>
2128 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2129 and OPERAND_TYPE_REGZMM entries.
2131 For older changes see ChangeLog-2017
2133 Copyright (C) 2018 Free Software Foundation, Inc.
2135 Copying and distribution of this file, with or without modification,
2136 are permitted in any medium without royalty provided the copyright
2137 notice and this notice are preserved.
2143 version-control: never