1 2019-06-27 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
4 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
5 VEX_LEN_0F2D_P_3): Delete.
6 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
7 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
8 (prefix_table): ... here.
10 2019-06-27 Jan Beulich <jbeulich@suse.com>
12 * i386-dis.c (Iq): Delete.
14 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
16 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
17 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
18 (OP_E_memory): Also honor needindex when deciding whether an
19 address size prefix needs printing.
20 (OP_I): Remove handling of q_mode. Add handling of d_mode.
22 2019-06-26 Jim Wilson <jimw@sifive.com>
25 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
26 Set info->display_endian to info->endian_code.
28 2019-06-25 Jan Beulich <jbeulich@suse.com>
30 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
31 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
32 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
33 OPERAND_TYPE_ACC64 entries.
34 * i386-init.h: Re-generate.
36 2019-06-25 Jan Beulich <jbeulich@suse.com>
38 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
40 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
42 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
44 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
45 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
47 2019-06-25 Jan Beulich <jbeulich@suse.com>
49 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
52 2019-06-25 Jan Beulich <jbeulich@suse.com>
54 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
55 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
57 * i386-opc.tbl (movnti): Add IgnoreSize.
58 * i386-tbl.h: Re-generate.
60 2019-06-25 Jan Beulich <jbeulich@suse.com>
62 * i386-opc.tbl (and): Mark Imm8S form for optimization.
63 * i386-tbl.h: Re-generate.
65 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
67 * i386-dis-evex.h: Break into ...
68 * i386-dis-evex-len.h: New file.
69 * i386-dis-evex-mod.h: Likewise.
70 * i386-dis-evex-prefix.h: Likewise.
71 * i386-dis-evex-reg.h: Likewise.
72 * i386-dis-evex-w.h: Likewise.
73 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
74 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
77 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
80 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
81 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
83 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
84 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
85 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
86 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
87 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
88 EVEX_LEN_0F385B_P_2_W_1.
89 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
90 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
91 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
92 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
93 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
94 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
95 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
96 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
97 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
98 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
100 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
103 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
104 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
105 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
106 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
107 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
108 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
109 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
110 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
111 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
112 EVEX_LEN_0F3A43_P_2_W_1.
113 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
114 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
115 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
116 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
117 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
118 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
119 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
120 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
121 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
122 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
123 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
124 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
126 2019-06-14 Nick Clifton <nickc@redhat.com>
128 * po/fr.po; Updated French translation.
130 2019-06-13 Stafford Horne <shorne@gmail.com>
132 * or1k-asm.c: Regenerated.
133 * or1k-desc.c: Regenerated.
134 * or1k-desc.h: Regenerated.
135 * or1k-dis.c: Regenerated.
136 * or1k-ibld.c: Regenerated.
137 * or1k-opc.c: Regenerated.
138 * or1k-opc.h: Regenerated.
139 * or1k-opinst.c: Regenerated.
141 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
143 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
145 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
148 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
149 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
150 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
151 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
152 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
153 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
154 EVEX_LEN_0F3A1B_P_2_W_1.
155 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
156 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
157 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
158 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
159 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
160 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
161 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
162 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
164 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
167 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
168 EVEX.vvvv when disassembling VEX and EVEX instructions.
169 (OP_VEX): Set vex.register_specifier to 0 after readding
170 vex.register_specifier.
171 (OP_Vex_2src_1): Likewise.
172 (OP_Vex_2src_2): Likewise.
173 (OP_LWP_E): Likewise.
174 (OP_EX_Vex): Don't check vex.register_specifier.
175 (OP_XMM_Vex): Likewise.
177 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
178 Lili Cui <lili.cui@intel.com>
180 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
181 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
183 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
184 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
185 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
186 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
187 (i386_cpu_flags): Add cpuavx512_vp2intersect.
188 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
189 * i386-init.h: Regenerated.
190 * i386-tbl.h: Likewise.
192 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
193 Lili Cui <lili.cui@intel.com>
195 * doc/c-i386.texi: Document enqcmd.
196 * testsuite/gas/i386/enqcmd-intel.d: New file.
197 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
198 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
199 * testsuite/gas/i386/enqcmd.d: Likewise.
200 * testsuite/gas/i386/enqcmd.s: Likewise.
201 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
202 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
203 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
204 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
205 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
206 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
207 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
210 2019-06-04 Alan Hayward <alan.hayward@arm.com>
212 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
214 2019-06-03 Alan Modra <amodra@gmail.com>
216 * ppc-dis.c (prefix_opcd_indices): Correct size.
218 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
221 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
223 * i386-tbl.h: Regenerated.
225 2019-05-24 Alan Modra <amodra@gmail.com>
227 * po/POTFILES.in: Regenerate.
229 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
230 Alan Modra <amodra@gmail.com>
232 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
233 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
234 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
235 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
236 XTOP>): Define and add entries.
237 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
238 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
239 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
240 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
242 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
243 Alan Modra <amodra@gmail.com>
245 * ppc-dis.c (ppc_opts): Add "future" entry.
246 (PREFIX_OPCD_SEGS): Define.
247 (prefix_opcd_indices): New array.
248 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
249 (lookup_prefix): New function.
250 (print_insn_powerpc): Handle 64-bit prefix instructions.
251 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
252 (PMRR, POWERXX): Define.
253 (prefix_opcodes): New instruction table.
254 (prefix_num_opcodes): New constant.
256 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
258 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
259 * configure: Regenerated.
260 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
262 (HFILES): Add bpf-desc.h and bpf-opc.h.
263 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
264 bpf-ibld.c and bpf-opc.c.
266 * Makefile.in: Regenerated.
267 * disassemble.c (ARCH_bpf): Define.
268 (disassembler): Add case for bfd_arch_bpf.
269 (disassemble_init_for_target): Likewise.
270 (enum epbf_isa_attr): Define.
271 * disassemble.h: extern print_insn_bpf.
272 * bpf-asm.c: Generated.
273 * bpf-opc.h: Likewise.
274 * bpf-opc.c: Likewise.
275 * bpf-ibld.c: Likewise.
276 * bpf-dis.c: Likewise.
277 * bpf-desc.h: Likewise.
278 * bpf-desc.c: Likewise.
280 2019-05-21 Sudakshina Das <sudi.das@arm.com>
282 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
283 and VMSR with the new operands.
285 2019-05-21 Sudakshina Das <sudi.das@arm.com>
287 * arm-dis.c (enum mve_instructions): New enum
288 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
290 (mve_opcodes): New instructions as above.
291 (is_mve_encoding_conflict): Add cases for csinc, csinv,
293 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
295 2019-05-21 Sudakshina Das <sudi.das@arm.com>
297 * arm-dis.c (emun mve_instructions): Updated for new instructions.
298 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
299 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
300 uqshl, urshrl and urshr.
301 (is_mve_okay_in_it): Add new instructions to TRUE list.
302 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
303 (print_insn_mve): Updated to accept new %j,
304 %<bitfield>m and %<bitfield>n patterns.
306 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
308 * mips-opc.c (mips_builtin_opcodes): Change source register
311 2019-05-20 Nick Clifton <nickc@redhat.com>
313 * po/fr.po: Updated French translation.
315 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
316 Michael Collison <michael.collison@arm.com>
318 * arm-dis.c (thumb32_opcodes): Add new instructions.
319 (enum mve_instructions): Likewise.
320 (enum mve_undefined): Add new reasons.
321 (is_mve_encoding_conflict): Handle new instructions.
322 (is_mve_undefined): Likewise.
323 (is_mve_unpredictable): Likewise.
324 (print_mve_undefined): Likewise.
325 (print_mve_size): Likewise.
327 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
328 Michael Collison <michael.collison@arm.com>
330 * arm-dis.c (thumb32_opcodes): Add new instructions.
331 (enum mve_instructions): Likewise.
332 (is_mve_encoding_conflict): Handle new instructions.
333 (is_mve_undefined): Likewise.
334 (is_mve_unpredictable): Likewise.
335 (print_mve_size): Likewise.
337 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
338 Michael Collison <michael.collison@arm.com>
340 * arm-dis.c (thumb32_opcodes): Add new instructions.
341 (enum mve_instructions): Likewise.
342 (is_mve_encoding_conflict): Likewise.
343 (is_mve_unpredictable): Likewise.
344 (print_mve_size): Likewise.
346 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
347 Michael Collison <michael.collison@arm.com>
349 * arm-dis.c (thumb32_opcodes): Add new instructions.
350 (enum mve_instructions): Likewise.
351 (is_mve_encoding_conflict): Handle new instructions.
352 (is_mve_undefined): Likewise.
353 (is_mve_unpredictable): Likewise.
354 (print_mve_size): Likewise.
356 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
357 Michael Collison <michael.collison@arm.com>
359 * arm-dis.c (thumb32_opcodes): Add new instructions.
360 (enum mve_instructions): Likewise.
361 (is_mve_encoding_conflict): Handle new instructions.
362 (is_mve_undefined): Likewise.
363 (is_mve_unpredictable): Likewise.
364 (print_mve_size): Likewise.
365 (print_insn_mve): Likewise.
367 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
368 Michael Collison <michael.collison@arm.com>
370 * arm-dis.c (thumb32_opcodes): Add new instructions.
371 (print_insn_thumb32): Handle new instructions.
373 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
374 Michael Collison <michael.collison@arm.com>
376 * arm-dis.c (enum mve_instructions): Add new instructions.
377 (enum mve_undefined): Add new reasons.
378 (is_mve_encoding_conflict): Handle new instructions.
379 (is_mve_undefined): Likewise.
380 (is_mve_unpredictable): Likewise.
381 (print_mve_undefined): Likewise.
382 (print_mve_size): Likewise.
383 (print_mve_shift_n): Likewise.
384 (print_insn_mve): Likewise.
386 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
387 Michael Collison <michael.collison@arm.com>
389 * arm-dis.c (enum mve_instructions): Add new instructions.
390 (is_mve_encoding_conflict): Handle new instructions.
391 (is_mve_unpredictable): Likewise.
392 (print_mve_rotate): Likewise.
393 (print_mve_size): Likewise.
394 (print_insn_mve): Likewise.
396 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
397 Michael Collison <michael.collison@arm.com>
399 * arm-dis.c (enum mve_instructions): Add new instructions.
400 (is_mve_encoding_conflict): Handle new instructions.
401 (is_mve_unpredictable): Likewise.
402 (print_mve_size): Likewise.
403 (print_insn_mve): Likewise.
405 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
406 Michael Collison <michael.collison@arm.com>
408 * arm-dis.c (enum mve_instructions): Add new instructions.
409 (enum mve_undefined): Add new reasons.
410 (is_mve_encoding_conflict): Handle new instructions.
411 (is_mve_undefined): Likewise.
412 (is_mve_unpredictable): Likewise.
413 (print_mve_undefined): Likewise.
414 (print_mve_size): Likewise.
415 (print_insn_mve): Likewise.
417 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
418 Michael Collison <michael.collison@arm.com>
420 * arm-dis.c (enum mve_instructions): Add new instructions.
421 (is_mve_encoding_conflict): Handle new instructions.
422 (is_mve_undefined): Likewise.
423 (is_mve_unpredictable): Likewise.
424 (print_mve_size): Likewise.
425 (print_insn_mve): Likewise.
427 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
428 Michael Collison <michael.collison@arm.com>
430 * arm-dis.c (enum mve_instructions): Add new instructions.
431 (enum mve_unpredictable): Add new reasons.
432 (enum mve_undefined): Likewise.
433 (is_mve_okay_in_it): Handle new isntructions.
434 (is_mve_encoding_conflict): Likewise.
435 (is_mve_undefined): Likewise.
436 (is_mve_unpredictable): Likewise.
437 (print_mve_vmov_index): Likewise.
438 (print_simd_imm8): Likewise.
439 (print_mve_undefined): Likewise.
440 (print_mve_unpredictable): Likewise.
441 (print_mve_size): Likewise.
442 (print_insn_mve): Likewise.
444 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
445 Michael Collison <michael.collison@arm.com>
447 * arm-dis.c (enum mve_instructions): Add new instructions.
448 (enum mve_unpredictable): Add new reasons.
449 (enum mve_undefined): Likewise.
450 (is_mve_encoding_conflict): Handle new instructions.
451 (is_mve_undefined): Likewise.
452 (is_mve_unpredictable): Likewise.
453 (print_mve_undefined): Likewise.
454 (print_mve_unpredictable): Likewise.
455 (print_mve_rounding_mode): Likewise.
456 (print_mve_vcvt_size): Likewise.
457 (print_mve_size): Likewise.
458 (print_insn_mve): Likewise.
460 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
461 Michael Collison <michael.collison@arm.com>
463 * arm-dis.c (enum mve_instructions): Add new instructions.
464 (enum mve_unpredictable): Add new reasons.
465 (enum mve_undefined): Likewise.
466 (is_mve_undefined): Handle new instructions.
467 (is_mve_unpredictable): Likewise.
468 (print_mve_undefined): Likewise.
469 (print_mve_unpredictable): Likewise.
470 (print_mve_size): Likewise.
471 (print_insn_mve): Likewise.
473 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
474 Michael Collison <michael.collison@arm.com>
476 * arm-dis.c (enum mve_instructions): Add new instructions.
477 (enum mve_undefined): Add new reasons.
478 (insns): Add new instructions.
479 (is_mve_encoding_conflict):
480 (print_mve_vld_str_addr): New print function.
481 (is_mve_undefined): Handle new instructions.
482 (is_mve_unpredictable): Likewise.
483 (print_mve_undefined): Likewise.
484 (print_mve_size): Likewise.
485 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
486 (print_insn_mve): Handle new operands.
488 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
489 Michael Collison <michael.collison@arm.com>
491 * arm-dis.c (enum mve_instructions): Add new instructions.
492 (enum mve_unpredictable): Add new reasons.
493 (is_mve_encoding_conflict): Handle new instructions.
494 (is_mve_unpredictable): Likewise.
495 (mve_opcodes): Add new instructions.
496 (print_mve_unpredictable): Handle new reasons.
497 (print_mve_register_blocks): New print function.
498 (print_mve_size): Handle new instructions.
499 (print_insn_mve): Likewise.
501 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
502 Michael Collison <michael.collison@arm.com>
504 * arm-dis.c (enum mve_instructions): Add new instructions.
505 (enum mve_unpredictable): Add new reasons.
506 (enum mve_undefined): Likewise.
507 (is_mve_encoding_conflict): Handle new instructions.
508 (is_mve_undefined): Likewise.
509 (is_mve_unpredictable): Likewise.
510 (coprocessor_opcodes): Move NEON VDUP from here...
511 (neon_opcodes): ... to here.
512 (mve_opcodes): Add new instructions.
513 (print_mve_undefined): Handle new reasons.
514 (print_mve_unpredictable): Likewise.
515 (print_mve_size): Handle new instructions.
516 (print_insn_neon): Handle vdup.
517 (print_insn_mve): Handle new operands.
519 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
520 Michael Collison <michael.collison@arm.com>
522 * arm-dis.c (enum mve_instructions): Add new instructions.
523 (enum mve_unpredictable): Add new values.
524 (mve_opcodes): Add new instructions.
525 (vec_condnames): New array with vector conditions.
526 (mve_predicatenames): New array with predicate suffixes.
527 (mve_vec_sizename): New array with vector sizes.
528 (enum vpt_pred_state): New enum with vector predication states.
529 (struct vpt_block): New struct type for vpt blocks.
530 (vpt_block_state): Global struct to keep track of state.
531 (mve_extract_pred_mask): New helper function.
532 (num_instructions_vpt_block): Likewise.
533 (mark_outside_vpt_block): Likewise.
534 (mark_inside_vpt_block): Likewise.
535 (invert_next_predicate_state): Likewise.
536 (update_next_predicate_state): Likewise.
537 (update_vpt_block_state): Likewise.
538 (is_vpt_instruction): Likewise.
539 (is_mve_encoding_conflict): Add entries for new instructions.
540 (is_mve_unpredictable): Likewise.
541 (print_mve_unpredictable): Handle new cases.
542 (print_instruction_predicate): Likewise.
543 (print_mve_size): New function.
544 (print_vec_condition): New function.
545 (print_insn_mve): Handle vpt blocks and new print operands.
547 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
549 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
550 8, 14 and 15 for Armv8.1-M Mainline.
552 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
553 Michael Collison <michael.collison@arm.com>
555 * arm-dis.c (enum mve_instructions): New enum.
556 (enum mve_unpredictable): Likewise.
557 (enum mve_undefined): Likewise.
558 (struct mopcode32): New struct.
559 (is_mve_okay_in_it): New function.
560 (is_mve_architecture): Likewise.
561 (arm_decode_field): Likewise.
562 (arm_decode_field_multiple): Likewise.
563 (is_mve_encoding_conflict): Likewise.
564 (is_mve_undefined): Likewise.
565 (is_mve_unpredictable): Likewise.
566 (print_mve_undefined): Likewise.
567 (print_mve_unpredictable): Likewise.
568 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
569 (print_insn_mve): New function.
570 (print_insn_thumb32): Handle MVE architecture.
571 (select_arm_features): Force thumb for Armv8.1-m Mainline.
573 2019-05-10 Nick Clifton <nickc@redhat.com>
576 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
577 end of the table prematurely.
579 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
581 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
584 2019-05-11 Alan Modra <amodra@gmail.com>
586 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
587 when -Mraw is in effect.
589 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
591 * aarch64-dis-2.c: Regenerate.
592 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
593 (OP_SVE_BBB): New variant set.
594 (OP_SVE_DDDD): New variant set.
595 (OP_SVE_HHH): New variant set.
596 (OP_SVE_HHHU): New variant set.
597 (OP_SVE_SSS): New variant set.
598 (OP_SVE_SSSU): New variant set.
599 (OP_SVE_SHH): New variant set.
600 (OP_SVE_SBBU): New variant set.
601 (OP_SVE_DSS): New variant set.
602 (OP_SVE_DHHU): New variant set.
603 (OP_SVE_VMV_HSD_BHS): New variant set.
604 (OP_SVE_VVU_HSD_BHS): New variant set.
605 (OP_SVE_VVVU_SD_BH): New variant set.
606 (OP_SVE_VVVU_BHSD): New variant set.
607 (OP_SVE_VVV_QHD_DBS): New variant set.
608 (OP_SVE_VVV_HSD_BHS): New variant set.
609 (OP_SVE_VVV_HSD_BHS2): New variant set.
610 (OP_SVE_VVV_BHS_HSD): New variant set.
611 (OP_SVE_VV_BHS_HSD): New variant set.
612 (OP_SVE_VVV_SD): New variant set.
613 (OP_SVE_VVU_BHS_HSD): New variant set.
614 (OP_SVE_VZVV_SD): New variant set.
615 (OP_SVE_VZVV_BH): New variant set.
616 (OP_SVE_VZV_SD): New variant set.
617 (aarch64_opcode_table): Add sve2 instructions.
619 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
621 * aarch64-asm-2.c: Regenerated.
622 * aarch64-dis-2.c: Regenerated.
623 * aarch64-opc-2.c: Regenerated.
624 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
625 for SVE_SHLIMM_UNPRED_22.
626 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
627 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
630 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
632 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
633 sve_size_tsz_bhs iclass encode.
634 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
635 sve_size_tsz_bhs iclass decode.
637 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
639 * aarch64-asm-2.c: Regenerated.
640 * aarch64-dis-2.c: Regenerated.
641 * aarch64-opc-2.c: Regenerated.
642 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
643 for SVE_Zm4_11_INDEX.
644 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
645 (fields): Handle SVE_i2h field.
646 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
647 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
649 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
651 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
652 sve_shift_tsz_bhsd iclass encode.
653 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
654 sve_shift_tsz_bhsd iclass decode.
656 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
658 * aarch64-asm-2.c: Regenerated.
659 * aarch64-dis-2.c: Regenerated.
660 * aarch64-opc-2.c: Regenerated.
661 * aarch64-asm.c (aarch64_ins_sve_shrimm):
662 (aarch64_encode_variant_using_iclass): Handle
663 sve_shift_tsz_hsd iclass encode.
664 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
665 sve_shift_tsz_hsd iclass decode.
666 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
667 for SVE_SHRIMM_UNPRED_22.
668 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
669 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
672 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
674 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
675 sve_size_013 iclass encode.
676 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
677 sve_size_013 iclass decode.
679 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
681 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
682 sve_size_bh iclass encode.
683 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
684 sve_size_bh iclass decode.
686 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
688 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
689 sve_size_sd2 iclass encode.
690 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
691 sve_size_sd2 iclass decode.
692 * aarch64-opc.c (fields): Handle SVE_sz2 field.
693 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
695 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
697 * aarch64-asm-2.c: Regenerated.
698 * aarch64-dis-2.c: Regenerated.
699 * aarch64-opc-2.c: Regenerated.
700 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
702 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
703 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
705 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
707 * aarch64-asm-2.c: Regenerated.
708 * aarch64-dis-2.c: Regenerated.
709 * aarch64-opc-2.c: Regenerated.
710 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
711 for SVE_Zm3_11_INDEX.
712 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
713 (fields): Handle SVE_i3l and SVE_i3h2 fields.
714 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
716 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
718 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
720 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
721 sve_size_hsd2 iclass encode.
722 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
723 sve_size_hsd2 iclass decode.
724 * aarch64-opc.c (fields): Handle SVE_size field.
725 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
727 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
729 * aarch64-asm-2.c: Regenerated.
730 * aarch64-dis-2.c: Regenerated.
731 * aarch64-opc-2.c: Regenerated.
732 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
734 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
735 (fields): Handle SVE_rot3 field.
736 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
737 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
739 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
741 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
744 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
747 (aarch64_feature_sve2, aarch64_feature_sve2aes,
748 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
749 aarch64_feature_sve2bitperm): New feature sets.
750 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
751 for feature set addresses.
752 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
753 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
755 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
756 Faraz Shahbazker <fshahbazker@wavecomp.com>
758 * mips-dis.c (mips_calculate_combination_ases): Add ISA
759 argument and set ASE_EVA_R6 appropriately.
760 (set_default_mips_dis_options): Pass ISA to above.
761 (parse_mips_dis_option): Likewise.
762 * mips-opc.c (EVAR6): New macro.
763 (mips_builtin_opcodes): Add llwpe, scwpe.
765 2019-05-01 Sudakshina Das <sudi.das@arm.com>
767 * aarch64-asm-2.c: Regenerated.
768 * aarch64-dis-2.c: Regenerated.
769 * aarch64-opc-2.c: Regenerated.
770 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
771 AARCH64_OPND_TME_UIMM16.
772 (aarch64_print_operand): Likewise.
773 * aarch64-tbl.h (QL_IMM_NIL): New.
776 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
778 2019-04-29 John Darrington <john@darrington.wattle.id.au>
780 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
782 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
783 Faraz Shahbazker <fshahbazker@wavecomp.com>
785 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
787 2019-04-24 John Darrington <john@darrington.wattle.id.au>
789 * s12z-opc.h: Add extern "C" bracketing to help
790 users who wish to use this interface in c++ code.
792 2019-04-24 John Darrington <john@darrington.wattle.id.au>
794 * s12z-opc.c (bm_decode): Handle bit map operations with the
797 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
799 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
800 specifier. Add entries for VLDR and VSTR of system registers.
801 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
802 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
803 of %J and %K format specifier.
805 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
807 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
808 Add new entries for VSCCLRM instruction.
809 (print_insn_coprocessor): Handle new %C format control code.
811 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
813 * arm-dis.c (enum isa): New enum.
814 (struct sopcode32): New structure.
815 (coprocessor_opcodes): change type of entries to struct sopcode32 and
816 set isa field of all current entries to ANY.
817 (print_insn_coprocessor): Change type of insn to struct sopcode32.
818 Only match an entry if its isa field allows the current mode.
820 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
822 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
824 (print_insn_thumb32): Add logic to print %n CLRM register list.
826 2019-04-15 Sudakshina Das <sudi.das@arm.com>
828 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
831 2019-04-15 Sudakshina Das <sudi.das@arm.com>
833 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
834 (print_insn_thumb32): Edit the switch case for %Z.
836 2019-04-15 Sudakshina Das <sudi.das@arm.com>
838 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
840 2019-04-15 Sudakshina Das <sudi.das@arm.com>
842 * arm-dis.c (thumb32_opcodes): New instruction bfl.
844 2019-04-15 Sudakshina Das <sudi.das@arm.com>
846 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
848 2019-04-15 Sudakshina Das <sudi.das@arm.com>
850 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
851 Arm register with r13 and r15 unpredictable.
852 (thumb32_opcodes): New instructions for bfx and bflx.
854 2019-04-15 Sudakshina Das <sudi.das@arm.com>
856 * arm-dis.c (thumb32_opcodes): New instructions for bf.
858 2019-04-15 Sudakshina Das <sudi.das@arm.com>
860 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
862 2019-04-15 Sudakshina Das <sudi.das@arm.com>
864 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
866 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
868 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
870 2019-04-12 John Darrington <john@darrington.wattle.id.au>
872 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
873 "optr". ("operator" is a reserved word in c++).
875 2019-04-11 Sudakshina Das <sudi.das@arm.com>
877 * aarch64-opc.c (aarch64_print_operand): Add case for
879 (verify_constraints): Likewise.
880 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
881 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
882 to accept Rt|SP as first operand.
883 (AARCH64_OPERANDS): Add new Rt_SP.
884 * aarch64-asm-2.c: Regenerated.
885 * aarch64-dis-2.c: Regenerated.
886 * aarch64-opc-2.c: Regenerated.
888 2019-04-11 Sudakshina Das <sudi.das@arm.com>
890 * aarch64-asm-2.c: Regenerated.
891 * aarch64-dis-2.c: Likewise.
892 * aarch64-opc-2.c: Likewise.
893 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
895 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
897 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
899 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
901 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
902 * i386-init.h: Regenerated.
904 2019-04-07 Alan Modra <amodra@gmail.com>
906 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
907 op_separator to control printing of spaces, comma and parens
908 rather than need_comma, need_paren and spaces vars.
910 2019-04-07 Alan Modra <amodra@gmail.com>
913 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
914 (print_insn_neon, print_insn_arm): Likewise.
916 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
918 * i386-dis-evex.h (evex_table): Updated to support BF16
920 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
921 and EVEX_W_0F3872_P_3.
922 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
923 (cpu_flags): Add bitfield for CpuAVX512_BF16.
924 * i386-opc.h (enum): Add CpuAVX512_BF16.
925 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
926 * i386-opc.tbl: Add AVX512 BF16 instructions.
927 * i386-init.h: Regenerated.
928 * i386-tbl.h: Likewise.
930 2019-04-05 Alan Modra <amodra@gmail.com>
932 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
933 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
934 to favour printing of "-" branch hint when using the "y" bit.
935 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
937 2019-04-05 Alan Modra <amodra@gmail.com>
939 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
940 opcode until first operand is output.
942 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
945 * ppc-opc.c (valid_bo_pre_v2): Add comments.
946 (valid_bo_post_v2): Add support for 'at' branch hints.
947 (insert_bo): Only error on branch on ctr.
948 (get_bo_hint_mask): New function.
949 (insert_boe): Add new 'branch_taken' formal argument. Add support
950 for inserting 'at' branch hints.
951 (extract_boe): Add new 'branch_taken' formal argument. Add support
952 for extracting 'at' branch hints.
953 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
954 (BOE): Delete operand.
955 (BOM, BOP): New operands.
957 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
958 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
959 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
960 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
961 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
962 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
963 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
964 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
965 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
966 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
967 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
968 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
969 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
970 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
971 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
972 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
973 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
974 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
975 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
976 bttarl+>: New extended mnemonics.
978 2019-03-28 Alan Modra <amodra@gmail.com>
981 * ppc-opc.c (BTF): Define.
982 (powerpc_opcodes): Use for mtfsb*.
983 * ppc-dis.c (print_insn_powerpc): Print fields with both
984 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
986 2019-03-25 Tamar Christina <tamar.christina@arm.com>
988 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
989 (mapping_symbol_for_insn): Implement new algorithm.
990 (print_insn): Remove duplicate code.
992 2019-03-25 Tamar Christina <tamar.christina@arm.com>
994 * aarch64-dis.c (print_insn_aarch64):
997 2019-03-25 Tamar Christina <tamar.christina@arm.com>
999 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1002 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1004 * aarch64-dis.c (last_stop_offset): New.
1005 (print_insn_aarch64): Use stop_offset.
1007 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1010 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1012 * i386-init.h: Regenerated.
1014 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1017 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1018 vmovdqu16, vmovdqu32 and vmovdqu64.
1019 * i386-tbl.h: Regenerated.
1021 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1023 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1024 from vstrszb, vstrszh, and vstrszf.
1026 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1028 * s390-opc.txt: Add instruction descriptions.
1030 2019-02-08 Jim Wilson <jimw@sifive.com>
1032 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1035 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1037 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1039 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1042 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1043 * aarch64-opc.c (verify_elem_sd): New.
1044 (fields): Add FLD_sz entr.
1045 * aarch64-tbl.h (_SIMD_INSN): New.
1046 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1047 fmulx scalar and vector by element isns.
1049 2019-02-07 Nick Clifton <nickc@redhat.com>
1051 * po/sv.po: Updated Swedish translation.
1053 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1055 * s390-mkopc.c (main): Accept arch13 as cpu string.
1056 * s390-opc.c: Add new instruction formats and instruction opcode
1058 * s390-opc.txt: Add new arch13 instructions.
1060 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1062 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1063 (aarch64_opcode): Change encoding for stg, stzg
1065 * aarch64-asm-2.c: Regenerated.
1066 * aarch64-dis-2.c: Regenerated.
1067 * aarch64-opc-2.c: Regenerated.
1069 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1071 * aarch64-asm-2.c: Regenerated.
1072 * aarch64-dis-2.c: Likewise.
1073 * aarch64-opc-2.c: Likewise.
1074 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1076 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1077 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1079 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1080 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1081 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1082 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1083 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1084 case for ldstgv_indexed.
1085 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1086 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1087 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1088 * aarch64-asm-2.c: Regenerated.
1089 * aarch64-dis-2.c: Regenerated.
1090 * aarch64-opc-2.c: Regenerated.
1092 2019-01-23 Nick Clifton <nickc@redhat.com>
1094 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1096 2019-01-21 Nick Clifton <nickc@redhat.com>
1098 * po/de.po: Updated German translation.
1099 * po/uk.po: Updated Ukranian translation.
1101 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1102 * mips-dis.c (mips_arch_choices): Fix typo in
1103 gs464, gs464e and gs264e descriptors.
1105 2019-01-19 Nick Clifton <nickc@redhat.com>
1107 * configure: Regenerate.
1108 * po/opcodes.pot: Regenerate.
1110 2018-06-24 Nick Clifton <nickc@redhat.com>
1112 2.32 branch created.
1114 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1116 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1118 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1121 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1123 * configure: Regenerate.
1125 2019-01-07 Alan Modra <amodra@gmail.com>
1127 * configure: Regenerate.
1128 * po/POTFILES.in: Regenerate.
1130 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1132 * s12z-opc.c: New file.
1133 * s12z-opc.h: New file.
1134 * s12z-dis.c: Removed all code not directly related to display
1135 of instructions. Used the interface provided by the new files
1137 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1138 * Makefile.in: Regenerate.
1139 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1140 * configure: Regenerate.
1142 2019-01-01 Alan Modra <amodra@gmail.com>
1144 Update year range in copyright notice of all files.
1146 For older changes see ChangeLog-2018
1148 Copyright (C) 2019 Free Software Foundation, Inc.
1150 Copying and distribution of this file, with or without modification,
1151 are permitted in any medium without royalty provided the copyright
1152 notice and this notice are preserved.
1158 version-control: never