opcodes/ChangeLog

   1 2019-10-09  Nick Clifton  <nickc@redhat.com>
   2
   3         PR 25041
   4         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
   5         instructions.
   6
   7 2019-10-07  Jan Beulich  <jbeulich@suse.com>
   8
   9         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
  10         (cmpsd): Likewise. Move EsSeg to other operand.
  11         * opcodes/i386-tbl.h: Re-generate.
  12
  13 2019-09-23  Alan Modra  <amodra@gmail.com>
  14
  15         * m68k-dis.c: Include cpu-m68k.h
  16
  17 2019-09-23  Alan Modra  <amodra@gmail.com>
  18
  19         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
  20         "elf/mips.h" earlier.
  21
  22 2018-09-20  Jan Beulich  <jbeulich@suse.com>
  23
  24         PR gas/25012
  25         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
  26         with SReg operand.
  27         * i386-tbl.h: Re-generate.
  28
  29 2019-09-18  Alan Modra  <amodra@gmail.com>
  30
  31         * arc-ext.c: Update throughout for bfd section macro changes.
  32
  33 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
  34
  35         * Makefile.in: Re-generate.
  36         * configure: Re-generate.
  37
  38 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
  39
  40         * riscv-opc.c (riscv_opcodes): Change subset field
  41         to insn_class field for all instructions.
  42         (riscv_insn_types): Likewise.
  43
  44 2019-09-16  Phil Blundell  <pb@pbcl.net>
  45
  46         * configure: Regenerated.
  47
  48 2019-09-10  Miod Vallat  <miod@online.fr>
  49
  50         PR 24982
  51         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
  52
  53 2019-09-09  Phil Blundell  <pb@pbcl.net>
  54
  55         binutils 2.33 branch created.
  56
  57 2019-09-03  Nick Clifton  <nickc@redhat.com>
  58
  59         PR 24961
  60         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
  61         greater than zero before indexing via (bufcnt -1).
  62
  63 2019-09-03  Nick Clifton  <nickc@redhat.com>
  64
  65         PR 24958
  66         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
  67         (MAX_SPEC_REG_NAME_LEN): Define.
  68         (struct mmix_dis_info): Use defined constants for array lengths.
  69         (get_reg_name): New function.
  70         (get_sprec_reg_name): New function.
  71         (print_insn_mmix): Use new functions.
  72
  73 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  74
  75         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
  76         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
  77         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
  78
  79 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
  80
  81         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
  82         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
  83         (aarch64_sys_reg_supported_p): Update checks for the above.
  84
  85 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  86
  87         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
  88         cases MVE_SQRSHRL and MVE_UQRSHLL.
  89         (print_insn_mve): Add case for specifier 'k' to check
  90         specific bit of the instruction.
  91
  92 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
  93
  94         PR 24854
  95         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
  96         encountering an unknown machine type.
  97         (print_insn_arc): Handle arc_insn_length returning 0.  In error
  98         cases return -1 rather than calling abort.
  99
 100 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 101
 102         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 103         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 104         IgnoreSize.
 105         * i386-tbl.h: Re-generate.
 106
 107 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 108
 109         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 110         instructions.
 111
 112 2019-07-30  Mel Chen <mel.chen@sifive.com>
 113
 114         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 115         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 116
 117         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 118         fscsr.
 119
 120 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 121
 122         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 123         and MPY class instructions.
 124         (parse_option): Add nps400 option.
 125         (print_arc_disassembler_options): Add nps400 info.
 126
 127 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 128
 129         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 130         (bspop): Likewise.
 131         (modapp): Likewise.
 132         * arc-opc.c (RAD_CHK): Add.
 133         * arc-tbl.h: Regenerate.
 134
 135 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 136
 137         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 138         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 139
 140 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 141
 142         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 143         instructions as UNPREDICTABLE.
 144
 145 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 146
 147         * bpf-desc.c: Regenerated.
 148
 149 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-gen.c (static_assert): Define.
 152         (main): Use it.
 153         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 154         (Opcode_Modifier_Num): ... this.
 155         (Mem): Delete.
 156
 157 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-gen.c (operand_types): Move RegMem ...
 160         (opcode_modifiers): ... here.
 161         * i386-opc.h (RegMem): Move to opcode modifer enum.
 162         (union i386_operand_type): Move regmem field ...
 163         (struct i386_opcode_modifier): ... here.
 164         * i386-opc.tbl (RegMem): Define.
 165         (mov, movq): Move RegMem on segment, control, debug, and test
 166         register flavors.
 167         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 168         to non-SSE2AVX flavor.
 169         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 170         Move RegMem on register only flavors. Drop IgnoreSize from
 171         legacy encoding flavors.
 172         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 173         flavors.
 174         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 175         register only flavors.
 176         (vmovd): Move RegMem and drop IgnoreSize on register only
 177         flavor. Change opcode and operand order to store form.
 178         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 179
 180 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 183         entries.
 184         * i386-opc.h (SReg2, SReg3): Replace by ...
 185         (SReg): ... this.
 186         (union i386_operand_type): Replace sreg fields.
 187         * i386-opc.tbl (mov, ): Use SReg.
 188         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 189         register flavors.
 190         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 191         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 192
 193 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 194
 195         * bpf-desc.c: Regenerate.
 196         * bpf-opc.c: Likewise.
 197         * bpf-opc.h: Likewise.
 198
 199 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 200
 201         * bpf-desc.c: Regenerate.
 202         * bpf-opc.c: Likewise.
 203
 204 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 205
 206         * arm-dis.c (print_insn_coprocessor): Rename index to
 207         index_operand.
 208
 209 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 210
 211         * riscv-opc.c (riscv_insn_types): Add r4 type.
 212
 213         * riscv-opc.c (riscv_insn_types): Add b and j type.
 214
 215         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 216         format for sb type and correct s type.
 217
 218 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 219
 220         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 221         SVE FMOV alias of FCPY.
 222
 223 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 224
 225         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 226         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 227
 228 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 229
 230         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 231         registers in an instruction prefixed by MOVPRFX.
 232
 233 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 234
 235         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 236         sve_size_13 icode to account for variant behaviour of
 237         pmull{t,b}.
 238         * aarch64-dis-2.c: Regenerate.
 239         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 240         sve_size_13 icode to account for variant behaviour of
 241         pmull{t,b}.
 242         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 243         (OP_SVE_VVV_Q_D): Add new qualifier.
 244         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 245         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 246         AES and those not.
 247
 248 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 249
 250         * opcodes/i386-gen.c (operand_type_init): Remove
 251         OPERAND_TYPE_VEC_IMM4 entry.
 252         (operand_types): Remove Vec_Imm4.
 253         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 254         (union i386_operand_type): Remove vec_imm4.
 255         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 256         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 257
 258 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 261         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 262         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 263         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 264         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 265         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 266         * i386-tbl.h: Re-generate.
 267
 268 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 269
 270         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 271         register operands.
 272         * i386-tbl.h: Re-generate.
 273
 274 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-opc.tbl (C): New.
 277         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 278         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 279         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 280         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 281         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 282         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 283         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 284         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 285         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 286         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 287         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 288         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 289         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 290         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 291         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 292         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 293         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 294         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 295         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 296         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 297         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 298         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 299         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 300         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 301         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 302         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 303         flavors.
 304         * i386-tbl.h: Re-generate.
 305
 306 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 309         register operands.
 310         * i386-tbl.h: Re-generate.
 311
 312 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 315         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 316         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 317         * i386-tbl.h: Re-generate.
 318
 319 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 322         Disp8MemShift from register only templates.
 323         * i386-tbl.h: Re-generate.
 324
 325 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 326
 327         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 328         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 329         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 330         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 331         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 332         EVEX_W_0F11_P_3_M_1): Delete.
 333         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 334         EVEX_W_0F11_P_3): New.
 335         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 336         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 337         MOD_EVEX_0F11_PREFIX_3 table entries.
 338         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 339         PREFIX_EVEX_0F11 table entries.
 340         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 341         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 342         EVEX_W_0F11_P_3_M_{0,1} table entries.
 343
 344 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 345
 346         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 347         Delete.
 348
 349 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 350
 351         PR binutils/24719
 352         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 353         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 354         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 355         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 356         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 357         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 358         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 359         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 360         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 361         PREFIX_EVEX_0F38C6_REG_6 entries.
 362         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 363         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 364         EVEX_W_0F38C7_R_6_P_2 entries.
 365         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 366         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 367         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 368         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 369         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 370         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 371         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 372
 373 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 376         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 377         VEX_LEN_0F2D_P_3): Delete.
 378         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 379         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 380         (prefix_table): ... here.
 381
 382 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-dis.c (Iq): Delete.
 385         (Id): New.
 386         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 387         TBM insns.
 388         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 389         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 390         (OP_E_memory): Also honor needindex when deciding whether an
 391         address size prefix needs printing.
 392         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 393
 394 2019-06-26  Jim Wilson  <jimw@sifive.com>
 395
 396         PR binutils/24739
 397         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 398         Set info->display_endian to info->endian_code.
 399
 400 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 401
 402         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 403         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 404         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 405         OPERAND_TYPE_ACC64 entries.
 406         * i386-init.h: Re-generate.
 407
 408 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 409
 410         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 411         Delete.
 412         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 413         of dqa_mode.
 414         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 415         entries here.
 416         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 417         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 418
 419 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 422         variables.
 423
 424 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 425
 426         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 427         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 428         movnti.
 429         * i386-opc.tbl (movnti): Add IgnoreSize.
 430         * i386-tbl.h: Re-generate.
 431
 432 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 433
 434         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 435         * i386-tbl.h: Re-generate.
 436
 437 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         * i386-dis-evex.h: Break into ...
 440         * i386-dis-evex-len.h: New file.
 441         * i386-dis-evex-mod.h: Likewise.
 442         * i386-dis-evex-prefix.h: Likewise.
 443         * i386-dis-evex-reg.h: Likewise.
 444         * i386-dis-evex-w.h: Likewise.
 445         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 446         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 447         i386-dis-evex-mod.h.
 448
 449 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 450
 451         PR binutils/24700
 452         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 453         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 454         EVEX_W_0F385B_P_2.
 455         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 456         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 457         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 458         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 459         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 460         EVEX_LEN_0F385B_P_2_W_1.
 461         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 462         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 463         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 464         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 465         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 466         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 467         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 468         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 469         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 470         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 471
 472 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 473
 474         PR binutils/24691
 475         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 476         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 477         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 478         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 479         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 480         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 481         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 482         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 483         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 484         EVEX_LEN_0F3A43_P_2_W_1.
 485         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 486         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 487         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 488         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 489         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 490         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 491         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 492         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 493         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 494         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 495         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 496         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 497
 498 2019-06-14  Nick Clifton  <nickc@redhat.com>
 499
 500         * po/fr.po; Updated French translation.
 501
 502 2019-06-13  Stafford Horne  <shorne@gmail.com>
 503
 504         * or1k-asm.c: Regenerated.
 505         * or1k-desc.c: Regenerated.
 506         * or1k-desc.h: Regenerated.
 507         * or1k-dis.c: Regenerated.
 508         * or1k-ibld.c: Regenerated.
 509         * or1k-opc.c: Regenerated.
 510         * or1k-opc.h: Regenerated.
 511         * or1k-opinst.c: Regenerated.
 512
 513 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 514
 515         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 516
 517 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 518
 519         PR binutils/24633
 520         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 521         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 522         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 523         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 524         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 525         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 526         EVEX_LEN_0F3A1B_P_2_W_1.
 527         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 528         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 529         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 530         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 531         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 532         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 533         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 534         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 535
 536 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 537
 538         PR binutils/24626
 539         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 540         EVEX.vvvv when disassembling VEX and EVEX instructions.
 541         (OP_VEX): Set vex.register_specifier to 0 after readding
 542         vex.register_specifier.
 543         (OP_Vex_2src_1): Likewise.
 544         (OP_Vex_2src_2): Likewise.
 545         (OP_LWP_E): Likewise.
 546         (OP_EX_Vex): Don't check vex.register_specifier.
 547         (OP_XMM_Vex): Likewise.
 548
 549 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 550             Lili Cui  <lili.cui@intel.com>
 551
 552         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 553         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 554         instructions.
 555         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 556         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 557         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 558         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 559         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 560         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 561         * i386-init.h: Regenerated.
 562         * i386-tbl.h: Likewise.
 563
 564 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 565             Lili Cui  <lili.cui@intel.com>
 566
 567         * doc/c-i386.texi: Document enqcmd.
 568         * testsuite/gas/i386/enqcmd-intel.d: New file.
 569         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 570         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 571         * testsuite/gas/i386/enqcmd.d: Likewise.
 572         * testsuite/gas/i386/enqcmd.s: Likewise.
 573         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 574         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 575         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 576         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 577         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 578         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 579         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 580         and x86-64-enqcmd.
 581
 582 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 583
 584         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 585
 586 2019-06-03  Alan Modra  <amodra@gmail.com>
 587
 588         * ppc-dis.c (prefix_opcd_indices): Correct size.
 589
 590 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 591
 592         PR gas/24625
 593         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 594         Disp8ShiftVL.
 595         * i386-tbl.h: Regenerated.
 596
 597 2019-05-24  Alan Modra  <amodra@gmail.com>
 598
 599         * po/POTFILES.in: Regenerate.
 600
 601 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 602             Alan Modra  <amodra@gmail.com>
 603
 604         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 605         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 606         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 607         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 608         XTOP>): Define and add entries.
 609         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 610         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 611         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 612         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 613
 614 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 615             Alan Modra  <amodra@gmail.com>
 616
 617         * ppc-dis.c (ppc_opts): Add "future" entry.
 618         (PREFIX_OPCD_SEGS): Define.
 619         (prefix_opcd_indices): New array.
 620         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 621         (lookup_prefix): New function.
 622         (print_insn_powerpc): Handle 64-bit prefix instructions.
 623         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 624         (PMRR, POWERXX): Define.
 625         (prefix_opcodes): New instruction table.
 626         (prefix_num_opcodes): New constant.
 627
 628 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 629
 630         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 631         * configure: Regenerated.
 632         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 633         and cpu/bpf.opc.
 634         (HFILES): Add bpf-desc.h and bpf-opc.h.
 635         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 636         bpf-ibld.c and bpf-opc.c.
 637         (BPF_DEPS): Define.
 638         * Makefile.in: Regenerated.
 639         * disassemble.c (ARCH_bpf): Define.
 640         (disassembler): Add case for bfd_arch_bpf.
 641         (disassemble_init_for_target): Likewise.
 642         (enum epbf_isa_attr): Define.
 643         * disassemble.h: extern print_insn_bpf.
 644         * bpf-asm.c: Generated.
 645         * bpf-opc.h: Likewise.
 646         * bpf-opc.c: Likewise.
 647         * bpf-ibld.c: Likewise.
 648         * bpf-dis.c: Likewise.
 649         * bpf-desc.h: Likewise.
 650         * bpf-desc.c: Likewise.
 651
 652 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 653
 654         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 655         and VMSR with the new operands.
 656
 657 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 658
 659         * arm-dis.c (enum mve_instructions): New enum
 660         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 661         and cneg.
 662         (mve_opcodes): New instructions as above.
 663         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 664         csneg and csel.
 665         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 666
 667 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 668
 669         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 670         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 671         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 672         uqshl, urshrl and urshr.
 673         (is_mve_okay_in_it): Add new instructions to TRUE list.
 674         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 675         (print_insn_mve): Updated to accept new %j,
 676         %<bitfield>m and %<bitfield>n patterns.
 677
 678 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 679
 680         * mips-opc.c (mips_builtin_opcodes): Change source register
 681         constraint for DAUI.
 682
 683 2019-05-20  Nick Clifton  <nickc@redhat.com>
 684
 685         * po/fr.po: Updated French translation.
 686
 687 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 688             Michael Collison <michael.collison@arm.com>
 689
 690         * arm-dis.c (thumb32_opcodes): Add new instructions.
 691         (enum mve_instructions): Likewise.
 692         (enum mve_undefined): Add new reasons.
 693         (is_mve_encoding_conflict): Handle new instructions.
 694         (is_mve_undefined): Likewise.
 695         (is_mve_unpredictable): Likewise.
 696         (print_mve_undefined): Likewise.
 697         (print_mve_size): Likewise.
 698
 699 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 700             Michael Collison <michael.collison@arm.com>
 701
 702         * arm-dis.c (thumb32_opcodes): Add new instructions.
 703         (enum mve_instructions): Likewise.
 704         (is_mve_encoding_conflict): Handle new instructions.
 705         (is_mve_undefined): Likewise.
 706         (is_mve_unpredictable): Likewise.
 707         (print_mve_size): Likewise.
 708
 709 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 710             Michael Collison <michael.collison@arm.com>
 711
 712         * arm-dis.c (thumb32_opcodes): Add new instructions.
 713         (enum mve_instructions): Likewise.
 714         (is_mve_encoding_conflict): Likewise.
 715         (is_mve_unpredictable): Likewise.
 716         (print_mve_size): Likewise.
 717
 718 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 719             Michael Collison <michael.collison@arm.com>
 720
 721         * arm-dis.c (thumb32_opcodes): Add new instructions.
 722         (enum mve_instructions): Likewise.
 723         (is_mve_encoding_conflict): Handle new instructions.
 724         (is_mve_undefined): Likewise.
 725         (is_mve_unpredictable): Likewise.
 726         (print_mve_size): Likewise.
 727
 728 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 729             Michael Collison <michael.collison@arm.com>
 730
 731         * arm-dis.c (thumb32_opcodes): Add new instructions.
 732         (enum mve_instructions): Likewise.
 733         (is_mve_encoding_conflict): Handle new instructions.
 734         (is_mve_undefined): Likewise.
 735         (is_mve_unpredictable): Likewise.
 736         (print_mve_size): Likewise.
 737         (print_insn_mve): Likewise.
 738
 739 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 740             Michael Collison <michael.collison@arm.com>
 741
 742         * arm-dis.c (thumb32_opcodes): Add new instructions.
 743         (print_insn_thumb32): Handle new instructions.
 744
 745 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 746             Michael Collison <michael.collison@arm.com>
 747
 748         * arm-dis.c (enum mve_instructions): Add new instructions.
 749         (enum mve_undefined): Add new reasons.
 750         (is_mve_encoding_conflict): Handle new instructions.
 751         (is_mve_undefined): Likewise.
 752         (is_mve_unpredictable): Likewise.
 753         (print_mve_undefined): Likewise.
 754         (print_mve_size): Likewise.
 755         (print_mve_shift_n): Likewise.
 756         (print_insn_mve): Likewise.
 757
 758 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 759             Michael Collison <michael.collison@arm.com>
 760
 761         * arm-dis.c (enum mve_instructions): Add new instructions.
 762         (is_mve_encoding_conflict): Handle new instructions.
 763         (is_mve_unpredictable): Likewise.
 764         (print_mve_rotate): Likewise.
 765         (print_mve_size): Likewise.
 766         (print_insn_mve): Likewise.
 767
 768 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 769             Michael Collison <michael.collison@arm.com>
 770
 771         * arm-dis.c (enum mve_instructions): Add new instructions.
 772         (is_mve_encoding_conflict): Handle new instructions.
 773         (is_mve_unpredictable): Likewise.
 774         (print_mve_size): Likewise.
 775         (print_insn_mve): Likewise.
 776
 777 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 778             Michael Collison <michael.collison@arm.com>
 779
 780         * arm-dis.c (enum mve_instructions): Add new instructions.
 781         (enum mve_undefined): Add new reasons.
 782         (is_mve_encoding_conflict): Handle new instructions.
 783         (is_mve_undefined): Likewise.
 784         (is_mve_unpredictable): Likewise.
 785         (print_mve_undefined): Likewise.
 786         (print_mve_size): Likewise.
 787         (print_insn_mve): Likewise.
 788
 789 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 790             Michael Collison <michael.collison@arm.com>
 791
 792         * arm-dis.c (enum mve_instructions): Add new instructions.
 793         (is_mve_encoding_conflict): Handle new instructions.
 794         (is_mve_undefined): Likewise.
 795         (is_mve_unpredictable): Likewise.
 796         (print_mve_size): Likewise.
 797         (print_insn_mve): Likewise.
 798
 799 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 800             Michael Collison <michael.collison@arm.com>
 801
 802         * arm-dis.c (enum mve_instructions): Add new instructions.
 803         (enum mve_unpredictable): Add new reasons.
 804         (enum mve_undefined): Likewise.
 805         (is_mve_okay_in_it): Handle new isntructions.
 806         (is_mve_encoding_conflict): Likewise.
 807         (is_mve_undefined): Likewise.
 808         (is_mve_unpredictable): Likewise.
 809         (print_mve_vmov_index): Likewise.
 810         (print_simd_imm8): Likewise.
 811         (print_mve_undefined): Likewise.
 812         (print_mve_unpredictable): Likewise.
 813         (print_mve_size): Likewise.
 814         (print_insn_mve): Likewise.
 815
 816 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 817             Michael Collison <michael.collison@arm.com>
 818
 819         * arm-dis.c (enum mve_instructions): Add new instructions.
 820         (enum mve_unpredictable): Add new reasons.
 821         (enum mve_undefined): Likewise.
 822         (is_mve_encoding_conflict): Handle new instructions.
 823         (is_mve_undefined): Likewise.
 824         (is_mve_unpredictable): Likewise.
 825         (print_mve_undefined): Likewise.
 826         (print_mve_unpredictable): Likewise.
 827         (print_mve_rounding_mode): Likewise.
 828         (print_mve_vcvt_size): Likewise.
 829         (print_mve_size): Likewise.
 830         (print_insn_mve): Likewise.
 831
 832 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 833             Michael Collison <michael.collison@arm.com>
 834
 835         * arm-dis.c (enum mve_instructions): Add new instructions.
 836         (enum mve_unpredictable): Add new reasons.
 837         (enum mve_undefined): Likewise.
 838         (is_mve_undefined): Handle new instructions.
 839         (is_mve_unpredictable): Likewise.
 840         (print_mve_undefined): Likewise.
 841         (print_mve_unpredictable): Likewise.
 842         (print_mve_size): Likewise.
 843         (print_insn_mve): Likewise.
 844
 845 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 846             Michael Collison <michael.collison@arm.com>
 847
 848         * arm-dis.c (enum mve_instructions): Add new instructions.
 849         (enum mve_undefined): Add new reasons.
 850         (insns): Add new instructions.
 851         (is_mve_encoding_conflict):
 852         (print_mve_vld_str_addr): New print function.
 853         (is_mve_undefined): Handle new instructions.
 854         (is_mve_unpredictable): Likewise.
 855         (print_mve_undefined): Likewise.
 856         (print_mve_size): Likewise.
 857         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 858         (print_insn_mve):  Handle new operands.
 859
 860 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 861             Michael Collison <michael.collison@arm.com>
 862
 863         * arm-dis.c (enum mve_instructions): Add new instructions.
 864         (enum mve_unpredictable): Add new reasons.
 865         (is_mve_encoding_conflict): Handle new instructions.
 866         (is_mve_unpredictable): Likewise.
 867         (mve_opcodes): Add new instructions.
 868         (print_mve_unpredictable): Handle new reasons.
 869         (print_mve_register_blocks): New print function.
 870         (print_mve_size): Handle new instructions.
 871         (print_insn_mve): Likewise.
 872
 873 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 874             Michael Collison <michael.collison@arm.com>
 875
 876         * arm-dis.c (enum mve_instructions): Add new instructions.
 877         (enum mve_unpredictable): Add new reasons.
 878         (enum mve_undefined): Likewise.
 879         (is_mve_encoding_conflict): Handle new instructions.
 880         (is_mve_undefined): Likewise.
 881         (is_mve_unpredictable): Likewise.
 882         (coprocessor_opcodes): Move NEON VDUP from here...
 883         (neon_opcodes): ... to here.
 884         (mve_opcodes): Add new instructions.
 885         (print_mve_undefined):  Handle new reasons.
 886         (print_mve_unpredictable): Likewise.
 887         (print_mve_size): Handle new instructions.
 888         (print_insn_neon): Handle vdup.
 889         (print_insn_mve): Handle new operands.
 890
 891 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 892             Michael Collison <michael.collison@arm.com>
 893
 894         * arm-dis.c (enum mve_instructions): Add new instructions.
 895         (enum mve_unpredictable): Add new values.
 896         (mve_opcodes): Add new instructions.
 897         (vec_condnames): New array with vector conditions.
 898         (mve_predicatenames): New array with predicate suffixes.
 899         (mve_vec_sizename): New array with vector sizes.
 900         (enum vpt_pred_state): New enum with vector predication states.
 901         (struct vpt_block): New struct type for vpt blocks.
 902         (vpt_block_state): Global struct to keep track of state.
 903         (mve_extract_pred_mask): New helper function.
 904         (num_instructions_vpt_block): Likewise.
 905         (mark_outside_vpt_block): Likewise.
 906         (mark_inside_vpt_block): Likewise.
 907         (invert_next_predicate_state): Likewise.
 908         (update_next_predicate_state): Likewise.
 909         (update_vpt_block_state): Likewise.
 910         (is_vpt_instruction): Likewise.
 911         (is_mve_encoding_conflict): Add entries for new instructions.
 912         (is_mve_unpredictable): Likewise.
 913         (print_mve_unpredictable): Handle new cases.
 914         (print_instruction_predicate): Likewise.
 915         (print_mve_size): New function.
 916         (print_vec_condition): New function.
 917         (print_insn_mve): Handle vpt blocks and new print operands.
 918
 919 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 920
 921         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 922         8, 14 and 15 for Armv8.1-M Mainline.
 923
 924 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 925             Michael Collison <michael.collison@arm.com>
 926
 927         * arm-dis.c (enum mve_instructions): New enum.
 928         (enum mve_unpredictable): Likewise.
 929         (enum mve_undefined): Likewise.
 930         (struct mopcode32): New struct.
 931         (is_mve_okay_in_it): New function.
 932         (is_mve_architecture): Likewise.
 933         (arm_decode_field): Likewise.
 934         (arm_decode_field_multiple): Likewise.
 935         (is_mve_encoding_conflict): Likewise.
 936         (is_mve_undefined): Likewise.
 937         (is_mve_unpredictable): Likewise.
 938         (print_mve_undefined): Likewise.
 939         (print_mve_unpredictable): Likewise.
 940         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 941         (print_insn_mve): New function.
 942         (print_insn_thumb32): Handle MVE architecture.
 943         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 944
 945 2019-05-10  Nick Clifton  <nickc@redhat.com>
 946
 947         PR 24538
 948         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 949         end of the table prematurely.
 950
 951 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 952
 953         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 954         macros for R6.
 955
 956 2019-05-11  Alan Modra  <amodra@gmail.com>
 957
 958         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 959         when -Mraw is in effect.
 960
 961 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 962
 963         * aarch64-dis-2.c: Regenerate.
 964         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 965         (OP_SVE_BBB): New variant set.
 966         (OP_SVE_DDDD): New variant set.
 967         (OP_SVE_HHH): New variant set.
 968         (OP_SVE_HHHU): New variant set.
 969         (OP_SVE_SSS): New variant set.
 970         (OP_SVE_SSSU): New variant set.
 971         (OP_SVE_SHH): New variant set.
 972         (OP_SVE_SBBU): New variant set.
 973         (OP_SVE_DSS): New variant set.
 974         (OP_SVE_DHHU): New variant set.
 975         (OP_SVE_VMV_HSD_BHS): New variant set.
 976         (OP_SVE_VVU_HSD_BHS): New variant set.
 977         (OP_SVE_VVVU_SD_BH): New variant set.
 978         (OP_SVE_VVVU_BHSD): New variant set.
 979         (OP_SVE_VVV_QHD_DBS): New variant set.
 980         (OP_SVE_VVV_HSD_BHS): New variant set.
 981         (OP_SVE_VVV_HSD_BHS2): New variant set.
 982         (OP_SVE_VVV_BHS_HSD): New variant set.
 983         (OP_SVE_VV_BHS_HSD): New variant set.
 984         (OP_SVE_VVV_SD): New variant set.
 985         (OP_SVE_VVU_BHS_HSD): New variant set.
 986         (OP_SVE_VZVV_SD): New variant set.
 987         (OP_SVE_VZVV_BH): New variant set.
 988         (OP_SVE_VZV_SD): New variant set.
 989         (aarch64_opcode_table): Add sve2 instructions.
 990
 991 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 992
 993         * aarch64-asm-2.c: Regenerated.
 994         * aarch64-dis-2.c: Regenerated.
 995         * aarch64-opc-2.c: Regenerated.
 996         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 997         for SVE_SHLIMM_UNPRED_22.
 998         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 999         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1000         operand.
1001
1002 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1003
1004         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1005         sve_size_tsz_bhs iclass encode.
1006         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1007         sve_size_tsz_bhs iclass decode.
1008
1009 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1010
1011         * aarch64-asm-2.c: Regenerated.
1012         * aarch64-dis-2.c: Regenerated.
1013         * aarch64-opc-2.c: Regenerated.
1014         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1015         for SVE_Zm4_11_INDEX.
1016         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1017         (fields): Handle SVE_i2h field.
1018         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1019         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1020
1021 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1022
1023         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1024         sve_shift_tsz_bhsd iclass encode.
1025         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1026         sve_shift_tsz_bhsd iclass decode.
1027
1028 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1029
1030         * aarch64-asm-2.c: Regenerated.
1031         * aarch64-dis-2.c: Regenerated.
1032         * aarch64-opc-2.c: Regenerated.
1033         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1034         (aarch64_encode_variant_using_iclass): Handle
1035         sve_shift_tsz_hsd iclass encode.
1036         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1037         sve_shift_tsz_hsd iclass decode.
1038         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1039         for SVE_SHRIMM_UNPRED_22.
1040         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1041         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1042         operand.
1043
1044 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1045
1046         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1047         sve_size_013 iclass encode.
1048         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1049         sve_size_013 iclass decode.
1050
1051 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1052
1053         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1054         sve_size_bh iclass encode.
1055         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1056         sve_size_bh iclass decode.
1057
1058 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1059
1060         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1061         sve_size_sd2 iclass encode.
1062         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1063         sve_size_sd2 iclass decode.
1064         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1065         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1066
1067 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1068
1069         * aarch64-asm-2.c: Regenerated.
1070         * aarch64-dis-2.c: Regenerated.
1071         * aarch64-opc-2.c: Regenerated.
1072         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1073         for SVE_ADDR_ZX.
1074         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1075         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1076
1077 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1078
1079         * aarch64-asm-2.c: Regenerated.
1080         * aarch64-dis-2.c: Regenerated.
1081         * aarch64-opc-2.c: Regenerated.
1082         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1083         for SVE_Zm3_11_INDEX.
1084         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1085         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1086         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1087         fields.
1088         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1089
1090 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1091
1092         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1093         sve_size_hsd2 iclass encode.
1094         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1095         sve_size_hsd2 iclass decode.
1096         * aarch64-opc.c (fields): Handle SVE_size field.
1097         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1098
1099 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1100
1101         * aarch64-asm-2.c: Regenerated.
1102         * aarch64-dis-2.c: Regenerated.
1103         * aarch64-opc-2.c: Regenerated.
1104         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1105         for SVE_IMM_ROT3.
1106         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1107         (fields): Handle SVE_rot3 field.
1108         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1109         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1110
1111 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1112
1113         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1114         instructions.
1115
1116 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1117
1118         * aarch64-tbl.h
1119         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1120         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1121         aarch64_feature_sve2bitperm): New feature sets.
1122         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1123         for feature set addresses.
1124         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1125         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1126
1127 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1128             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1129
1130         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1131         argument and set ASE_EVA_R6 appropriately.
1132         (set_default_mips_dis_options): Pass ISA to above.
1133         (parse_mips_dis_option): Likewise.
1134         * mips-opc.c (EVAR6): New macro.
1135         (mips_builtin_opcodes): Add llwpe, scwpe.
1136
1137 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1138
1139         * aarch64-asm-2.c: Regenerated.
1140         * aarch64-dis-2.c: Regenerated.
1141         * aarch64-opc-2.c: Regenerated.
1142         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1143         AARCH64_OPND_TME_UIMM16.
1144         (aarch64_print_operand): Likewise.
1145         * aarch64-tbl.h (QL_IMM_NIL): New.
1146         (TME): New.
1147         (_TME_INSN): New.
1148         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1149
1150 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1151
1152         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1153
1154 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1155             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1156
1157         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1158
1159 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1160
1161         * s12z-opc.h: Add extern "C" bracketing to help
1162         users who wish to use this interface in c++ code.
1163
1164 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1165
1166         * s12z-opc.c (bm_decode): Handle bit map operations with the
1167         "reserved0" mode.
1168
1169 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1170
1171         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1172         specifier.  Add entries for VLDR and VSTR of system registers.
1173         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1174         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1175         of %J and %K format specifier.
1176
1177 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1178
1179         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1180         Add new entries for VSCCLRM instruction.
1181         (print_insn_coprocessor): Handle new %C format control code.
1182
1183 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1184
1185         * arm-dis.c (enum isa): New enum.
1186         (struct sopcode32): New structure.
1187         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1188         set isa field of all current entries to ANY.
1189         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1190         Only match an entry if its isa field allows the current mode.
1191
1192 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1193
1194         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1195         CLRM.
1196         (print_insn_thumb32): Add logic to print %n CLRM register list.
1197
1198 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1199
1200         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1201         and %Q patterns.
1202
1203 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1204
1205         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1206         (print_insn_thumb32): Edit the switch case for %Z.
1207
1208 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1209
1210         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1211
1212 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1213
1214         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1215
1216 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1217
1218         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1219
1220 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1221
1222         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1223         Arm register with r13 and r15 unpredictable.
1224         (thumb32_opcodes): New instructions for bfx and bflx.
1225
1226 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1227
1228         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1229
1230 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1231
1232         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1233
1234 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1235
1236         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1237
1238 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1239
1240         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1241
1242 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1243
1244         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1245         "optr". ("operator" is a reserved word in c++).
1246
1247 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1248
1249         * aarch64-opc.c (aarch64_print_operand): Add case for
1250         AARCH64_OPND_Rt_SP.
1251         (verify_constraints): Likewise.
1252         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1253         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1254         to accept Rt|SP as first operand.
1255         (AARCH64_OPERANDS): Add new Rt_SP.
1256         * aarch64-asm-2.c: Regenerated.
1257         * aarch64-dis-2.c: Regenerated.
1258         * aarch64-opc-2.c: Regenerated.
1259
1260 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1261
1262         * aarch64-asm-2.c: Regenerated.
1263         * aarch64-dis-2.c: Likewise.
1264         * aarch64-opc-2.c: Likewise.
1265         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1266
1267 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1268
1269         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1270
1271 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1272
1273         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1274         * i386-init.h: Regenerated.
1275
1276 2019-04-07  Alan Modra  <amodra@gmail.com>
1277
1278         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1279         op_separator to control printing of spaces, comma and parens
1280         rather than need_comma, need_paren and spaces vars.
1281
1282 2019-04-07  Alan Modra  <amodra@gmail.com>
1283
1284         PR 24421
1285         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1286         (print_insn_neon, print_insn_arm): Likewise.
1287
1288 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1289
1290         * i386-dis-evex.h (evex_table): Updated to support BF16
1291         instructions.
1292         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1293         and EVEX_W_0F3872_P_3.
1294         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1295         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1296         * i386-opc.h (enum): Add CpuAVX512_BF16.
1297         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1298         * i386-opc.tbl: Add AVX512 BF16 instructions.
1299         * i386-init.h: Regenerated.
1300         * i386-tbl.h: Likewise.
1301
1302 2019-04-05  Alan Modra  <amodra@gmail.com>
1303
1304         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1305         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1306         to favour printing of "-" branch hint when using the "y" bit.
1307         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1308
1309 2019-04-05  Alan Modra  <amodra@gmail.com>
1310
1311         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1312         opcode until first operand is output.
1313
1314 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1315
1316         PR gas/24349
1317         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1318         (valid_bo_post_v2): Add support for 'at' branch hints.
1319         (insert_bo): Only error on branch on ctr.
1320         (get_bo_hint_mask): New function.
1321         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1322         for inserting 'at' branch hints.
1323         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1324         for extracting 'at' branch hints.
1325         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1326         (BOE): Delete operand.
1327         (BOM, BOP): New operands.
1328         (RM): Update value.
1329         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1330         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1331         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1332         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1333         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1334         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1335         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1336         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1337         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1338         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1339         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1340         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1341         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1342         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1343         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1344         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1345         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1346         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1347         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1348         bttarl+>: New extended mnemonics.
1349
1350 2019-03-28  Alan Modra  <amodra@gmail.com>
1351
1352         PR 24390
1353         * ppc-opc.c (BTF): Define.
1354         (powerpc_opcodes): Use for mtfsb*.
1355         * ppc-dis.c (print_insn_powerpc): Print fields with both
1356         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1357
1358 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1359
1360         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1361         (mapping_symbol_for_insn): Implement new algorithm.
1362         (print_insn): Remove duplicate code.
1363
1364 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1365
1366         * aarch64-dis.c (print_insn_aarch64):
1367         Implement override.
1368
1369 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1370
1371         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1372         order.
1373
1374 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1375
1376         * aarch64-dis.c (last_stop_offset): New.
1377         (print_insn_aarch64): Use stop_offset.
1378
1379 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1380
1381         PR gas/24359
1382         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1383         CPU_ANY_AVX2_FLAGS.
1384         * i386-init.h: Regenerated.
1385
1386 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1387
1388         PR gas/24348
1389         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1390         vmovdqu16, vmovdqu32 and vmovdqu64.
1391         * i386-tbl.h: Regenerated.
1392
1393 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1394
1395         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1396         from vstrszb, vstrszh, and vstrszf.
1397
1398 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1399
1400         * s390-opc.txt: Add instruction descriptions.
1401
1402 2019-02-08  Jim Wilson  <jimw@sifive.com>
1403
1404         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1405         <bne>: Likewise.
1406
1407 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1408
1409         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1410
1411 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1412
1413         PR binutils/23212
1414         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1415         * aarch64-opc.c (verify_elem_sd): New.
1416         (fields): Add FLD_sz entr.
1417         * aarch64-tbl.h (_SIMD_INSN): New.
1418         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1419         fmulx scalar and vector by element isns.
1420
1421 2019-02-07  Nick Clifton  <nickc@redhat.com>
1422
1423         * po/sv.po: Updated Swedish translation.
1424
1425 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1426
1427         * s390-mkopc.c (main): Accept arch13 as cpu string.
1428         * s390-opc.c: Add new instruction formats and instruction opcode
1429         masks.
1430         * s390-opc.txt: Add new arch13 instructions.
1431
1432 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1433
1434         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1435         (aarch64_opcode): Change encoding for stg, stzg
1436         st2g and st2zg.
1437         * aarch64-asm-2.c: Regenerated.
1438         * aarch64-dis-2.c: Regenerated.
1439         * aarch64-opc-2.c: Regenerated.
1440
1441 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1442
1443         * aarch64-asm-2.c: Regenerated.
1444         * aarch64-dis-2.c: Likewise.
1445         * aarch64-opc-2.c: Likewise.
1446         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1447
1448 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1449             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1450
1451         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1452         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1453         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1454         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1455         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1456         case for ldstgv_indexed.
1457         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1458         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1459         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1460         * aarch64-asm-2.c: Regenerated.
1461         * aarch64-dis-2.c: Regenerated.
1462         * aarch64-opc-2.c: Regenerated.
1463
1464 2019-01-23  Nick Clifton  <nickc@redhat.com>
1465
1466         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1467
1468 2019-01-21  Nick Clifton  <nickc@redhat.com>
1469
1470         * po/de.po: Updated German translation.
1471         * po/uk.po: Updated Ukranian translation.
1472
1473 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1474         * mips-dis.c (mips_arch_choices): Fix typo in
1475         gs464, gs464e and gs264e descriptors.
1476
1477 2019-01-19  Nick Clifton  <nickc@redhat.com>
1478
1479         * configure: Regenerate.
1480         * po/opcodes.pot: Regenerate.
1481
1482 2018-06-24  Nick Clifton  <nickc@redhat.com>
1483
1484         2.32 branch created.
1485
1486 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1487
1488         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1489         if it is null.
1490         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1491         zero.
1492
1493 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1494
1495         * configure: Regenerate.
1496
1497 2019-01-07  Alan Modra  <amodra@gmail.com>
1498
1499         * configure: Regenerate.
1500         * po/POTFILES.in: Regenerate.
1501
1502 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1503
1504         * s12z-opc.c: New file.
1505         * s12z-opc.h: New file.
1506         * s12z-dis.c: Removed all code not directly related to display
1507         of instructions.  Used the interface provided by the new files
1508         instead.
1509         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1510         * Makefile.in: Regenerate.
1511         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1512         * configure: Regenerate.
1513
1514 2019-01-01  Alan Modra  <amodra@gmail.com>
1515
1516         Update year range in copyright notice of all files.
1517
1518 For older changes see ChangeLog-2018
1519 \f
1520 Copyright (C) 2019 Free Software Foundation, Inc.
1521
1522 Copying and distribution of this file, with or without modification,
1523 are permitted in any medium without royalty provided the copyright
1524 notice and this notice are preserved.
1525
1526 Local Variables:
1527 mode: change-log
1528 left-margin: 8
1529 fill-column: 74
1530 version-control: never
1531 End: