1 2020-02-12 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
4 with Unspecified, making the present one AT&T syntax only.
5 * i386-tbl.h: Re-generate.
7 2020-02-12 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
10 * i386-tbl.h: Re-generate.
12 2020-02-12 Jan Beulich <jbeulich@suse.com>
15 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
16 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
17 Amd64 and Intel64 templates.
18 (call, jmp): Likewise for far indirect variants. Dro
20 * i386-tbl.h: Re-generate.
22 2020-02-11 Jan Beulich <jbeulich@suse.com>
24 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
25 * i386-opc.h (ShortForm): Delete.
26 (struct i386_opcode_modifier): Remove shortform field.
27 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
28 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
29 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
30 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
32 * i386-tbl.h: Re-generate.
34 2020-02-11 Jan Beulich <jbeulich@suse.com>
36 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
37 fucompi): Drop ShortForm from operand-less templates.
38 * i386-tbl.h: Re-generate.
40 2020-02-11 Alan Modra <amodra@gmail.com>
42 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
43 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
44 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
45 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
46 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
48 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
50 * arm-dis.c (print_insn_cde): Define 'V' parse character.
51 (cde_opcodes): Add VCX* instructions.
53 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
54 Matthew Malcomson <matthew.malcomson@arm.com>
56 * arm-dis.c (struct cdeopcode32): New.
57 (CDE_OPCODE): New macro.
58 (cde_opcodes): New disassembly table.
59 (regnames): New option to table.
60 (cde_coprocs): New global variable.
62 (print_insn_thumb32): Use print_insn_cde.
63 (parse_arm_disassembler_options): Parse coprocN args.
65 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
68 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
70 * i386-opc.h (AMD64): Removed.
74 (INTEL64ONLY): Likewise.
75 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
76 * i386-opc.tbl (Amd64): New.
78 (Intel64Only): Likewise.
79 Replace AMD64 with Amd64. Update sysenter/sysenter with
80 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
81 * i386-tbl.h: Regenerated.
83 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
86 * z80-dis.c: Add support for GBZ80 opcodes.
88 2020-02-04 Alan Modra <amodra@gmail.com>
90 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
92 2020-02-03 Alan Modra <amodra@gmail.com>
94 * m32c-ibld.c: Regenerate.
96 2020-02-01 Alan Modra <amodra@gmail.com>
98 * frv-ibld.c: Regenerate.
100 2020-01-31 Jan Beulich <jbeulich@suse.com>
102 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
103 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
104 (OP_E_memory): Replace xmm_mdq_mode case label by
105 vex_scalar_w_dq_mode one.
106 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
108 2020-01-31 Jan Beulich <jbeulich@suse.com>
110 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
111 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
112 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
113 (intel_operand_size): Drop vex_w_dq_mode case label.
115 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
117 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
118 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
120 2020-01-30 Alan Modra <amodra@gmail.com>
122 * m32c-ibld.c: Regenerate.
124 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
126 * bpf-opc.c: Regenerate.
128 2020-01-30 Jan Beulich <jbeulich@suse.com>
130 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
131 (dis386): Use them to replace C2/C3 table entries.
132 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
133 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
134 ones. Use Size64 instead of DefaultSize on Intel64 ones.
135 * i386-tbl.h: Re-generate.
137 2020-01-30 Jan Beulich <jbeulich@suse.com>
139 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
141 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
143 * i386-tbl.h: Re-generate.
145 2020-01-30 Alan Modra <amodra@gmail.com>
147 * tic4x-dis.c (tic4x_dp): Make unsigned.
149 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
150 Jan Beulich <jbeulich@suse.com>
153 * i386-dis.c (MOVSXD_Fixup): New function.
154 (movsxd_mode): New enum.
155 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
156 (intel_operand_size): Handle movsxd_mode.
157 (OP_E_register): Likewise.
159 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
160 register on movsxd. Add movsxd with 16-bit destination register
161 for AMD64 and Intel64 ISAs.
162 * i386-tbl.h: Regenerated.
164 2020-01-27 Tamar Christina <tamar.christina@arm.com>
167 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
168 * aarch64-asm-2.c: Regenerate
169 * aarch64-dis-2.c: Likewise.
170 * aarch64-opc-2.c: Likewise.
172 2020-01-21 Jan Beulich <jbeulich@suse.com>
174 * i386-opc.tbl (sysret): Drop DefaultSize.
175 * i386-tbl.h: Re-generate.
177 2020-01-21 Jan Beulich <jbeulich@suse.com>
179 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
181 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
182 * i386-tbl.h: Re-generate.
184 2020-01-20 Nick Clifton <nickc@redhat.com>
186 * po/de.po: Updated German translation.
187 * po/pt_BR.po: Updated Brazilian Portuguese translation.
188 * po/uk.po: Updated Ukranian translation.
190 2020-01-20 Alan Modra <amodra@gmail.com>
192 * hppa-dis.c (fput_const): Remove useless cast.
194 2020-01-20 Alan Modra <amodra@gmail.com>
196 * arm-dis.c (print_insn_arm): Wrap 'T' value.
198 2020-01-18 Nick Clifton <nickc@redhat.com>
200 * configure: Regenerate.
201 * po/opcodes.pot: Regenerate.
203 2020-01-18 Nick Clifton <nickc@redhat.com>
205 Binutils 2.34 branch created.
207 2020-01-17 Christian Biesinger <cbiesinger@google.com>
209 * opintl.h: Fix spelling error (seperate).
211 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
213 * i386-opc.tbl: Add {vex} pseudo prefix.
214 * i386-tbl.h: Regenerated.
216 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
219 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
220 (neon_opcodes): Likewise.
221 (select_arm_features): Make sure we enable MVE bits when selecting
222 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
225 2020-01-16 Jan Beulich <jbeulich@suse.com>
227 * i386-opc.tbl: Drop stale comment from XOP section.
229 2020-01-16 Jan Beulich <jbeulich@suse.com>
231 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
232 (extractps): Add VexWIG to SSE2AVX forms.
233 * i386-tbl.h: Re-generate.
235 2020-01-16 Jan Beulich <jbeulich@suse.com>
237 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
238 Size64 from and use VexW1 on SSE2AVX forms.
239 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
240 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
241 * i386-tbl.h: Re-generate.
243 2020-01-15 Alan Modra <amodra@gmail.com>
245 * tic4x-dis.c (tic4x_version): Make unsigned long.
246 (optab, optab_special, registernames): New file scope vars.
247 (tic4x_print_register): Set up registernames rather than
248 malloc'd registertable.
249 (tic4x_disassemble): Delete optable and optable_special. Use
250 optab and optab_special instead. Throw away old optab,
251 optab_special and registernames when info->mach changes.
253 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
256 * z80-dis.c (suffix): Use .db instruction to generate double
259 2020-01-14 Alan Modra <amodra@gmail.com>
261 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
262 values to unsigned before shifting.
264 2020-01-13 Thomas Troeger <tstroege@gmx.de>
266 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
268 (print_insn_thumb16, print_insn_thumb32): Likewise.
269 (print_insn): Initialize the insn info.
270 * i386-dis.c (print_insn): Initialize the insn info fields, and
273 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
275 * arc-opc.c (C_NE): Make it required.
277 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
279 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
280 reserved register name.
282 2020-01-13 Alan Modra <amodra@gmail.com>
284 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
285 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
287 2020-01-13 Alan Modra <amodra@gmail.com>
289 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
290 result of wasm_read_leb128 in a uint64_t and check that bits
291 are not lost when copying to other locals. Use uint32_t for
292 most locals. Use PRId64 when printing int64_t.
294 2020-01-13 Alan Modra <amodra@gmail.com>
296 * score-dis.c: Formatting.
297 * score7-dis.c: Formatting.
299 2020-01-13 Alan Modra <amodra@gmail.com>
301 * score-dis.c (print_insn_score48): Use unsigned variables for
302 unsigned values. Don't left shift negative values.
303 (print_insn_score32): Likewise.
304 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
306 2020-01-13 Alan Modra <amodra@gmail.com>
308 * tic4x-dis.c (tic4x_print_register): Remove dead code.
310 2020-01-13 Alan Modra <amodra@gmail.com>
312 * fr30-ibld.c: Regenerate.
314 2020-01-13 Alan Modra <amodra@gmail.com>
316 * xgate-dis.c (print_insn): Don't left shift signed value.
317 (ripBits): Formatting, use 1u.
319 2020-01-10 Alan Modra <amodra@gmail.com>
321 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
322 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
324 2020-01-10 Alan Modra <amodra@gmail.com>
326 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
327 and XRREG value earlier to avoid a shift with negative exponent.
328 * m10200-dis.c (disassemble): Similarly.
330 2020-01-09 Nick Clifton <nickc@redhat.com>
333 * z80-dis.c (ld_ii_ii): Use correct cast.
335 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
338 * z80-dis.c (ld_ii_ii): Use character constant when checking
341 2020-01-09 Jan Beulich <jbeulich@suse.com>
343 * i386-dis.c (SEP_Fixup): New.
345 (dis386_twobyte): Use it for sysenter/sysexit.
346 (enum x86_64_isa): Change amd64 enumerator to value 1.
347 (OP_J): Compare isa64 against intel64 instead of amd64.
348 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
350 * i386-tbl.h: Re-generate.
352 2020-01-08 Alan Modra <amodra@gmail.com>
354 * z8k-dis.c: Include libiberty.h
355 (instr_data_s): Make max_fetched unsigned.
356 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
357 Don't exceed byte_info bounds.
358 (output_instr): Make num_bytes unsigned.
359 (unpack_instr): Likewise for nibl_count and loop.
360 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
362 * z8k-opc.h: Regenerate.
364 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
366 * arc-tbl.h (llock): Use 'LLOCK' as class.
368 (scond): Use 'SCOND' as class.
370 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
373 2020-01-06 Alan Modra <amodra@gmail.com>
375 * m32c-ibld.c: Regenerate.
377 2020-01-06 Alan Modra <amodra@gmail.com>
380 * z80-dis.c (suffix): Don't use a local struct buffer copy.
381 Peek at next byte to prevent recursion on repeated prefix bytes.
382 Ensure uninitialised "mybuf" is not accessed.
383 (print_insn_z80): Don't zero n_fetch and n_used here,..
384 (print_insn_z80_buf): ..do it here instead.
386 2020-01-04 Alan Modra <amodra@gmail.com>
388 * m32r-ibld.c: Regenerate.
390 2020-01-04 Alan Modra <amodra@gmail.com>
392 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
394 2020-01-04 Alan Modra <amodra@gmail.com>
396 * crx-dis.c (match_opcode): Avoid shift left of signed value.
398 2020-01-04 Alan Modra <amodra@gmail.com>
400 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
402 2020-01-03 Jan Beulich <jbeulich@suse.com>
404 * aarch64-tbl.h (aarch64_opcode_table): Use
405 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
407 2020-01-03 Jan Beulich <jbeulich@suse.com>
409 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
410 forms of SUDOT and USDOT.
412 2020-01-03 Jan Beulich <jbeulich@suse.com>
414 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
416 * opcodes/aarch64-dis-2.c: Re-generate.
418 2020-01-03 Jan Beulich <jbeulich@suse.com>
420 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
422 * opcodes/aarch64-dis-2.c: Re-generate.
424 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
426 * z80-dis.c: Add support for eZ80 and Z80 instructions.
428 2020-01-01 Alan Modra <amodra@gmail.com>
430 Update year range in copyright notice of all files.
432 For older changes see ChangeLog-2019
434 Copyright (C) 2020 Free Software Foundation, Inc.
436 Copying and distribution of this file, with or without modification,
437 are permitted in any medium without royalty provided the copyright
438 notice and this notice are preserved.
444 version-control: never