1 2017-12-18 Jan Beulich <jbeulich@suse.com>
3 * i386-gen.c (operand_type_shorthands): Add FloatAcc and
5 (operand_types): Drop FloatAcc and FloatReg.
6 * i386-opc.h (enum of operand types): Likewise. Extend comment.
7 (union i386_operand_type): Drop floatacc and floatreg.
8 * i386-reg.tbl (st, st(0)): Replace FloatAcc by Acc.
9 * i386-init.h, i386-tbl.h: Re-generate.
11 2017-12-18 Jan Beulich <jbeulich@suse.com>
13 * i386-gen.c (operand_type_shorthands): New.
14 (opcode_modifiers): Replace Reg<N> with just Reg.
15 (set_bitfield_from_cpu_flag_init): Rename to
16 set_bitfield_from_shorthand. Drop value parameter. Process
17 operand_type_shorthands.
18 (set_bitfield): Adjust call accordingly.
19 * i386-opc.h (enum of operand types): Replace Reg<N> with just
21 (union i386_operand_type): Replace reg<N> with just reg.
22 * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
23 vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
24 separate register and memory forms.
25 * i386-reg.tbl (al): Drop Byte.
29 * i386-init.h, i386-tbl.h: Re-generate.
31 2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
33 * disassemble.c (disassemble_init_for_target): Don't put PRU
34 between powerpc and rs6000 cases.
36 2017-12-15 Jan Beulich <jbeulich@suse.com>
38 * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
39 movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
40 sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
41 stos, sub, test, xor): Drop CheckRegSize from variants not
42 allowing for two (or more) register operands.
43 * i386-tbl.h: Re-generate.
45 2017-12-13 Jim Wilson <jimw@sifive.com>
48 * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
50 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
52 * disassemble.c: Enable disassembler_needs_relocs for PRU.
54 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
55 Renlin Li <renlin.li@arm.com>
57 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
58 (get_sym_code_type): Here.
60 2017-12-03 Alan Modra <amodra@gmail.com>
62 * ppc-opc.c (extract_li20): Rewrite.
64 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
66 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
67 (operand_value_powerpc): Update return and argument type.
68 <value, top>: Update type.
69 (skip_optional_operands): Update argument type.
70 (lookup_powerpc): Likewise.
71 (lookup_vle): Likewise.
72 <table_opcd, table_mask, insn2>: Update type.
73 (lookup_spe2): Update argument type.
74 <table_opcd, table_mask, insn2>: Update type.
75 (print_insn_powerpc) <insn, value>: Update type.
76 Use PPC_INT_FMT for printing instructions and operands.
77 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
78 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
79 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
80 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
81 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
82 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
83 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
84 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
85 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
86 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
87 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
88 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
89 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
90 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
91 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
92 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
93 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
94 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
95 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
96 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
97 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
98 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
99 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
100 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
101 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
102 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
103 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
104 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
105 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
106 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
107 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
108 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
109 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
110 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
111 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
112 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
113 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
115 2017-11-29 Jan Beulich <jbeulich@suse.com>
117 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
119 (output_cpu_flags): Update active_cpu_flags.
120 (process_i386_opcode_modifier): Update active_isstring.
121 (output_operand_type): Rename "macro" parameter to "stage",
123 (process_i386_operand_type): Likewise. Track presence of
124 BaseIndex and emit DispN accordingly.
125 (output_i386_opcode, process_i386_registers,
126 process_i386_initializers): Adjust calls to
127 process_i386_operand_type() for its changed parameter type.
128 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
129 all insns operands having BaseIndex set.
130 * i386-tbl.h: Re-generate.
132 2017-11-29 Jan Beulich <jbeulich@suse.com>
134 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
136 (operand_types): Remove Vec_Disp8 entry.
137 * i386-opc.h (Vec_Disp8): Delete.
138 (union i386_operand_type): Remove vec_disp8.
139 (i386-opc.tbl): Remove Vec_Disp8.
140 * i386-init.h, i386-tbl.h: Re-generate.
142 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
144 * po/Make-in (datadir): Define as @datadir@.
145 (localedir): Define as @localedir@.
146 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
148 2017-11-27 Nick Clifton <nickc@redhat.com>
150 * po/zh_CN.po: Updated simplified Chinese translation.
152 2017-11-24 Jan Beulich <jbeulich@suse.com>
154 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
157 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
159 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
160 * i386-tbl.h: Regenerate.
162 2017-11-23 Jan Beulich <jbeulich@suse.com>
164 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
165 the 16-bit addressing case.
167 2017-11-23 Jan Beulich <jbeulich@suse.com>
169 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
170 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
171 * i386-opc.tbl (ud1, ud2b): Add operands.
173 * i386-tbl.h: Re-generate.
175 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
177 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
178 * i386-tbl.h: Regenerate.
180 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
182 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
183 * i386-tbl.h: Regenerate.
185 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
187 *arc-opc (insert_rhv2): Check h-regs range.
189 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
191 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
192 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
194 2017-11-16 Tamar Christina <tamar.christina@arm.com>
196 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
197 and AARCH64_FEATURE_F16.
199 2017-11-16 Tamar Christina <tamar.christina@arm.com>
201 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
202 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
203 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
204 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
205 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
206 (ldapur, ldapursw, stlur): New.
207 * aarch64-dis-2.c: Regenerate.
209 2017-11-16 Jan Beulich <jbeulich@suse.com>
211 (get_valid_dis386): Never flag bad opcode when
212 vex.register_specifier is beyond 7. Always store all four
213 bits of it. Move 16-/32-bit override in EVEX handling after
214 all to be overridden bits have been set.
215 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
216 Use rex to determine GPR register set.
217 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
218 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
220 2017-11-15 Jan Beulich <jbeulich@suse.com>
222 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
223 determine GPR register set.
225 2017-11-15 Jan Beulich <jbeulich@suse.com>
227 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
228 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
229 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
231 (OP_REG_VexI4): Drop low 4 bits check.
233 2017-11-15 Jan Beulich <jbeulich@suse.com>
235 * i386-reg.tbl (axl): Remove Acc and Byte.
236 * i386-tbl.h: Re-generate.
238 2017-11-14 Jan Beulich <jbeulich@suse.com>
240 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
241 (vex_len_table): Use VPCOM.
243 2017-11-14 Jan Beulich <jbeulich@suse.com>
245 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
246 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
247 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
249 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
250 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
251 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
252 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
254 * i386-tbl.h: Re-generate.
256 2017-11-14 Jan Beulich <jbeulich@suse.com>
258 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
259 smov, ssca, stos, ssto, xlat): Drop Disp*.
260 * i386-tbl.h: Re-generate.
262 2017-11-13 Jan Beulich <jbeulich@suse.com>
264 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
265 xsaveopt64): Add No_qSuf.
266 * i386-tbl.h: Re-generate.
268 2017-11-09 Tamar Christina <tamar.christina@arm.com>
270 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
271 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
272 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
273 sder32_el2, vncr_el2.
274 (aarch64_sys_reg_supported_p): Likewise.
275 (aarch64_pstatefields): Add dit register.
276 (aarch64_pstatefield_supported_p): Likewise.
277 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
278 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
279 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
280 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
281 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
282 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
283 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
285 2017-11-09 Tamar Christina <tamar.christina@arm.com>
287 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
288 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
289 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
290 (QL_STLW, QL_STLX): New.
292 2017-11-09 Tamar Christina <tamar.christina@arm.com>
294 * aarch64-asm.h (ins_addr_offset): New.
295 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
296 (aarch64_ins_addr_offset): New.
297 * aarch64-asm-2.c: Regenerate.
298 * aarch64-dis.h (ext_addr_offset): New.
299 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
300 (aarch64_ext_addr_offset): New.
301 * aarch64-dis-2.c: Regenerate.
302 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
303 FLD_imm4_2 and FLD_SM3_imm2.
304 * aarch64-opc.c (fields): Add FLD_imm6_2,
305 FLD_imm4_2 and FLD_SM3_imm2.
306 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
307 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
308 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
309 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
311 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
313 2017-11-09 Tamar Christina <tamar.christina@arm.com>
316 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
317 (aarch64_feature_sm4, aarch64_feature_sha3): New.
318 (aarch64_feature_fp_16_v8_2): New.
319 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
320 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
321 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
323 2017-11-08 Tamar Christina <tamar.christina@arm.com>
325 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
326 (aarch64_feature_sha2, aarch64_feature_aes): New.
328 (AES_INSN, SHA2_INSN): New.
329 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
330 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
331 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
334 2017-11-08 Jiong Wang <jiong.wang@arm.com>
335 Tamar Christina <tamar.christina@arm.com>
337 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
338 FP16 instructions, including vfmal.f16 and vfmsl.f16.
340 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
342 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
344 2017-11-07 Alan Modra <amodra@gmail.com>
346 * opintl.h: Formatting, comment fixes.
347 (gettext, ngettext): Redefine when ENABLE_NLS.
348 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
349 (_): Define using gettext.
350 (textdomain, bindtextdomain): Use safer "do nothing".
352 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
354 * arc-dis.c (print_hex): New variable.
355 (parse_option): Check for hex option.
356 (print_insn_arc): Use hexadecimal representation for short
357 immediate values when requested.
358 (print_arc_disassembler_options): Add hex option to the list.
360 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
362 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
363 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
364 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
365 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
366 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
367 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
368 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
369 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
370 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
371 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
372 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
373 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
374 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
375 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
376 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
377 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
378 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
379 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
380 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
382 (prealloc, prefetch*): Place them before ld instruction.
383 * arc-opc.c (skip_this_opcode): Add ARITH class.
385 2017-10-25 Alan Modra <amodra@gmail.com>
388 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
389 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
390 (imm4flag, size_changed): Likewise.
391 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
392 (words, allWords, processing_argument_number): Likewise.
393 (cst4flag, size_changed): Likewise.
394 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
395 (crx_cst4_maps): Rename from cst4_maps.
396 (crx_no_op_insn): Rename from no_op_insn.
398 2017-10-24 Andrew Waterman <andrew@sifive.com>
400 * riscv-opc.c (match_c_addi16sp) : New function.
401 (match_c_addi4spn): New function.
402 (match_c_lui): Don't allow 0-immediate encodings.
403 (riscv_opcodes) <addi>: Use the above functions.
405 <c.addi4spn>: Likewise.
406 <c.addi16sp>: Likewise.
408 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
410 * i386-init.h: Regenerate
411 * i386-tbl.h: Likewise
413 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
415 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
416 (enum): Add EVEX_W_0F3854_P_2.
417 * i386-dis-evex.h (evex_table): Updated.
418 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
419 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
420 (cpu_flags): Add CpuAVX512_BITALG.
421 * i386-opc.h (enum): Add CpuAVX512_BITALG.
422 (i386_cpu_flags): Add cpuavx512_bitalg..
423 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
424 * i386-init.h: Regenerate.
425 * i386-tbl.h: Likewise.
427 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
429 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
430 * i386-dis-evex.h (evex_table): Updated.
431 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
432 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
433 (cpu_flags): Add CpuAVX512_VNNI.
434 * i386-opc.h (enum): Add CpuAVX512_VNNI.
435 (i386_cpu_flags): Add cpuavx512_vnni.
436 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
437 * i386-init.h: Regenerate.
438 * i386-tbl.h: Likewise.
440 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
442 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
443 (enum): Remove VEX_LEN_0F3A44_P_2.
444 (vex_len_table): Ditto.
445 (enum): Remove VEX_W_0F3A44_P_2.
446 (vew_w_table): Ditto.
447 (prefix_table): Adjust instructions (see prefixes above).
448 * i386-dis-evex.h (evex_table):
449 Add new instructions (see prefixes above).
450 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
451 (bitfield_cpu_flags): Ditto.
452 * i386-opc.h (enum): Ditto.
453 (i386_cpu_flags): Ditto.
454 (CpuUnused): Comment out to avoid zero-width field problem.
455 * i386-opc.tbl (vpclmulqdq): New instruction.
456 * i386-init.h: Regenerate.
459 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
461 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
462 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
463 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
464 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
465 (vex_len_table): Ditto.
466 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
467 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
468 (vew_w_table): Ditto.
469 (prefix_table): Adjust instructions (see prefixes above).
470 * i386-dis-evex.h (evex_table):
471 Add new instructions (see prefixes above).
472 * i386-gen.c (cpu_flag_init): Add VAES.
473 (bitfield_cpu_flags): Ditto.
474 * i386-opc.h (enum): Ditto.
475 (i386_cpu_flags): Ditto.
476 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
477 * i386-init.h: Regenerate.
480 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
482 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
483 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
484 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
485 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
486 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
487 (prefix_table): Updated (see prefixes above).
488 (three_byte_table): Likewise.
489 (vex_w_table): Likewise.
490 * i386-dis-evex.h: Likewise.
491 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
492 (cpu_flags): Add CpuGFNI.
493 * i386-opc.h (enum): Add CpuGFNI.
494 (i386_cpu_flags): Add cpugfni.
495 * i386-opc.tbl: Add Intel GFNI instructions.
496 * i386-init.h: Regenerate.
497 * i386-tbl.h: Likewise.
499 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
501 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
502 Define EXbScalar and EXwScalar for OP_EX.
503 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
504 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
505 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
506 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
507 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
508 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
509 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
510 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
511 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
512 (OP_E_memory): Likewise.
513 * i386-dis-evex.h: Updated.
514 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
515 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
516 (cpu_flags): Add CpuAVX512_VBMI2.
517 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
518 (i386_cpu_flags): Add cpuavx512_vbmi2.
519 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
520 * i386-init.h: Regenerate.
521 * i386-tbl.h: Likewise.
523 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
525 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
527 2017-10-12 James Bowman <james.bowman@ftdichip.com>
529 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
530 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
531 K15. Add jmpix pattern.
533 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
535 * s390-opc.txt (prno, tpei, irbm): New instructions added.
537 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
539 * s390-opc.c (INSTR_SI_RD): New macro.
540 (INSTR_S_RD): Adjust example instruction.
541 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
544 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
546 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
547 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
548 VLE multimple load/store instructions. Old e_ldm* variants are
550 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
552 2017-09-27 Nick Clifton <nickc@redhat.com>
555 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
556 names for the fmv.x.s and fmv.s.x instructions respectively.
558 2017-09-26 do <do@nerilex.org>
561 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
562 be used on CPUs that have emacs support.
564 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
566 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
568 2017-09-09 Kamil Rytarowski <n54@gmx.com>
570 * nds32-asm.c: Rename __BIT() to N32_BIT().
571 * nds32-asm.h: Likewise.
572 * nds32-dis.c: Likewise.
574 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
576 * i386-dis.c (last_active_prefix): Removed.
577 (ckprefix): Don't set last_active_prefix.
578 (NOTRACK_Fixup): Don't check last_active_prefix.
580 2017-08-31 Nick Clifton <nickc@redhat.com>
582 * po/fr.po: Updated French translation.
584 2017-08-31 James Bowman <james.bowman@ftdichip.com>
586 * ft32-dis.c (print_insn_ft32): Correct display of non-address
589 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
590 Edmar Wienskoski <edmar.wienskoski@nxp.com>
592 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
593 PPC_OPCODE_EFS2 flag to "e200z4" entry.
594 New entries efs2 and spe2.
595 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
596 (SPE2_OPCD_SEGS): New macro.
597 (spe2_opcd_indices): New.
598 (disassemble_init_powerpc): Handle SPE2 opcodes.
599 (lookup_spe2): New function.
600 (print_insn_powerpc): call lookup_spe2.
601 * ppc-opc.c (insert_evuimm1_ex0): New function.
602 (extract_evuimm1_ex0): Likewise.
603 (insert_evuimm_lt8): Likewise.
604 (extract_evuimm_lt8): Likewise.
605 (insert_off_spe2): Likewise.
606 (extract_off_spe2): Likewise.
607 (insert_Ddd): Likewise.
608 (extract_Ddd): Likewise.
610 (EVUIMM_LT8): Likewise.
611 (EVUIMM_LT16): Adjust.
613 (EVUIMM_1): Likewise.
614 (EVUIMM_1_EX0): Likewise.
617 (VX_OFF_SPE2): Likewise.
620 (VX_MASK_DDD): New mask.
622 (VX_RA_CONST): New macro.
623 (VX_RA_CONST_MASK): Likewise.
624 (VX_RB_CONST): Likewise.
625 (VX_RB_CONST_MASK): Likewise.
626 (VX_OFF_SPE2_MASK): Likewise.
627 (VX_SPE_CRFD): Likewise.
628 (VX_SPE_CRFD_MASK VX): Likewise.
629 (VX_SPE2_CLR): Likewise.
630 (VX_SPE2_CLR_MASK): Likewise.
631 (VX_SPE2_SPLATB): Likewise.
632 (VX_SPE2_SPLATB_MASK): Likewise.
633 (VX_SPE2_OCTET): Likewise.
634 (VX_SPE2_OCTET_MASK): Likewise.
635 (VX_SPE2_DDHH): Likewise.
636 (VX_SPE2_DDHH_MASK): Likewise.
637 (VX_SPE2_HH): Likewise.
638 (VX_SPE2_HH_MASK): Likewise.
639 (VX_SPE2_EVMAR): Likewise.
640 (VX_SPE2_EVMAR_MASK): Likewise.
643 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
644 (powerpc_macros): Map old SPE instructions have new names
645 with the same opcodes. Add SPE2 instructions which just are
647 (spe2_opcodes): Add SPE2 opcodes.
649 2017-08-23 Alan Modra <amodra@gmail.com>
651 * ppc-opc.c: Formatting and comment fixes. Move insert and
652 extract functions earlier, deleting forward declarations.
653 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
656 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
658 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
660 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
661 Edmar Wienskoski <edmar.wienskoski@nxp.com>
663 * ppc-opc.c (insert_evuimm2_ex0): New function.
664 (extract_evuimm2_ex0): Likewise.
665 (insert_evuimm4_ex0): Likewise.
666 (extract_evuimm4_ex0): Likewise.
667 (insert_evuimm8_ex0): Likewise.
668 (extract_evuimm8_ex0): Likewise.
669 (insert_evuimm_lt16): Likewise.
670 (extract_evuimm_lt16): Likewise.
671 (insert_rD_rS_even): Likewise.
672 (extract_rD_rS_even): Likewise.
673 (insert_off_lsp): Likewise.
674 (extract_off_lsp): Likewise.
675 (RD_EVEN): New operand.
678 (EVUIMM_LT16): New operand.
680 (EVUIMM_2_EX0): New operand.
682 (EVUIMM_4_EX0): New operand.
684 (EVUIMM_8_EX0): New operand.
686 (VX_OFF): New operand.
688 (VX_LSP_MASK): Likewise.
689 (VX_LSP_OFF_MASK): Likewise.
690 (PPC_OPCODE_LSP): Likewise.
691 (vle_opcodes): Add LSP opcodes.
692 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
694 2017-08-09 Jiong Wang <jiong.wang@arm.com>
696 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
697 register operands in CRC instructions.
698 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
701 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
703 * disassemble.c (disassembler): Mark big and mach with
706 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
708 * disassemble.c (disassembler): Remove arch/mach/endian
711 2017-07-25 Nick Clifton <nickc@redhat.com>
714 * arc-opc.c (insert_rhv2): Use lower case first letter in error
716 (insert_r0): Likewise.
717 (insert_r1): Likewise.
718 (insert_r2): Likewise.
719 (insert_r3): Likewise.
720 (insert_sp): Likewise.
721 (insert_gp): Likewise.
722 (insert_pcl): Likewise.
723 (insert_blink): Likewise.
724 (insert_ilink1): Likewise.
725 (insert_ilink2): Likewise.
726 (insert_ras): Likewise.
727 (insert_rbs): Likewise.
728 (insert_rcs): Likewise.
729 (insert_simm3s): Likewise.
730 (insert_rrange): Likewise.
731 (insert_r13el): Likewise.
732 (insert_fpel): Likewise.
733 (insert_blinkel): Likewise.
734 (insert_pclel): Likewise.
735 (insert_nps_bitop_size_2b): Likewise.
736 (insert_nps_imm_offset): Likewise.
737 (insert_nps_imm_entry): Likewise.
738 (insert_nps_size_16bit): Likewise.
739 (insert_nps_##NAME##_pos): Likewise.
740 (insert_nps_##NAME): Likewise.
741 (insert_nps_bitop_ins_ext): Likewise.
742 (insert_nps_##NAME): Likewise.
743 (insert_nps_min_hofs): Likewise.
744 (insert_nps_##NAME): Likewise.
745 (insert_nps_rbdouble_64): Likewise.
746 (insert_nps_misc_imm_offset): Likewise.
747 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
750 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
751 Jiong Wang <jiong.wang@arm.com>
753 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
755 * aarch64-dis-2.c: Regenerated.
757 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
759 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
762 2017-07-20 Nick Clifton <nickc@redhat.com>
764 * po/de.po: Updated German translation.
766 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
768 * arc-regs.h (sec_stat): New aux register.
769 (aux_kernel_sp): Likewise.
770 (aux_sec_u_sp): Likewise.
771 (aux_sec_k_sp): Likewise.
772 (sec_vecbase_build): Likewise.
773 (nsc_table_top): Likewise.
774 (nsc_table_base): Likewise.
775 (ersec_stat): Likewise.
776 (aux_sec_except): Likewise.
778 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
780 * arc-opc.c (extract_uimm12_20): New function.
781 (UIMM12_20): New operand.
783 * arc-tbl.h (sjli): Add new instruction.
785 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
786 John Eric Martin <John.Martin@emmicro-us.com>
788 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
789 (UIMM3_23): Adjust accordingly.
790 * arc-regs.h: Add/correct jli_base register.
791 * arc-tbl.h (jli_s): Likewise.
793 2017-07-18 Nick Clifton <nickc@redhat.com>
796 * aarch64-opc.c: Fix spelling typos.
797 * i386-dis.c: Likewise.
799 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
801 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
802 max_addr_offset and octets variables to size_t.
804 2017-07-12 Alan Modra <amodra@gmail.com>
806 * po/da.po: Update from translationproject.org/latest/opcodes/.
807 * po/de.po: Likewise.
808 * po/es.po: Likewise.
809 * po/fi.po: Likewise.
810 * po/fr.po: Likewise.
811 * po/id.po: Likewise.
812 * po/it.po: Likewise.
813 * po/nl.po: Likewise.
814 * po/pt_BR.po: Likewise.
815 * po/ro.po: Likewise.
816 * po/sv.po: Likewise.
817 * po/tr.po: Likewise.
818 * po/uk.po: Likewise.
819 * po/vi.po: Likewise.
820 * po/zh_CN.po: Likewise.
822 2017-07-11 Yao Qi <yao.qi@linaro.org>
823 Alan Modra <amodra@gmail.com>
825 * cgen.sh: Mark generated files read-only.
826 * epiphany-asm.c: Regenerate.
827 * epiphany-desc.c: Regenerate.
828 * epiphany-desc.h: Regenerate.
829 * epiphany-dis.c: Regenerate.
830 * epiphany-ibld.c: Regenerate.
831 * epiphany-opc.c: Regenerate.
832 * epiphany-opc.h: Regenerate.
833 * fr30-asm.c: Regenerate.
834 * fr30-desc.c: Regenerate.
835 * fr30-desc.h: Regenerate.
836 * fr30-dis.c: Regenerate.
837 * fr30-ibld.c: Regenerate.
838 * fr30-opc.c: Regenerate.
839 * fr30-opc.h: Regenerate.
840 * frv-asm.c: Regenerate.
841 * frv-desc.c: Regenerate.
842 * frv-desc.h: Regenerate.
843 * frv-dis.c: Regenerate.
844 * frv-ibld.c: Regenerate.
845 * frv-opc.c: Regenerate.
846 * frv-opc.h: Regenerate.
847 * ip2k-asm.c: Regenerate.
848 * ip2k-desc.c: Regenerate.
849 * ip2k-desc.h: Regenerate.
850 * ip2k-dis.c: Regenerate.
851 * ip2k-ibld.c: Regenerate.
852 * ip2k-opc.c: Regenerate.
853 * ip2k-opc.h: Regenerate.
854 * iq2000-asm.c: Regenerate.
855 * iq2000-desc.c: Regenerate.
856 * iq2000-desc.h: Regenerate.
857 * iq2000-dis.c: Regenerate.
858 * iq2000-ibld.c: Regenerate.
859 * iq2000-opc.c: Regenerate.
860 * iq2000-opc.h: Regenerate.
861 * lm32-asm.c: Regenerate.
862 * lm32-desc.c: Regenerate.
863 * lm32-desc.h: Regenerate.
864 * lm32-dis.c: Regenerate.
865 * lm32-ibld.c: Regenerate.
866 * lm32-opc.c: Regenerate.
867 * lm32-opc.h: Regenerate.
868 * lm32-opinst.c: Regenerate.
869 * m32c-asm.c: Regenerate.
870 * m32c-desc.c: Regenerate.
871 * m32c-desc.h: Regenerate.
872 * m32c-dis.c: Regenerate.
873 * m32c-ibld.c: Regenerate.
874 * m32c-opc.c: Regenerate.
875 * m32c-opc.h: Regenerate.
876 * m32r-asm.c: Regenerate.
877 * m32r-desc.c: Regenerate.
878 * m32r-desc.h: Regenerate.
879 * m32r-dis.c: Regenerate.
880 * m32r-ibld.c: Regenerate.
881 * m32r-opc.c: Regenerate.
882 * m32r-opc.h: Regenerate.
883 * m32r-opinst.c: Regenerate.
884 * mep-asm.c: Regenerate.
885 * mep-desc.c: Regenerate.
886 * mep-desc.h: Regenerate.
887 * mep-dis.c: Regenerate.
888 * mep-ibld.c: Regenerate.
889 * mep-opc.c: Regenerate.
890 * mep-opc.h: Regenerate.
891 * mt-asm.c: Regenerate.
892 * mt-desc.c: Regenerate.
893 * mt-desc.h: Regenerate.
894 * mt-dis.c: Regenerate.
895 * mt-ibld.c: Regenerate.
896 * mt-opc.c: Regenerate.
897 * mt-opc.h: Regenerate.
898 * or1k-asm.c: Regenerate.
899 * or1k-desc.c: Regenerate.
900 * or1k-desc.h: Regenerate.
901 * or1k-dis.c: Regenerate.
902 * or1k-ibld.c: Regenerate.
903 * or1k-opc.c: Regenerate.
904 * or1k-opc.h: Regenerate.
905 * or1k-opinst.c: Regenerate.
906 * xc16x-asm.c: Regenerate.
907 * xc16x-desc.c: Regenerate.
908 * xc16x-desc.h: Regenerate.
909 * xc16x-dis.c: Regenerate.
910 * xc16x-ibld.c: Regenerate.
911 * xc16x-opc.c: Regenerate.
912 * xc16x-opc.h: Regenerate.
913 * xstormy16-asm.c: Regenerate.
914 * xstormy16-desc.c: Regenerate.
915 * xstormy16-desc.h: Regenerate.
916 * xstormy16-dis.c: Regenerate.
917 * xstormy16-ibld.c: Regenerate.
918 * xstormy16-opc.c: Regenerate.
919 * xstormy16-opc.h: Regenerate.
921 2017-07-07 Alan Modra <amodra@gmail.com>
923 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
924 * m32c-dis.c: Regenerate.
925 * mep-dis.c: Regenerate.
927 2017-07-05 Borislav Petkov <bp@suse.de>
929 * i386-dis.c: Enable ModRM.reg /6 aliases.
931 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
933 * opcodes/arm-dis.c: Support MVFR2 in disassembly
936 2017-07-04 Tristan Gingold <gingold@adacore.com>
938 * configure: Regenerate.
940 2017-07-03 Tristan Gingold <gingold@adacore.com>
942 * po/opcodes.pot: Regenerate.
944 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
946 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
947 entries to the MSA ASE instruction block.
949 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
950 Maciej W. Rozycki <macro@imgtec.com>
952 * micromips-opc.c (XPA, XPAVZ): New macros.
953 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
956 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
957 Maciej W. Rozycki <macro@imgtec.com>
959 * micromips-opc.c (I36): New macro.
960 (micromips_opcodes): Add "eretnc".
962 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
963 Andrew Bennett <andrew.bennett@imgtec.com>
965 * mips-dis.c (mips_calculate_combination_ases): Handle the
967 (parse_mips_ase_option): New function.
968 (parse_mips_dis_option): Factor out ASE option handling to the
969 new function. Call `mips_calculate_combination_ases'.
970 * mips-opc.c (XPAVZ): New macro.
971 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
972 "mfhgc0", "mthc0" and "mthgc0".
974 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
976 * mips-dis.c (mips_calculate_combination_ases): New function.
977 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
978 calculation to the new function.
979 (set_default_mips_dis_options): Call the new function.
981 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
983 * arc-dis.c (parse_disassembler_options): Use
984 FOR_EACH_DISASSEMBLER_OPTION.
986 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
988 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
989 disassembler option strings.
990 (parse_cpu_option): Likewise.
992 2017-06-28 Tamar Christina <tamar.christina@arm.com>
994 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
995 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
996 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
997 (aarch64_feature_dotprod, DOT_INSN): New.
999 * aarch64-dis-2.c: Regenerated.
1001 2017-06-28 Jiong Wang <jiong.wang@arm.com>
1003 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
1005 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
1006 Matthew Fortune <matthew.fortune@imgtec.com>
1007 Andrew Bennett <andrew.bennett@imgtec.com>
1009 * mips-formats.h (INT_BIAS): New macro.
1010 (INT_ADJ): Redefine in INT_BIAS terms.
1011 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
1012 (mips_print_save_restore): New function.
1013 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
1014 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
1016 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
1017 (print_mips16_insn_arg): Call `mips_print_save_restore' for
1018 OP_SAVE_RESTORE_LIST handling, factored out from here.
1019 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
1020 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
1021 (mips_builtin_opcodes): Add "restore" and "save" entries.
1022 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
1024 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
1026 2017-06-23 Andrew Waterman <andrew@sifive.com>
1028 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
1029 alias; do not mark SLTI instruction as an alias.
1031 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1033 * i386-dis.c (RM_0FAE_REG_5): Removed.
1034 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1035 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1036 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1037 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
1038 PREFIX_MOD_3_0F01_REG_5_RM_0.
1039 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
1040 PREFIX_MOD_3_0FAE_REG_5.
1041 (mod_table): Update MOD_0FAE_REG_5.
1042 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
1043 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1044 * i386-tbl.h: Regenerated.
1046 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1048 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1049 * i386-opc.tbl: Likewise.
1050 * i386-tbl.h: Regenerated.
1052 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1054 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1056 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1059 2017-06-19 Nick Clifton <nickc@redhat.com>
1062 * score-dis.c (score_opcodes): Add sentinel.
1064 2017-06-16 Alan Modra <amodra@gmail.com>
1066 * rx-decode.c: Regenerate.
1068 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1071 * i386-dis.c (OP_E_register): Check valid bnd register.
1074 2017-06-15 Nick Clifton <nickc@redhat.com>
1077 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1080 2017-06-15 Nick Clifton <nickc@redhat.com>
1083 * rl78-decode.opc (OP_BUF_LEN): Define.
1084 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1085 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1087 * rl78-decode.c: Regenerate.
1089 2017-06-15 Nick Clifton <nickc@redhat.com>
1092 * bfin-dis.c (gregs): Clip index to prevent overflow.
1094 (regs_lo): Likewise.
1095 (regs_hi): Likewise.
1097 2017-06-14 Nick Clifton <nickc@redhat.com>
1100 * score7-dis.c (score_opcodes): Add sentinel.
1102 2017-06-14 Yao Qi <yao.qi@linaro.org>
1104 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1105 * arm-dis.c: Likewise.
1106 * ia64-dis.c: Likewise.
1107 * mips-dis.c: Likewise.
1108 * spu-dis.c: Likewise.
1109 * disassemble.h (print_insn_aarch64): New declaration, moved from
1111 (print_insn_big_arm, print_insn_big_mips): Likewise.
1112 (print_insn_i386, print_insn_ia64): Likewise.
1113 (print_insn_little_arm, print_insn_little_mips): Likewise.
1115 2017-06-14 Nick Clifton <nickc@redhat.com>
1118 * rx-decode.opc: Include libiberty.h
1119 (GET_SCALE): New macro - validates access to SCALE array.
1120 (GET_PSCALE): New macro - validates access to PSCALE array.
1121 (DIs, SIs, S2Is, rx_disp): Use new macros.
1122 * rx-decode.c: Regenerate.
1124 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1126 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1128 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1130 * arc-dis.c (enforced_isa_mask): Declare.
1131 (cpu_types): Likewise.
1132 (parse_cpu_option): New function.
1133 (parse_disassembler_options): Use it.
1134 (print_insn_arc): Use enforced_isa_mask.
1135 (print_arc_disassembler_options): Document new options.
1137 2017-05-24 Yao Qi <yao.qi@linaro.org>
1139 * alpha-dis.c: Include disassemble.h, don't include
1141 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1142 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1143 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1144 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1145 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1146 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1147 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1148 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1149 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1150 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1151 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1152 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1153 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1154 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1155 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1156 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1157 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1158 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1159 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1160 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1161 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1162 * z80-dis.c, z8k-dis.c: Likewise.
1163 * disassemble.h: New file.
1165 2017-05-24 Yao Qi <yao.qi@linaro.org>
1167 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1168 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1170 2017-05-24 Yao Qi <yao.qi@linaro.org>
1172 * disassemble.c (disassembler): Add arguments a, big and mach.
1175 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1177 * i386-dis.c (NOTRACK_Fixup): New.
1178 (NOTRACK): Likewise.
1179 (NOTRACK_PREFIX): Likewise.
1180 (last_active_prefix): Likewise.
1181 (reg_table): Use NOTRACK on indirect call and jmp.
1182 (ckprefix): Set last_active_prefix.
1183 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1184 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1185 * i386-opc.h (NoTrackPrefixOk): New.
1186 (i386_opcode_modifier): Add notrackprefixok.
1187 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1189 * i386-tbl.h: Regenerated.
1191 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1193 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1195 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1196 bfd_mach_sparc_v9m8.
1197 (print_insn_sparc): Handle new operand types.
1198 * sparc-opc.c (MASK_M8): Define.
1200 (v6notlet): Likewise.
1211 (v9andleon): Likewise.
1214 (HWS2_VM8): Likewise.
1215 (sparc_opcode_archs): Add entry for "m8".
1216 (sparc_opcodes): Add OSA2017 and M8 instructions
1217 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1219 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1220 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1221 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1222 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1223 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1224 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1225 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1226 ASI_CORE_SELECT_COMMIT_NHT.
1228 2017-05-18 Alan Modra <amodra@gmail.com>
1230 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1231 * aarch64-dis.c: Likewise.
1232 * aarch64-gen.c: Likewise.
1233 * aarch64-opc.c: Likewise.
1235 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1236 Matthew Fortune <matthew.fortune@imgtec.com>
1238 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1239 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1240 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1241 (print_insn_arg) <OP_REG28>: Add handler.
1242 (validate_insn_args) <OP_REG28>: Handle.
1243 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1244 32-bit encoding and 9-bit immediates.
1245 (print_insn_mips16): Handle MIPS16 instructions that require
1246 32-bit encoding and MFC0/MTC0 operand decoding.
1247 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1248 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1249 (RD_C0, WR_C0, E2, E2MT): New macros.
1250 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1251 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1252 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1253 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1254 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1255 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1256 instructions, "swl", "swr", "sync" and its "sync_acquire",
1257 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1258 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1259 regular/extended entries for original MIPS16 ISA revision
1260 instructions whose extended forms are subdecoded in the MIPS16e2
1261 ISA revision: "li", "sll" and "srl".
1263 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1265 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1266 reference in CP0 move operand decoding.
1268 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1270 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1271 type to hexadecimal.
1272 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1274 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1276 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1277 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1278 "sync_rmb" and "sync_wmb" as aliases.
1279 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1280 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1282 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1284 * arc-dis.c (parse_option): Update quarkse_em option..
1285 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1287 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1289 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1291 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1293 2017-05-01 Michael Clark <michaeljclark@mac.com>
1295 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1298 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1300 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1301 and branches and not synthetic data instructions.
1303 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1305 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1307 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1309 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1310 * arc-opc.c (insert_r13el): New function.
1312 * arc-tbl.h: Add new enter/leave variants.
1314 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1316 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1318 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1320 * mips-dis.c (print_mips_disassembler_options): Add
1323 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1325 * mips16-opc.c (AL): New macro.
1326 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1327 of "ld" and "lw" as aliases.
1329 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1331 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1334 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1335 Alan Modra <amodra@gmail.com>
1337 * ppc-opc.c (ELEV): Define.
1338 (vle_opcodes): Add se_rfgi and e_sc.
1339 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1342 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1344 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1346 2017-04-21 Nick Clifton <nickc@redhat.com>
1349 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1352 2017-04-13 Alan Modra <amodra@gmail.com>
1354 * epiphany-desc.c: Regenerate.
1355 * fr30-desc.c: Regenerate.
1356 * frv-desc.c: Regenerate.
1357 * ip2k-desc.c: Regenerate.
1358 * iq2000-desc.c: Regenerate.
1359 * lm32-desc.c: Regenerate.
1360 * m32c-desc.c: Regenerate.
1361 * m32r-desc.c: Regenerate.
1362 * mep-desc.c: Regenerate.
1363 * mt-desc.c: Regenerate.
1364 * or1k-desc.c: Regenerate.
1365 * xc16x-desc.c: Regenerate.
1366 * xstormy16-desc.c: Regenerate.
1368 2017-04-11 Alan Modra <amodra@gmail.com>
1370 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1371 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1372 PPC_OPCODE_TMR for e6500.
1373 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1374 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1375 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1376 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1377 (PPCHTM): Define as PPC_OPCODE_POWER8.
1378 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1380 2017-04-10 Alan Modra <amodra@gmail.com>
1382 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1383 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1384 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1385 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1387 2017-04-09 Pip Cet <pipcet@gmail.com>
1389 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1390 appropriate floating-point precision directly.
1392 2017-04-07 Alan Modra <amodra@gmail.com>
1394 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1395 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1396 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1397 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1398 vector instructions with E6500 not PPCVEC2.
1400 2017-04-06 Pip Cet <pipcet@gmail.com>
1402 * Makefile.am: Add wasm32-dis.c.
1403 * configure.ac: Add wasm32-dis.c to wasm32 target.
1404 * disassemble.c: Add wasm32 disassembler code.
1405 * wasm32-dis.c: New file.
1406 * Makefile.in: Regenerate.
1407 * configure: Regenerate.
1408 * po/POTFILES.in: Regenerate.
1409 * po/opcodes.pot: Regenerate.
1411 2017-04-05 Pedro Alves <palves@redhat.com>
1413 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1414 * arm-dis.c (parse_arm_disassembler_options): Constify.
1415 * ppc-dis.c (powerpc_init_dialect): Constify local.
1416 * vax-dis.c (parse_disassembler_options): Constify.
1418 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1420 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1423 2017-03-30 Pip Cet <pipcet@gmail.com>
1425 * configure.ac: Add (empty) bfd_wasm32_arch target.
1426 * configure: Regenerate
1427 * po/opcodes.pot: Regenerate.
1429 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1431 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1433 * opcodes/sparc-opc.c (asi_table): New ASIs.
1435 2017-03-29 Alan Modra <amodra@gmail.com>
1437 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1439 (lookup_powerpc): Don't special case -1 dialect. Handle
1441 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1442 lookup_powerpc call, pass it on second.
1444 2017-03-27 Alan Modra <amodra@gmail.com>
1447 * ppc-dis.c (struct ppc_mopt): Comment.
1448 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1450 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1452 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1453 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1454 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1455 (insert_nps_misc_imm_offset): New function.
1456 (extract_nps_misc imm_offset): New function.
1457 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1458 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1460 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1462 * s390-mkopc.c (main): Remove vx2 check.
1463 * s390-opc.txt: Remove vx2 instruction flags.
1465 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1467 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1468 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1469 (insert_nps_imm_offset): New function.
1470 (extract_nps_imm_offset): New function.
1471 (insert_nps_imm_entry): New function.
1472 (extract_nps_imm_entry): New function.
1474 2017-03-17 Alan Modra <amodra@gmail.com>
1477 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1478 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1479 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1481 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1483 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1487 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1489 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1491 2017-03-13 Andrew Waterman <andrew@sifive.com>
1493 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1498 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1500 * i386-gen.c (opcode_modifiers): Replace S with Load.
1501 * i386-opc.h (S): Removed.
1503 (i386_opcode_modifier): Replace s with load.
1504 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1505 and {evex}. Replace S with Load.
1506 * i386-tbl.h: Regenerated.
1508 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1510 * i386-opc.tbl: Use CpuCET on rdsspq.
1511 * i386-tbl.h: Regenerated.
1513 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1515 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1516 <vsx>: Do not use PPC_OPCODE_VSX3;
1518 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1520 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1522 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1524 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1525 (MOD_0F1E_PREFIX_1): Likewise.
1526 (MOD_0F38F5_PREFIX_2): Likewise.
1527 (MOD_0F38F6_PREFIX_0): Likewise.
1528 (RM_0F1E_MOD_3_REG_7): Likewise.
1529 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1530 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1531 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1532 (PREFIX_0F1E): Likewise.
1533 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1534 (PREFIX_0F38F5): Likewise.
1535 (dis386_twobyte): Use PREFIX_0F1E.
1536 (reg_table): Add REG_0F1E_MOD_3.
1537 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1538 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1539 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1540 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1541 (three_byte_table): Use PREFIX_0F38F5.
1542 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1543 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1544 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1545 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1546 PREFIX_MOD_3_0F01_REG_5_RM_2.
1547 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1548 (cpu_flags): Add CpuCET.
1549 * i386-opc.h (CpuCET): New enum.
1550 (CpuUnused): Commented out.
1551 (i386_cpu_flags): Add cpucet.
1552 * i386-opc.tbl: Add Intel CET instructions.
1553 * i386-init.h: Regenerated.
1554 * i386-tbl.h: Likewise.
1556 2017-03-06 Alan Modra <amodra@gmail.com>
1559 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1560 (extract_raq, extract_ras, extract_rbx): New functions.
1561 (powerpc_operands): Use opposite corresponding insert function.
1563 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1564 register restriction.
1566 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1568 * disassemble.c Include "safe-ctype.h".
1569 (disassemble_init_for_target): Handle s390 init.
1570 (remove_whitespace_and_extra_commas): New function.
1571 (disassembler_options_cmp): Likewise.
1572 * arm-dis.c: Include "libiberty.h".
1574 (regnames): Use long disassembler style names.
1575 Add force-thumb and no-force-thumb options.
1576 (NUM_ARM_REGNAMES): Rename from this...
1577 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1578 (get_arm_regname_num_options): Delete.
1579 (set_arm_regname_option): Likewise.
1580 (get_arm_regnames): Likewise.
1581 (parse_disassembler_options): Likewise.
1582 (parse_arm_disassembler_option): Rename from this...
1583 (parse_arm_disassembler_options): ...to this. Make static.
1584 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1585 (print_insn): Use parse_arm_disassembler_options.
1586 (disassembler_options_arm): New function.
1587 (print_arm_disassembler_options): Handle updated regnames.
1588 * ppc-dis.c: Include "libiberty.h".
1589 (ppc_opts): Add "32" and "64" entries.
1590 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1591 (powerpc_init_dialect): Add break to switch statement.
1592 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1593 (disassembler_options_powerpc): New function.
1594 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1595 Remove printing of "32" and "64".
1596 * s390-dis.c: Include "libiberty.h".
1597 (init_flag): Remove unneeded variable.
1598 (struct s390_options_t): New structure type.
1599 (options): New structure.
1600 (init_disasm): Rename from this...
1601 (disassemble_init_s390): ...to this. Add initializations for
1602 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1603 (print_insn_s390): Delete call to init_disasm.
1604 (disassembler_options_s390): New function.
1605 (print_s390_disassembler_options): Print using information from
1607 * po/opcodes.pot: Regenerate.
1609 2017-02-28 Jan Beulich <jbeulich@suse.com>
1611 * i386-dis.c (PCMPESTR_Fixup): New.
1612 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1613 (prefix_table): Use PCMPESTR_Fixup.
1614 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1616 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1617 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1618 Split 64-bit and non-64-bit variants.
1619 * opcodes/i386-tbl.h: Re-generate.
1621 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1623 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1624 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1625 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1626 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1627 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1628 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1629 (OP_SVE_V_HSD): New macros.
1630 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1631 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1632 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1633 (aarch64_opcode_table): Add new SVE instructions.
1634 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1635 for rotation operands. Add new SVE operands.
1636 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1637 (ins_sve_quad_index): Likewise.
1638 (ins_imm_rotate): Split into...
1639 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1640 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1641 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1643 (aarch64_ins_sve_addr_ri_s4): New function.
1644 (aarch64_ins_sve_quad_index): Likewise.
1645 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1646 * aarch64-asm-2.c: Regenerate.
1647 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1648 (ext_sve_quad_index): Likewise.
1649 (ext_imm_rotate): Split into...
1650 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1651 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1652 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1654 (aarch64_ext_sve_addr_ri_s4): New function.
1655 (aarch64_ext_sve_quad_index): Likewise.
1656 (aarch64_ext_sve_index): Allow quad indices.
1657 (do_misc_decoding): Likewise.
1658 * aarch64-dis-2.c: Regenerate.
1659 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1660 aarch64_field_kinds.
1661 (OPD_F_OD_MASK): Widen by one bit.
1662 (OPD_F_NO_ZR): Bump accordingly.
1663 (get_operand_field_width): New function.
1664 * aarch64-opc.c (fields): Add new SVE fields.
1665 (operand_general_constraint_met_p): Handle new SVE operands.
1666 (aarch64_print_operand): Likewise.
1667 * aarch64-opc-2.c: Regenerate.
1669 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1671 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1672 (aarch64_feature_compnum): ...this.
1673 (SIMD_V8_3): Replace with...
1675 (CNUM_INSN): New macro.
1676 (aarch64_opcode_table): Use it for the complex number instructions.
1678 2017-02-24 Jan Beulich <jbeulich@suse.com>
1680 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1682 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1684 Add support for associating SPARC ASIs with an architecture level.
1685 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1686 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1687 decoding of SPARC ASIs.
1689 2017-02-23 Jan Beulich <jbeulich@suse.com>
1691 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1692 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1694 2017-02-21 Jan Beulich <jbeulich@suse.com>
1696 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1697 1 (instead of to itself). Correct typo.
1699 2017-02-14 Andrew Waterman <andrew@sifive.com>
1701 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1704 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1706 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1707 (aarch64_sys_reg_supported_p): Handle them.
1709 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1711 * arc-opc.c (UIMM6_20R): Define.
1712 (SIMM12_20): Use above.
1713 (SIMM12_20R): Define.
1714 (SIMM3_5_S): Use above.
1715 (UIMM7_A32_11R_S): Define.
1716 (UIMM7_9_S): Use above.
1717 (UIMM3_13R_S): Define.
1718 (SIMM11_A32_7_S): Use above.
1720 (UIMM10_A32_8_S): Use above.
1721 (UIMM8_8R_S): Define.
1723 (arc_relax_opcodes): Use all above defines.
1725 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1727 * arc-regs.h: Distinguish some of the registers different on
1728 ARC700 and HS38 cpus.
1730 2017-02-14 Alan Modra <amodra@gmail.com>
1733 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1734 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1736 2017-02-11 Stafford Horne <shorne@gmail.com>
1737 Alan Modra <amodra@gmail.com>
1739 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1740 Use insn_bytes_value and insn_int_value directly instead. Don't
1741 free allocated memory until function exit.
1743 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1745 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1747 2017-02-03 Nick Clifton <nickc@redhat.com>
1750 * aarch64-opc.c (print_register_list): Ensure that the register
1751 list index will fir into the tb buffer.
1752 (print_register_offset_address): Likewise.
1753 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1755 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1758 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1759 instructions when the previous fetch packet ends with a 32-bit
1762 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1764 * pru-opc.c: Remove vague reference to a future GDB port.
1766 2017-01-20 Nick Clifton <nickc@redhat.com>
1768 * po/ga.po: Updated Irish translation.
1770 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1772 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1774 2017-01-13 Yao Qi <yao.qi@linaro.org>
1776 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1777 if FETCH_DATA returns 0.
1778 (m68k_scan_mask): Likewise.
1779 (print_insn_m68k): Update code to handle -1 return value.
1781 2017-01-13 Yao Qi <yao.qi@linaro.org>
1783 * m68k-dis.c (enum print_insn_arg_error): New.
1784 (NEXTBYTE): Replace -3 with
1785 PRINT_INSN_ARG_MEMORY_ERROR.
1786 (NEXTULONG): Likewise.
1787 (NEXTSINGLE): Likewise.
1788 (NEXTDOUBLE): Likewise.
1789 (NEXTDOUBLE): Likewise.
1790 (NEXTPACKED): Likewise.
1791 (FETCH_ARG): Likewise.
1792 (FETCH_DATA): Update comments.
1793 (print_insn_arg): Update comments. Replace magic numbers with
1795 (match_insn_m68k): Likewise.
1797 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1799 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1800 * i386-dis-evex.h (evex_table): Updated.
1801 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1802 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1803 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1804 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1805 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1806 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1807 * i386-init.h: Regenerate.
1808 * i386-tbl.h: Ditto.
1810 2017-01-12 Yao Qi <yao.qi@linaro.org>
1812 * msp430-dis.c (msp430_singleoperand): Return -1 if
1813 msp430dis_opcode_signed returns false.
1814 (msp430_doubleoperand): Likewise.
1815 (msp430_branchinstr): Return -1 if
1816 msp430dis_opcode_unsigned returns false.
1817 (msp430x_calla_instr): Likewise.
1818 (print_insn_msp430): Likewise.
1820 2017-01-05 Nick Clifton <nickc@redhat.com>
1823 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1824 could not be matched.
1825 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1828 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1830 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1831 (aarch64_opcode_table): Use RCPC_INSN.
1833 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1835 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1837 * riscv-opcodes/all-opcodes: Likewise.
1839 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1841 * riscv-dis.c (print_insn_args): Add fall through comment.
1843 2017-01-03 Nick Clifton <nickc@redhat.com>
1845 * po/sr.po: New Serbian translation.
1846 * configure.ac (ALL_LINGUAS): Add sr.
1847 * configure: Regenerate.
1849 2017-01-02 Alan Modra <amodra@gmail.com>
1851 * epiphany-desc.h: Regenerate.
1852 * epiphany-opc.h: Regenerate.
1853 * fr30-desc.h: Regenerate.
1854 * fr30-opc.h: Regenerate.
1855 * frv-desc.h: Regenerate.
1856 * frv-opc.h: Regenerate.
1857 * ip2k-desc.h: Regenerate.
1858 * ip2k-opc.h: Regenerate.
1859 * iq2000-desc.h: Regenerate.
1860 * iq2000-opc.h: Regenerate.
1861 * lm32-desc.h: Regenerate.
1862 * lm32-opc.h: Regenerate.
1863 * m32c-desc.h: Regenerate.
1864 * m32c-opc.h: Regenerate.
1865 * m32r-desc.h: Regenerate.
1866 * m32r-opc.h: Regenerate.
1867 * mep-desc.h: Regenerate.
1868 * mep-opc.h: Regenerate.
1869 * mt-desc.h: Regenerate.
1870 * mt-opc.h: Regenerate.
1871 * or1k-desc.h: Regenerate.
1872 * or1k-opc.h: Regenerate.
1873 * xc16x-desc.h: Regenerate.
1874 * xc16x-opc.h: Regenerate.
1875 * xstormy16-desc.h: Regenerate.
1876 * xstormy16-opc.h: Regenerate.
1878 2017-01-02 Alan Modra <amodra@gmail.com>
1880 Update year range in copyright notice of all files.
1882 For older changes see ChangeLog-2016
1884 Copyright (C) 2017 Free Software Foundation, Inc.
1886 Copying and distribution of this file, with or without modification,
1887 are permitted in any medium without royalty provided the copyright
1888 notice and this notice are preserved.
1894 version-control: never