1 2020-05-11 Alan Modra <amodra@gmail.com>
3 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
4 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
6 2020-05-11 Alan Modra <amodra@gmail.com>
8 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
10 2020-05-11 Alan Modra <amodra@gmail.com>
12 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
13 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
15 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
17 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
20 2020-05-11 Alan Modra <amodra@gmail.com>
22 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
23 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
24 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
25 (prefix_opcodes): Add xxeval.
27 2020-05-11 Alan Modra <amodra@gmail.com>
29 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
30 xxgenpcvwm, xxgenpcvdm.
32 2020-05-11 Alan Modra <amodra@gmail.com>
34 * ppc-opc.c (MP, VXVAM_MASK): Define.
35 (VXVAPS_MASK): Use VXVA_MASK.
36 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
37 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
38 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
39 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
41 2020-05-11 Alan Modra <amodra@gmail.com>
42 Peter Bergner <bergner@linux.ibm.com>
44 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
46 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
47 YMSK2, XA6a, XA6ap, XB6a entries.
48 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
49 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
51 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
52 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
53 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
54 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
55 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
56 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
57 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
58 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
59 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
60 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
61 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
62 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
63 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
64 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
66 2020-05-11 Alan Modra <amodra@gmail.com>
68 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
69 (insert_xts, extract_xts): New functions.
70 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
71 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
72 (VXRC_MASK, VXSH_MASK): Define.
73 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
74 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
75 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
76 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
77 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
78 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
79 xxblendvh, xxblendvw, xxblendvd, xxpermx.
81 2020-05-11 Alan Modra <amodra@gmail.com>
83 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
84 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
85 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
86 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
87 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
89 2020-05-11 Alan Modra <amodra@gmail.com>
91 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
92 (XTP, DQXP, DQXP_MASK): Define.
93 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
94 (prefix_opcodes): Add plxvp and pstxvp.
96 2020-05-11 Alan Modra <amodra@gmail.com>
98 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
99 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
100 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
102 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
104 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
106 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
108 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
110 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
112 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
114 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
116 2020-05-11 Alan Modra <amodra@gmail.com>
118 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
120 2020-05-11 Alan Modra <amodra@gmail.com>
122 * ppc-dis.c (ppc_opts): Add "power10" entry.
123 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
124 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
126 2020-05-11 Nick Clifton <nickc@redhat.com>
128 * po/fr.po: Updated French translation.
130 2020-04-30 Alex Coplan <alex.coplan@arm.com>
132 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
133 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
134 (operand_general_constraint_met_p): validate
135 AARCH64_OPND_UNDEFINED.
136 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
138 * aarch64-asm-2.c: Regenerated.
139 * aarch64-dis-2.c: Regenerated.
140 * aarch64-opc-2.c: Regenerated.
142 2020-04-29 Nick Clifton <nickc@redhat.com>
145 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
148 2020-04-29 Nick Clifton <nickc@redhat.com>
150 * po/sv.po: Updated Swedish translation.
152 2020-04-29 Nick Clifton <nickc@redhat.com>
155 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
156 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
157 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
160 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
163 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
164 cmpi only on m68020up and cpu32.
166 2020-04-20 Sudakshina Das <sudi.das@arm.com>
168 * aarch64-asm.c (aarch64_ins_none): New.
169 * aarch64-asm.h (ins_none): New declaration.
170 * aarch64-dis.c (aarch64_ext_none): New.
171 * aarch64-dis.h (ext_none): New declaration.
172 * aarch64-opc.c (aarch64_print_operand): Update case for
173 AARCH64_OPND_BARRIER_PSB.
174 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
175 (AARCH64_OPERANDS): Update inserter/extracter for
176 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
177 * aarch64-asm-2.c: Regenerated.
178 * aarch64-dis-2.c: Regenerated.
179 * aarch64-opc-2.c: Regenerated.
181 2020-04-20 Sudakshina Das <sudi.das@arm.com>
183 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
184 (aarch64_feature_ras, RAS): Likewise.
185 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
186 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
187 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
188 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
189 * aarch64-asm-2.c: Regenerated.
190 * aarch64-dis-2.c: Regenerated.
191 * aarch64-opc-2.c: Regenerated.
193 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
195 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
196 (print_insn_neon): Support disassembly of conditional
199 2020-02-16 David Faust <david.faust@oracle.com>
201 * bpf-desc.c: Regenerate.
202 * bpf-desc.h: Likewise.
203 * bpf-opc.c: Regenerate.
204 * bpf-opc.h: Likewise.
206 2020-04-07 Lili Cui <lili.cui@intel.com>
208 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
209 (prefix_table): New instructions (see prefixes above).
211 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
212 CPU_ANY_TSXLDTRK_FLAGS.
213 (cpu_flags): Add CpuTSXLDTRK.
214 * i386-opc.h (enum): Add CpuTSXLDTRK.
215 (i386_cpu_flags): Add cputsxldtrk.
216 * i386-opc.tbl: Add XSUSPLDTRK insns.
217 * i386-init.h: Regenerate.
218 * i386-tbl.h: Likewise.
220 2020-04-02 Lili Cui <lili.cui@intel.com>
222 * i386-dis.c (prefix_table): New instructions serialize.
223 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
224 CPU_ANY_SERIALIZE_FLAGS.
225 (cpu_flags): Add CpuSERIALIZE.
226 * i386-opc.h (enum): Add CpuSERIALIZE.
227 (i386_cpu_flags): Add cpuserialize.
228 * i386-opc.tbl: Add SERIALIZE insns.
229 * i386-init.h: Regenerate.
230 * i386-tbl.h: Likewise.
232 2020-03-26 Alan Modra <amodra@gmail.com>
234 * disassemble.h (opcodes_assert): Declare.
235 (OPCODES_ASSERT): Define.
236 * disassemble.c: Don't include assert.h. Include opintl.h.
237 (opcodes_assert): New function.
238 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
239 (bfd_h8_disassemble): Reduce size of data array. Correctly
240 calculate maxlen. Omit insn decoding when insn length exceeds
241 maxlen. Exit from nibble loop when looking for E, before
242 accessing next data byte. Move processing of E outside loop.
243 Replace tests of maxlen in loop with assertions.
245 2020-03-26 Alan Modra <amodra@gmail.com>
247 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
249 2020-03-25 Alan Modra <amodra@gmail.com>
251 * z80-dis.c (suffix): Init mybuf.
253 2020-03-22 Alan Modra <amodra@gmail.com>
255 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
256 successflly read from section.
258 2020-03-22 Alan Modra <amodra@gmail.com>
260 * arc-dis.c (find_format): Use ISO C string concatenation rather
261 than line continuation within a string. Don't access needs_limm
262 before testing opcode != NULL.
264 2020-03-22 Alan Modra <amodra@gmail.com>
266 * ns32k-dis.c (print_insn_arg): Update comment.
267 (print_insn_ns32k): Reduce size of index_offset array, and
268 initialize, passing -1 to print_insn_arg for args that are not
269 an index. Don't exit arg loop early. Abort on bad arg number.
271 2020-03-22 Alan Modra <amodra@gmail.com>
273 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
274 * s12z-opc.c: Formatting.
275 (operands_f): Return an int.
276 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
277 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
278 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
279 (exg_sex_discrim): Likewise.
280 (create_immediate_operand, create_bitfield_operand),
281 (create_register_operand_with_size, create_register_all_operand),
282 (create_register_all16_operand, create_simple_memory_operand),
283 (create_memory_operand, create_memory_auto_operand): Don't
284 segfault on malloc failure.
285 (z_ext24_decode): Return an int status, negative on fail, zero
287 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
288 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
289 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
290 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
291 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
292 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
293 (loop_primitive_decode, shift_decode, psh_pul_decode),
294 (bit_field_decode): Similarly.
295 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
296 to return value, update callers.
297 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
298 Don't segfault on NULL operand.
299 (decode_operation): Return OP_INVALID on first fail.
300 (decode_s12z): Check all reads, returning -1 on fail.
302 2020-03-20 Alan Modra <amodra@gmail.com>
304 * metag-dis.c (print_insn_metag): Don't ignore status from
307 2020-03-20 Alan Modra <amodra@gmail.com>
309 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
310 Initialize parts of buffer not written when handling a possible
311 2-byte insn at end of section. Don't attempt decoding of such
312 an insn by the 4-byte machinery.
314 2020-03-20 Alan Modra <amodra@gmail.com>
316 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
317 partially filled buffer. Prevent lookup of 4-byte insns when
318 only VLE 2-byte insns are possible due to section size. Print
319 ".word" rather than ".long" for 2-byte leftovers.
321 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
324 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
326 2020-03-13 Jan Beulich <jbeulich@suse.com>
328 * i386-dis.c (X86_64_0D): Rename to ...
329 (X86_64_0E): ... this.
331 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
333 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
334 * Makefile.in: Regenerated.
336 2020-03-09 Jan Beulich <jbeulich@suse.com>
338 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
340 * i386-tbl.h: Re-generate.
342 2020-03-09 Jan Beulich <jbeulich@suse.com>
344 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
345 vprot*, vpsha*, and vpshl*.
346 * i386-tbl.h: Re-generate.
348 2020-03-09 Jan Beulich <jbeulich@suse.com>
350 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
351 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
352 * i386-tbl.h: Re-generate.
354 2020-03-09 Jan Beulich <jbeulich@suse.com>
356 * i386-gen.c (set_bitfield): Ignore zero-length field names.
357 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
358 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
359 * i386-tbl.h: Re-generate.
361 2020-03-09 Jan Beulich <jbeulich@suse.com>
363 * i386-gen.c (struct template_arg, struct template_instance,
364 struct template_param, struct template, templates,
365 parse_template, expand_templates): New.
366 (process_i386_opcodes): Various local variables moved to
367 expand_templates. Call parse_template and expand_templates.
368 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
369 * i386-tbl.h: Re-generate.
371 2020-03-06 Jan Beulich <jbeulich@suse.com>
373 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
374 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
375 register and memory source templates. Replace VexW= by VexW*
377 * i386-tbl.h: Re-generate.
379 2020-03-06 Jan Beulich <jbeulich@suse.com>
381 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
382 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
383 * i386-tbl.h: Re-generate.
385 2020-03-06 Jan Beulich <jbeulich@suse.com>
387 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
388 * i386-tbl.h: Re-generate.
390 2020-03-06 Jan Beulich <jbeulich@suse.com>
392 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
393 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
394 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
395 VexW0 on SSE2AVX variants.
396 (vmovq): Drop NoRex64 from XMM/XMM variants.
397 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
398 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
399 applicable use VexW0.
400 * i386-tbl.h: Re-generate.
402 2020-03-06 Jan Beulich <jbeulich@suse.com>
404 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
405 * i386-opc.h (Rex64): Delete.
406 (struct i386_opcode_modifier): Remove rex64 field.
407 * i386-opc.tbl (crc32): Drop Rex64.
408 Replace Rex64 with Size64 everywhere else.
409 * i386-tbl.h: Re-generate.
411 2020-03-06 Jan Beulich <jbeulich@suse.com>
413 * i386-dis.c (OP_E_memory): Exclude recording of used address
414 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
415 addressed memory operands for MPX insns.
417 2020-03-06 Jan Beulich <jbeulich@suse.com>
419 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
420 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
421 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
422 (ptwrite): Split into non-64-bit and 64-bit forms.
423 * i386-tbl.h: Re-generate.
425 2020-03-06 Jan Beulich <jbeulich@suse.com>
427 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
429 * i386-tbl.h: Re-generate.
431 2020-03-04 Jan Beulich <jbeulich@suse.com>
433 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
434 (prefix_table): Move vmmcall here. Add vmgexit.
435 (rm_table): Replace vmmcall entry by prefix_table[] escape.
436 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
437 (cpu_flags): Add CpuSEV_ES entry.
438 * i386-opc.h (CpuSEV_ES): New.
439 (union i386_cpu_flags): Add cpusev_es field.
440 * i386-opc.tbl (vmgexit): New.
441 * i386-init.h, i386-tbl.h: Re-generate.
443 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
445 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
447 * i386-opc.h (IGNORESIZE): New.
448 (DEFAULTSIZE): Likewise.
449 (IgnoreSize): Removed.
450 (DefaultSize): Likewise.
452 (i386_opcode_modifier): Replace ignoresize/defaultsize with
454 * i386-opc.tbl (IgnoreSize): New.
455 (DefaultSize): Likewise.
456 * i386-tbl.h: Regenerated.
458 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
461 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
464 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
467 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
468 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
469 * i386-tbl.h: Regenerated.
471 2020-02-26 Alan Modra <amodra@gmail.com>
473 * aarch64-asm.c: Indent labels correctly.
474 * aarch64-dis.c: Likewise.
475 * aarch64-gen.c: Likewise.
476 * aarch64-opc.c: Likewise.
477 * alpha-dis.c: Likewise.
478 * i386-dis.c: Likewise.
479 * nds32-asm.c: Likewise.
480 * nfp-dis.c: Likewise.
481 * visium-dis.c: Likewise.
483 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
485 * arc-regs.h (int_vector_base): Make it available for all ARC
488 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
490 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
493 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
495 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
496 c.mv/c.li if rs1 is zero.
498 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
500 * i386-gen.c (cpu_flag_init): Replace CpuABM with
501 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
503 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
504 * i386-opc.h (CpuABM): Removed.
506 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
507 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
508 popcnt. Remove CpuABM from lzcnt.
509 * i386-init.h: Regenerated.
510 * i386-tbl.h: Likewise.
512 2020-02-17 Jan Beulich <jbeulich@suse.com>
514 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
515 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
516 VexW1 instead of open-coding them.
517 * i386-tbl.h: Re-generate.
519 2020-02-17 Jan Beulich <jbeulich@suse.com>
521 * i386-opc.tbl (AddrPrefixOpReg): Define.
522 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
523 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
524 templates. Drop NoRex64.
525 * i386-tbl.h: Re-generate.
527 2020-02-17 Jan Beulich <jbeulich@suse.com>
530 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
531 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
532 into Intel syntax instance (with Unpsecified) and AT&T one
534 (vcvtneps2bf16): Likewise, along with folding the two so far
536 * i386-tbl.h: Re-generate.
538 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
540 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
543 2020-02-17 Alan Modra <amodra@gmail.com>
545 * i386-gen.c (cpu_flag_init): Correct last change.
547 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
549 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
552 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
554 * i386-opc.tbl (movsx): Remove Intel syntax comments.
557 2020-02-14 Jan Beulich <jbeulich@suse.com>
560 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
561 destination for Cpu64-only variant.
562 (movzx): Fold patterns.
563 * i386-tbl.h: Re-generate.
565 2020-02-13 Jan Beulich <jbeulich@suse.com>
567 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
568 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
569 CPU_ANY_SSE4_FLAGS entry.
570 * i386-init.h: Re-generate.
572 2020-02-12 Jan Beulich <jbeulich@suse.com>
574 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
575 with Unspecified, making the present one AT&T syntax only.
576 * i386-tbl.h: Re-generate.
578 2020-02-12 Jan Beulich <jbeulich@suse.com>
580 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
581 * i386-tbl.h: Re-generate.
583 2020-02-12 Jan Beulich <jbeulich@suse.com>
586 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
587 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
588 Amd64 and Intel64 templates.
589 (call, jmp): Likewise for far indirect variants. Dro
591 * i386-tbl.h: Re-generate.
593 2020-02-11 Jan Beulich <jbeulich@suse.com>
595 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
596 * i386-opc.h (ShortForm): Delete.
597 (struct i386_opcode_modifier): Remove shortform field.
598 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
599 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
600 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
601 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
603 * i386-tbl.h: Re-generate.
605 2020-02-11 Jan Beulich <jbeulich@suse.com>
607 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
608 fucompi): Drop ShortForm from operand-less templates.
609 * i386-tbl.h: Re-generate.
611 2020-02-11 Alan Modra <amodra@gmail.com>
613 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
614 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
615 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
616 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
617 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
619 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
621 * arm-dis.c (print_insn_cde): Define 'V' parse character.
622 (cde_opcodes): Add VCX* instructions.
624 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
625 Matthew Malcomson <matthew.malcomson@arm.com>
627 * arm-dis.c (struct cdeopcode32): New.
628 (CDE_OPCODE): New macro.
629 (cde_opcodes): New disassembly table.
630 (regnames): New option to table.
631 (cde_coprocs): New global variable.
632 (print_insn_cde): New
633 (print_insn_thumb32): Use print_insn_cde.
634 (parse_arm_disassembler_options): Parse coprocN args.
636 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
639 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
641 * i386-opc.h (AMD64): Removed.
645 (INTEL64ONLY): Likewise.
646 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
647 * i386-opc.tbl (Amd64): New.
649 (Intel64Only): Likewise.
650 Replace AMD64 with Amd64. Update sysenter/sysenter with
651 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
652 * i386-tbl.h: Regenerated.
654 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
657 * z80-dis.c: Add support for GBZ80 opcodes.
659 2020-02-04 Alan Modra <amodra@gmail.com>
661 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
663 2020-02-03 Alan Modra <amodra@gmail.com>
665 * m32c-ibld.c: Regenerate.
667 2020-02-01 Alan Modra <amodra@gmail.com>
669 * frv-ibld.c: Regenerate.
671 2020-01-31 Jan Beulich <jbeulich@suse.com>
673 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
674 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
675 (OP_E_memory): Replace xmm_mdq_mode case label by
676 vex_scalar_w_dq_mode one.
677 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
679 2020-01-31 Jan Beulich <jbeulich@suse.com>
681 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
682 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
683 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
684 (intel_operand_size): Drop vex_w_dq_mode case label.
686 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
688 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
689 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
691 2020-01-30 Alan Modra <amodra@gmail.com>
693 * m32c-ibld.c: Regenerate.
695 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
697 * bpf-opc.c: Regenerate.
699 2020-01-30 Jan Beulich <jbeulich@suse.com>
701 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
702 (dis386): Use them to replace C2/C3 table entries.
703 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
704 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
705 ones. Use Size64 instead of DefaultSize on Intel64 ones.
706 * i386-tbl.h: Re-generate.
708 2020-01-30 Jan Beulich <jbeulich@suse.com>
710 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
712 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
714 * i386-tbl.h: Re-generate.
716 2020-01-30 Alan Modra <amodra@gmail.com>
718 * tic4x-dis.c (tic4x_dp): Make unsigned.
720 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
721 Jan Beulich <jbeulich@suse.com>
724 * i386-dis.c (MOVSXD_Fixup): New function.
725 (movsxd_mode): New enum.
726 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
727 (intel_operand_size): Handle movsxd_mode.
728 (OP_E_register): Likewise.
730 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
731 register on movsxd. Add movsxd with 16-bit destination register
732 for AMD64 and Intel64 ISAs.
733 * i386-tbl.h: Regenerated.
735 2020-01-27 Tamar Christina <tamar.christina@arm.com>
738 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
739 * aarch64-asm-2.c: Regenerate
740 * aarch64-dis-2.c: Likewise.
741 * aarch64-opc-2.c: Likewise.
743 2020-01-21 Jan Beulich <jbeulich@suse.com>
745 * i386-opc.tbl (sysret): Drop DefaultSize.
746 * i386-tbl.h: Re-generate.
748 2020-01-21 Jan Beulich <jbeulich@suse.com>
750 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
752 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
753 * i386-tbl.h: Re-generate.
755 2020-01-20 Nick Clifton <nickc@redhat.com>
757 * po/de.po: Updated German translation.
758 * po/pt_BR.po: Updated Brazilian Portuguese translation.
759 * po/uk.po: Updated Ukranian translation.
761 2020-01-20 Alan Modra <amodra@gmail.com>
763 * hppa-dis.c (fput_const): Remove useless cast.
765 2020-01-20 Alan Modra <amodra@gmail.com>
767 * arm-dis.c (print_insn_arm): Wrap 'T' value.
769 2020-01-18 Nick Clifton <nickc@redhat.com>
771 * configure: Regenerate.
772 * po/opcodes.pot: Regenerate.
774 2020-01-18 Nick Clifton <nickc@redhat.com>
776 Binutils 2.34 branch created.
778 2020-01-17 Christian Biesinger <cbiesinger@google.com>
780 * opintl.h: Fix spelling error (seperate).
782 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
784 * i386-opc.tbl: Add {vex} pseudo prefix.
785 * i386-tbl.h: Regenerated.
787 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
790 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
791 (neon_opcodes): Likewise.
792 (select_arm_features): Make sure we enable MVE bits when selecting
793 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
796 2020-01-16 Jan Beulich <jbeulich@suse.com>
798 * i386-opc.tbl: Drop stale comment from XOP section.
800 2020-01-16 Jan Beulich <jbeulich@suse.com>
802 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
803 (extractps): Add VexWIG to SSE2AVX forms.
804 * i386-tbl.h: Re-generate.
806 2020-01-16 Jan Beulich <jbeulich@suse.com>
808 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
809 Size64 from and use VexW1 on SSE2AVX forms.
810 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
811 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
812 * i386-tbl.h: Re-generate.
814 2020-01-15 Alan Modra <amodra@gmail.com>
816 * tic4x-dis.c (tic4x_version): Make unsigned long.
817 (optab, optab_special, registernames): New file scope vars.
818 (tic4x_print_register): Set up registernames rather than
819 malloc'd registertable.
820 (tic4x_disassemble): Delete optable and optable_special. Use
821 optab and optab_special instead. Throw away old optab,
822 optab_special and registernames when info->mach changes.
824 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
827 * z80-dis.c (suffix): Use .db instruction to generate double
830 2020-01-14 Alan Modra <amodra@gmail.com>
832 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
833 values to unsigned before shifting.
835 2020-01-13 Thomas Troeger <tstroege@gmx.de>
837 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
839 (print_insn_thumb16, print_insn_thumb32): Likewise.
840 (print_insn): Initialize the insn info.
841 * i386-dis.c (print_insn): Initialize the insn info fields, and
844 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
846 * arc-opc.c (C_NE): Make it required.
848 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
850 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
851 reserved register name.
853 2020-01-13 Alan Modra <amodra@gmail.com>
855 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
856 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
858 2020-01-13 Alan Modra <amodra@gmail.com>
860 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
861 result of wasm_read_leb128 in a uint64_t and check that bits
862 are not lost when copying to other locals. Use uint32_t for
863 most locals. Use PRId64 when printing int64_t.
865 2020-01-13 Alan Modra <amodra@gmail.com>
867 * score-dis.c: Formatting.
868 * score7-dis.c: Formatting.
870 2020-01-13 Alan Modra <amodra@gmail.com>
872 * score-dis.c (print_insn_score48): Use unsigned variables for
873 unsigned values. Don't left shift negative values.
874 (print_insn_score32): Likewise.
875 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
877 2020-01-13 Alan Modra <amodra@gmail.com>
879 * tic4x-dis.c (tic4x_print_register): Remove dead code.
881 2020-01-13 Alan Modra <amodra@gmail.com>
883 * fr30-ibld.c: Regenerate.
885 2020-01-13 Alan Modra <amodra@gmail.com>
887 * xgate-dis.c (print_insn): Don't left shift signed value.
888 (ripBits): Formatting, use 1u.
890 2020-01-10 Alan Modra <amodra@gmail.com>
892 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
893 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
895 2020-01-10 Alan Modra <amodra@gmail.com>
897 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
898 and XRREG value earlier to avoid a shift with negative exponent.
899 * m10200-dis.c (disassemble): Similarly.
901 2020-01-09 Nick Clifton <nickc@redhat.com>
904 * z80-dis.c (ld_ii_ii): Use correct cast.
906 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
909 * z80-dis.c (ld_ii_ii): Use character constant when checking
912 2020-01-09 Jan Beulich <jbeulich@suse.com>
914 * i386-dis.c (SEP_Fixup): New.
916 (dis386_twobyte): Use it for sysenter/sysexit.
917 (enum x86_64_isa): Change amd64 enumerator to value 1.
918 (OP_J): Compare isa64 against intel64 instead of amd64.
919 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
921 * i386-tbl.h: Re-generate.
923 2020-01-08 Alan Modra <amodra@gmail.com>
925 * z8k-dis.c: Include libiberty.h
926 (instr_data_s): Make max_fetched unsigned.
927 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
928 Don't exceed byte_info bounds.
929 (output_instr): Make num_bytes unsigned.
930 (unpack_instr): Likewise for nibl_count and loop.
931 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
933 * z8k-opc.h: Regenerate.
935 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
937 * arc-tbl.h (llock): Use 'LLOCK' as class.
939 (scond): Use 'SCOND' as class.
941 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
944 2020-01-06 Alan Modra <amodra@gmail.com>
946 * m32c-ibld.c: Regenerate.
948 2020-01-06 Alan Modra <amodra@gmail.com>
951 * z80-dis.c (suffix): Don't use a local struct buffer copy.
952 Peek at next byte to prevent recursion on repeated prefix bytes.
953 Ensure uninitialised "mybuf" is not accessed.
954 (print_insn_z80): Don't zero n_fetch and n_used here,..
955 (print_insn_z80_buf): ..do it here instead.
957 2020-01-04 Alan Modra <amodra@gmail.com>
959 * m32r-ibld.c: Regenerate.
961 2020-01-04 Alan Modra <amodra@gmail.com>
963 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
965 2020-01-04 Alan Modra <amodra@gmail.com>
967 * crx-dis.c (match_opcode): Avoid shift left of signed value.
969 2020-01-04 Alan Modra <amodra@gmail.com>
971 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
973 2020-01-03 Jan Beulich <jbeulich@suse.com>
975 * aarch64-tbl.h (aarch64_opcode_table): Use
976 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
978 2020-01-03 Jan Beulich <jbeulich@suse.com>
980 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
981 forms of SUDOT and USDOT.
983 2020-01-03 Jan Beulich <jbeulich@suse.com>
985 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
987 * opcodes/aarch64-dis-2.c: Re-generate.
989 2020-01-03 Jan Beulich <jbeulich@suse.com>
991 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
993 * opcodes/aarch64-dis-2.c: Re-generate.
995 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
997 * z80-dis.c: Add support for eZ80 and Z80 instructions.
999 2020-01-01 Alan Modra <amodra@gmail.com>
1001 Update year range in copyright notice of all files.
1003 For older changes see ChangeLog-2019
1005 Copyright (C) 2020 Free Software Foundation, Inc.
1007 Copying and distribution of this file, with or without modification,
1008 are permitted in any medium without royalty provided the copyright
1009 notice and this notice are preserved.
1015 version-control: never