opcodes/ChangeLog

   1 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
   4         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
   5         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
   6         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
   7         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
   8         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
   9         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
  10         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
  11         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
  12         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
  13         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
  14         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
  15         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
  16         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
  17         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
  18         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
  19         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
  20         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
  21         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
  22         Changed opcodes.
  23         (prealloc, prefetch*): Place them before ld instruction.
  24         * arc-opc.c (skip_this_opcode): Add ARITH class.
  25
  26 2017-10-25  Alan Modra  <amodra@gmail.com>
  27
  28         PR 22348
  29         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
  30         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
  31         (imm4flag, size_changed): Likewise.
  32         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
  33         (words, allWords, processing_argument_number): Likewise.
  34         (cst4flag, size_changed): Likewise.
  35         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
  36         (crx_cst4_maps): Rename from cst4_maps.
  37         (crx_no_op_insn): Rename from no_op_insn.
  38
  39 2017-10-24  Andrew Waterman  <andrew@sifive.com>
  40
  41         * riscv-opc.c (match_c_addi16sp) : New function.
  42         (match_c_addi4spn): New function.
  43         (match_c_lui): Don't allow 0-immediate encodings.
  44         (riscv_opcodes) <addi>: Use the above functions.
  45         <add>: Likewise.
  46         <c.addi4spn>: Likewise.
  47         <c.addi16sp>: Likewise.
  48
  49 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  50
  51         * i386-init.h: Regenerate
  52         * i386-tbl.h: Likewise
  53
  54 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  55
  56         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
  57         (enum): Add EVEX_W_0F3854_P_2.
  58         * i386-dis-evex.h (evex_table): Updated.
  59         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
  60         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  61         (cpu_flags): Add CpuAVX512_BITALG.
  62         * i386-opc.h (enum): Add CpuAVX512_BITALG.
  63         (i386_cpu_flags): Add cpuavx512_bitalg..
  64         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
  65         * i386-init.h: Regenerate.
  66         * i386-tbl.h: Likewise.
  67
  68 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  69
  70         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
  71         * i386-dis-evex.h (evex_table): Updated.
  72         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
  73         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
  74         (cpu_flags): Add CpuAVX512_VNNI.
  75         * i386-opc.h (enum): Add CpuAVX512_VNNI.
  76         (i386_cpu_flags): Add cpuavx512_vnni.
  77         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
  78         * i386-init.h: Regenerate.
  79         * i386-tbl.h: Likewise.
  80
  81 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  82
  83         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
  84         (enum): Remove VEX_LEN_0F3A44_P_2.
  85         (vex_len_table): Ditto.
  86         (enum): Remove VEX_W_0F3A44_P_2.
  87         (vew_w_table): Ditto.
  88         (prefix_table): Adjust instructions (see prefixes above).
  89         * i386-dis-evex.h (evex_table):
  90         Add new instructions (see prefixes above).
  91         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
  92         (bitfield_cpu_flags): Ditto.
  93         * i386-opc.h (enum): Ditto.
  94         (i386_cpu_flags): Ditto.
  95         (CpuUnused): Comment out to avoid zero-width field problem.
  96         * i386-opc.tbl (vpclmulqdq): New instruction.
  97         * i386-init.h: Regenerate.
  98         * i386-tbl.h: Ditto.
  99
 100 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 101
 102         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 103         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 104         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 105         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 106         (vex_len_table): Ditto.
 107         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 108         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 109         (vew_w_table): Ditto.
 110         (prefix_table): Adjust instructions (see prefixes above).
 111         * i386-dis-evex.h (evex_table):
 112         Add new instructions (see prefixes above).
 113         * i386-gen.c (cpu_flag_init): Add VAES.
 114         (bitfield_cpu_flags): Ditto.
 115         * i386-opc.h (enum): Ditto.
 116         (i386_cpu_flags): Ditto.
 117         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 118         * i386-init.h: Regenerate.
 119         * i386-tbl.h: Ditto.
 120
 121 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 122
 123         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 124         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 125         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 126         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 127         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 128         (prefix_table): Updated (see prefixes above).
 129         (three_byte_table): Likewise.
 130         (vex_w_table): Likewise.
 131         * i386-dis-evex.h: Likewise.
 132         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 133         (cpu_flags): Add CpuGFNI.
 134         * i386-opc.h (enum): Add CpuGFNI.
 135         (i386_cpu_flags): Add cpugfni.
 136         * i386-opc.tbl: Add Intel GFNI instructions.
 137         * i386-init.h: Regenerate.
 138         * i386-tbl.h: Likewise.
 139
 140 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 141
 142         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 143         Define EXbScalar and EXwScalar for OP_EX.
 144         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 145         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 146         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 147         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 148         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 149         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 150         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 151         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 152         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 153         (OP_E_memory): Likewise.
 154         * i386-dis-evex.h: Updated.
 155         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 156         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 157         (cpu_flags): Add CpuAVX512_VBMI2.
 158         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 159         (i386_cpu_flags): Add cpuavx512_vbmi2.
 160         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 161         * i386-init.h: Regenerate.
 162         * i386-tbl.h: Likewise.
 163
 164 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 165
 166         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 167
 168 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 169
 170         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 171         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 172         K15. Add jmpix pattern.
 173
 174 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 175
 176         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 177
 178 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 179
 180         * s390-opc.c (INSTR_SI_RD): New macro.
 181         (INSTR_S_RD): Adjust example instruction.
 182         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 183         SI_RD.
 184
 185 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 186
 187         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 188         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 189         VLE multimple load/store instructions. Old e_ldm* variants are
 190         kept as aliases.
 191         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 192
 193 2017-09-27  Nick Clifton  <nickc@redhat.com>
 194
 195         PR 22179
 196         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 197         names for the fmv.x.s and fmv.s.x instructions respectively.
 198
 199 2017-09-26  do  <do@nerilex.org>
 200
 201         PR 22123
 202         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 203         be used on CPUs that have emacs support.
 204
 205 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 206
 207         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 208
 209 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 210
 211         * nds32-asm.c: Rename __BIT() to N32_BIT().
 212         * nds32-asm.h: Likewise.
 213         * nds32-dis.c: Likewise.
 214
 215 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         * i386-dis.c (last_active_prefix): Removed.
 218         (ckprefix): Don't set last_active_prefix.
 219         (NOTRACK_Fixup): Don't check last_active_prefix.
 220
 221 2017-08-31  Nick Clifton  <nickc@redhat.com>
 222
 223         * po/fr.po: Updated French translation.
 224
 225 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 226
 227         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 228         fields.
 229
 230 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 231             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 232
 233         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 234         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 235         New entries efs2 and spe2.
 236         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 237         (SPE2_OPCD_SEGS): New macro.
 238         (spe2_opcd_indices): New.
 239         (disassemble_init_powerpc): Handle SPE2 opcodes.
 240         (lookup_spe2): New function.
 241         (print_insn_powerpc): call lookup_spe2.
 242         * ppc-opc.c (insert_evuimm1_ex0): New function.
 243         (extract_evuimm1_ex0): Likewise.
 244         (insert_evuimm_lt8): Likewise.
 245         (extract_evuimm_lt8): Likewise.
 246         (insert_off_spe2): Likewise.
 247         (extract_off_spe2): Likewise.
 248         (insert_Ddd): Likewise.
 249         (extract_Ddd): Likewise.
 250         (DD): New operand.
 251         (EVUIMM_LT8): Likewise.
 252         (EVUIMM_LT16): Adjust.
 253         (MMMM): New operand.
 254         (EVUIMM_1): Likewise.
 255         (EVUIMM_1_EX0): Likewise.
 256         (EVUIMM_2): Adjust.
 257         (NNN): New operand.
 258         (VX_OFF_SPE2): Likewise.
 259         (BBB): Likewise.
 260         (DDD): Likewise.
 261         (VX_MASK_DDD): New mask.
 262         (HH): New operand.
 263         (VX_RA_CONST): New macro.
 264         (VX_RA_CONST_MASK): Likewise.
 265         (VX_RB_CONST): Likewise.
 266         (VX_RB_CONST_MASK): Likewise.
 267         (VX_OFF_SPE2_MASK): Likewise.
 268         (VX_SPE_CRFD): Likewise.
 269         (VX_SPE_CRFD_MASK VX): Likewise.
 270         (VX_SPE2_CLR): Likewise.
 271         (VX_SPE2_CLR_MASK): Likewise.
 272         (VX_SPE2_SPLATB): Likewise.
 273         (VX_SPE2_SPLATB_MASK): Likewise.
 274         (VX_SPE2_OCTET): Likewise.
 275         (VX_SPE2_OCTET_MASK): Likewise.
 276         (VX_SPE2_DDHH): Likewise.
 277         (VX_SPE2_DDHH_MASK): Likewise.
 278         (VX_SPE2_HH): Likewise.
 279         (VX_SPE2_HH_MASK): Likewise.
 280         (VX_SPE2_EVMAR): Likewise.
 281         (VX_SPE2_EVMAR_MASK): Likewise.
 282         (PPCSPE2): Likewise.
 283         (PPCEFS2): Likewise.
 284         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 285         (powerpc_macros): Map old SPE instructions have new names
 286         with the same opcodes. Add SPE2 instructions which just are
 287         mapped to SPE2.
 288         (spe2_opcodes): Add SPE2 opcodes.
 289
 290 2017-08-23  Alan Modra  <amodra@gmail.com>
 291
 292         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 293         extract functions earlier, deleting forward declarations.
 294         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 295         RA_MASK.
 296
 297 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 298
 299         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 300
 301 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 302             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 303
 304         * ppc-opc.c (insert_evuimm2_ex0): New function.
 305         (extract_evuimm2_ex0): Likewise.
 306         (insert_evuimm4_ex0): Likewise.
 307         (extract_evuimm4_ex0): Likewise.
 308         (insert_evuimm8_ex0): Likewise.
 309         (extract_evuimm8_ex0): Likewise.
 310         (insert_evuimm_lt16): Likewise.
 311         (extract_evuimm_lt16): Likewise.
 312         (insert_rD_rS_even): Likewise.
 313         (extract_rD_rS_even): Likewise.
 314         (insert_off_lsp): Likewise.
 315         (extract_off_lsp): Likewise.
 316         (RD_EVEN): New operand.
 317         (RS_EVEN): Likewise.
 318         (RSQ): Adjust.
 319         (EVUIMM_LT16): New operand.
 320         (HTM_SI): Adjust.
 321         (EVUIMM_2_EX0): New operand.
 322         (EVUIMM_4): Adjust.
 323         (EVUIMM_4_EX0): New operand.
 324         (EVUIMM_8): Adjust.
 325         (EVUIMM_8_EX0): New operand.
 326         (WS): Adjust.
 327         (VX_OFF): New operand.
 328         (VX_LSP): New macro.
 329         (VX_LSP_MASK): Likewise.
 330         (VX_LSP_OFF_MASK): Likewise.
 331         (PPC_OPCODE_LSP): Likewise.
 332         (vle_opcodes): Add LSP opcodes.
 333         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 334
 335 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 336
 337         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 338         register operands in CRC instructions.
 339         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 340         comments.
 341
 342 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 343
 344         * disassemble.c (disassembler): Mark big and mach with
 345         ATTRIBUTE_UNUSED.
 346
 347 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 348
 349         * disassemble.c (disassembler): Remove arch/mach/endian
 350         assertions.
 351
 352 2017-07-25  Nick Clifton  <nickc@redhat.com>
 353
 354         PR 21739
 355         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 356         message.
 357         (insert_r0): Likewise.
 358         (insert_r1): Likewise.
 359         (insert_r2): Likewise.
 360         (insert_r3): Likewise.
 361         (insert_sp): Likewise.
 362         (insert_gp): Likewise.
 363         (insert_pcl): Likewise.
 364         (insert_blink): Likewise.
 365         (insert_ilink1): Likewise.
 366         (insert_ilink2): Likewise.
 367         (insert_ras): Likewise.
 368         (insert_rbs): Likewise.
 369         (insert_rcs): Likewise.
 370         (insert_simm3s): Likewise.
 371         (insert_rrange): Likewise.
 372         (insert_r13el): Likewise.
 373         (insert_fpel): Likewise.
 374         (insert_blinkel): Likewise.
 375         (insert_pclel): Likewise.
 376         (insert_nps_bitop_size_2b): Likewise.
 377         (insert_nps_imm_offset): Likewise.
 378         (insert_nps_imm_entry): Likewise.
 379         (insert_nps_size_16bit): Likewise.
 380         (insert_nps_##NAME##_pos): Likewise.
 381         (insert_nps_##NAME): Likewise.
 382         (insert_nps_bitop_ins_ext): Likewise.
 383         (insert_nps_##NAME): Likewise.
 384         (insert_nps_min_hofs): Likewise.
 385         (insert_nps_##NAME): Likewise.
 386         (insert_nps_rbdouble_64): Likewise.
 387         (insert_nps_misc_imm_offset): Likewise.
 388         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 389         option description.
 390
 391 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 392             Jiong Wang  <jiong.wang@arm.com>
 393
 394         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 395         correct the print.
 396         * aarch64-dis-2.c: Regenerated.
 397
 398 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 399
 400         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 401         table.
 402
 403 2017-07-20  Nick Clifton  <nickc@redhat.com>
 404
 405         * po/de.po: Updated German translation.
 406
 407 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 408
 409         * arc-regs.h (sec_stat): New aux register.
 410         (aux_kernel_sp): Likewise.
 411         (aux_sec_u_sp): Likewise.
 412         (aux_sec_k_sp): Likewise.
 413         (sec_vecbase_build): Likewise.
 414         (nsc_table_top): Likewise.
 415         (nsc_table_base): Likewise.
 416         (ersec_stat): Likewise.
 417         (aux_sec_except): Likewise.
 418
 419 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 420
 421         * arc-opc.c (extract_uimm12_20): New function.
 422         (UIMM12_20): New operand.
 423         (SIMM3_5_S): Adjust.
 424         * arc-tbl.h (sjli): Add new instruction.
 425
 426 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 427             John Eric Martin  <John.Martin@emmicro-us.com>
 428
 429         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 430         (UIMM3_23): Adjust accordingly.
 431         * arc-regs.h: Add/correct jli_base register.
 432         * arc-tbl.h (jli_s): Likewise.
 433
 434 2017-07-18  Nick Clifton  <nickc@redhat.com>
 435
 436         PR 21775
 437         * aarch64-opc.c: Fix spelling typos.
 438         * i386-dis.c: Likewise.
 439
 440 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 441
 442         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 443         max_addr_offset and octets variables to size_t.
 444
 445 2017-07-12  Alan Modra  <amodra@gmail.com>
 446
 447         * po/da.po: Update from translationproject.org/latest/opcodes/.
 448         * po/de.po: Likewise.
 449         * po/es.po: Likewise.
 450         * po/fi.po: Likewise.
 451         * po/fr.po: Likewise.
 452         * po/id.po: Likewise.
 453         * po/it.po: Likewise.
 454         * po/nl.po: Likewise.
 455         * po/pt_BR.po: Likewise.
 456         * po/ro.po: Likewise.
 457         * po/sv.po: Likewise.
 458         * po/tr.po: Likewise.
 459         * po/uk.po: Likewise.
 460         * po/vi.po: Likewise.
 461         * po/zh_CN.po: Likewise.
 462
 463 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 464             Alan Modra  <amodra@gmail.com>
 465
 466         * cgen.sh: Mark generated files read-only.
 467         * epiphany-asm.c: Regenerate.
 468         * epiphany-desc.c: Regenerate.
 469         * epiphany-desc.h: Regenerate.
 470         * epiphany-dis.c: Regenerate.
 471         * epiphany-ibld.c: Regenerate.
 472         * epiphany-opc.c: Regenerate.
 473         * epiphany-opc.h: Regenerate.
 474         * fr30-asm.c: Regenerate.
 475         * fr30-desc.c: Regenerate.
 476         * fr30-desc.h: Regenerate.
 477         * fr30-dis.c: Regenerate.
 478         * fr30-ibld.c: Regenerate.
 479         * fr30-opc.c: Regenerate.
 480         * fr30-opc.h: Regenerate.
 481         * frv-asm.c: Regenerate.
 482         * frv-desc.c: Regenerate.
 483         * frv-desc.h: Regenerate.
 484         * frv-dis.c: Regenerate.
 485         * frv-ibld.c: Regenerate.
 486         * frv-opc.c: Regenerate.
 487         * frv-opc.h: Regenerate.
 488         * ip2k-asm.c: Regenerate.
 489         * ip2k-desc.c: Regenerate.
 490         * ip2k-desc.h: Regenerate.
 491         * ip2k-dis.c: Regenerate.
 492         * ip2k-ibld.c: Regenerate.
 493         * ip2k-opc.c: Regenerate.
 494         * ip2k-opc.h: Regenerate.
 495         * iq2000-asm.c: Regenerate.
 496         * iq2000-desc.c: Regenerate.
 497         * iq2000-desc.h: Regenerate.
 498         * iq2000-dis.c: Regenerate.
 499         * iq2000-ibld.c: Regenerate.
 500         * iq2000-opc.c: Regenerate.
 501         * iq2000-opc.h: Regenerate.
 502         * lm32-asm.c: Regenerate.
 503         * lm32-desc.c: Regenerate.
 504         * lm32-desc.h: Regenerate.
 505         * lm32-dis.c: Regenerate.
 506         * lm32-ibld.c: Regenerate.
 507         * lm32-opc.c: Regenerate.
 508         * lm32-opc.h: Regenerate.
 509         * lm32-opinst.c: Regenerate.
 510         * m32c-asm.c: Regenerate.
 511         * m32c-desc.c: Regenerate.
 512         * m32c-desc.h: Regenerate.
 513         * m32c-dis.c: Regenerate.
 514         * m32c-ibld.c: Regenerate.
 515         * m32c-opc.c: Regenerate.
 516         * m32c-opc.h: Regenerate.
 517         * m32r-asm.c: Regenerate.
 518         * m32r-desc.c: Regenerate.
 519         * m32r-desc.h: Regenerate.
 520         * m32r-dis.c: Regenerate.
 521         * m32r-ibld.c: Regenerate.
 522         * m32r-opc.c: Regenerate.
 523         * m32r-opc.h: Regenerate.
 524         * m32r-opinst.c: Regenerate.
 525         * mep-asm.c: Regenerate.
 526         * mep-desc.c: Regenerate.
 527         * mep-desc.h: Regenerate.
 528         * mep-dis.c: Regenerate.
 529         * mep-ibld.c: Regenerate.
 530         * mep-opc.c: Regenerate.
 531         * mep-opc.h: Regenerate.
 532         * mt-asm.c: Regenerate.
 533         * mt-desc.c: Regenerate.
 534         * mt-desc.h: Regenerate.
 535         * mt-dis.c: Regenerate.
 536         * mt-ibld.c: Regenerate.
 537         * mt-opc.c: Regenerate.
 538         * mt-opc.h: Regenerate.
 539         * or1k-asm.c: Regenerate.
 540         * or1k-desc.c: Regenerate.
 541         * or1k-desc.h: Regenerate.
 542         * or1k-dis.c: Regenerate.
 543         * or1k-ibld.c: Regenerate.
 544         * or1k-opc.c: Regenerate.
 545         * or1k-opc.h: Regenerate.
 546         * or1k-opinst.c: Regenerate.
 547         * xc16x-asm.c: Regenerate.
 548         * xc16x-desc.c: Regenerate.
 549         * xc16x-desc.h: Regenerate.
 550         * xc16x-dis.c: Regenerate.
 551         * xc16x-ibld.c: Regenerate.
 552         * xc16x-opc.c: Regenerate.
 553         * xc16x-opc.h: Regenerate.
 554         * xstormy16-asm.c: Regenerate.
 555         * xstormy16-desc.c: Regenerate.
 556         * xstormy16-desc.h: Regenerate.
 557         * xstormy16-dis.c: Regenerate.
 558         * xstormy16-ibld.c: Regenerate.
 559         * xstormy16-opc.c: Regenerate.
 560         * xstormy16-opc.h: Regenerate.
 561
 562 2017-07-07  Alan Modra  <amodra@gmail.com>
 563
 564         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 565         * m32c-dis.c: Regenerate.
 566         * mep-dis.c: Regenerate.
 567
 568 2017-07-05  Borislav Petkov  <bp@suse.de>
 569
 570         * i386-dis.c: Enable ModRM.reg /6 aliases.
 571
 572 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 573
 574         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 575         with vmrs and vmsr.
 576
 577 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 578
 579         * configure: Regenerate.
 580
 581 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 582
 583         * po/opcodes.pot: Regenerate.
 584
 585 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 586
 587         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 588         entries to the MSA ASE instruction block.
 589
 590 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 591             Maciej W. Rozycki  <macro@imgtec.com>
 592
 593         * micromips-opc.c (XPA, XPAVZ): New macros.
 594         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 595         "mthgc0".
 596
 597 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 598             Maciej W. Rozycki  <macro@imgtec.com>
 599
 600         * micromips-opc.c (I36): New macro.
 601         (micromips_opcodes): Add "eretnc".
 602
 603 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 604             Andrew Bennett  <andrew.bennett@imgtec.com>
 605
 606         * mips-dis.c (mips_calculate_combination_ases): Handle the
 607         ASE_XPA_VIRT flag.
 608         (parse_mips_ase_option): New function.
 609         (parse_mips_dis_option): Factor out ASE option handling to the
 610         new function.  Call `mips_calculate_combination_ases'.
 611         * mips-opc.c (XPAVZ): New macro.
 612         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 613         "mfhgc0", "mthc0" and "mthgc0".
 614
 615 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 616
 617         * mips-dis.c (mips_calculate_combination_ases): New function.
 618         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 619         calculation to the new function.
 620         (set_default_mips_dis_options): Call the new function.
 621
 622 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 623
 624         * arc-dis.c (parse_disassembler_options): Use
 625         FOR_EACH_DISASSEMBLER_OPTION.
 626
 627 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 628
 629         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 630         disassembler option strings.
 631         (parse_cpu_option): Likewise.
 632
 633 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 634
 635         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 636         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 637         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 638         (aarch64_feature_dotprod, DOT_INSN): New.
 639         (udot, sdot): New.
 640         * aarch64-dis-2.c: Regenerated.
 641
 642 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 643
 644         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 645
 646 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 647             Matthew Fortune  <matthew.fortune@imgtec.com>
 648             Andrew Bennett  <andrew.bennett@imgtec.com>
 649
 650         * mips-formats.h (INT_BIAS): New macro.
 651         (INT_ADJ): Redefine in INT_BIAS terms.
 652         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 653         (mips_print_save_restore): New function.
 654         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 655         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 656         call.
 657         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 658         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 659         OP_SAVE_RESTORE_LIST handling, factored out from here.
 660         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 661         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 662         (mips_builtin_opcodes): Add "restore" and "save" entries.
 663         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 664         (IAMR2): New macro.
 665         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 666
 667 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 668
 669         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 670         alias; do not mark SLTI instruction as an alias.
 671
 672 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 673
 674         * i386-dis.c (RM_0FAE_REG_5): Removed.
 675         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 676         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 677         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 678         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 679         PREFIX_MOD_3_0F01_REG_5_RM_0.
 680         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 681         PREFIX_MOD_3_0FAE_REG_5.
 682         (mod_table): Update MOD_0FAE_REG_5.
 683         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 684         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 685         * i386-tbl.h: Regenerated.
 686
 687 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 688
 689         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 690         * i386-opc.tbl: Likewise.
 691         * i386-tbl.h: Regenerated.
 692
 693 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 694
 695         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 696         and "jmp{&|}".
 697         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 698         prefix.
 699
 700 2017-06-19  Nick Clifton  <nickc@redhat.com>
 701
 702         PR binutils/21614
 703         * score-dis.c (score_opcodes): Add sentinel.
 704
 705 2017-06-16  Alan Modra  <amodra@gmail.com>
 706
 707         * rx-decode.c: Regenerate.
 708
 709 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 710
 711         PR binutils/21594
 712         * i386-dis.c (OP_E_register): Check valid bnd register.
 713         (OP_G): Likewise.
 714
 715 2017-06-15  Nick Clifton  <nickc@redhat.com>
 716
 717         PR binutils/21595
 718         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 719         range value.
 720
 721 2017-06-15  Nick Clifton  <nickc@redhat.com>
 722
 723         PR binutils/21588
 724         * rl78-decode.opc (OP_BUF_LEN): Define.
 725         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 726         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 727         array.
 728         * rl78-decode.c: Regenerate.
 729
 730 2017-06-15  Nick Clifton  <nickc@redhat.com>
 731
 732         PR binutils/21586
 733         * bfin-dis.c (gregs): Clip index to prevent overflow.
 734         (regs): Likewise.
 735         (regs_lo): Likewise.
 736         (regs_hi): Likewise.
 737
 738 2017-06-14  Nick Clifton  <nickc@redhat.com>
 739
 740         PR binutils/21576
 741         * score7-dis.c (score_opcodes): Add sentinel.
 742
 743 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 744
 745         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 746         * arm-dis.c: Likewise.
 747         * ia64-dis.c: Likewise.
 748         * mips-dis.c: Likewise.
 749         * spu-dis.c: Likewise.
 750         * disassemble.h (print_insn_aarch64): New declaration, moved from
 751         include/dis-asm.h.
 752         (print_insn_big_arm, print_insn_big_mips): Likewise.
 753         (print_insn_i386, print_insn_ia64): Likewise.
 754         (print_insn_little_arm, print_insn_little_mips): Likewise.
 755
 756 2017-06-14  Nick Clifton  <nickc@redhat.com>
 757
 758         PR binutils/21587
 759         * rx-decode.opc: Include libiberty.h
 760         (GET_SCALE): New macro - validates access to SCALE array.
 761         (GET_PSCALE): New macro - validates access to PSCALE array.
 762         (DIs, SIs, S2Is, rx_disp): Use new macros.
 763         * rx-decode.c: Regenerate.
 764
 765 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 766
 767         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 768
 769 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 770
 771         * arc-dis.c (enforced_isa_mask): Declare.
 772         (cpu_types): Likewise.
 773         (parse_cpu_option): New function.
 774         (parse_disassembler_options): Use it.
 775         (print_insn_arc): Use enforced_isa_mask.
 776         (print_arc_disassembler_options): Document new options.
 777
 778 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 779
 780         * alpha-dis.c: Include disassemble.h, don't include
 781         dis-asm.h.
 782         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 783         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 784         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 785         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 786         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 787         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 788         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 789         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 790         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 791         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 792         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 793         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 794         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 795         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 796         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 797         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 798         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 799         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 800         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 801         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 802         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 803         * z80-dis.c, z8k-dis.c: Likewise.
 804         * disassemble.h: New file.
 805
 806 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 807
 808         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 809         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 810
 811 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 812
 813         * disassemble.c (disassembler): Add arguments a, big and mach.
 814         Use them.
 815
 816 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         * i386-dis.c (NOTRACK_Fixup): New.
 819         (NOTRACK): Likewise.
 820         (NOTRACK_PREFIX): Likewise.
 821         (last_active_prefix): Likewise.
 822         (reg_table): Use NOTRACK on indirect call and jmp.
 823         (ckprefix): Set last_active_prefix.
 824         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 825         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 826         * i386-opc.h (NoTrackPrefixOk): New.
 827         (i386_opcode_modifier): Add notrackprefixok.
 828         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 829         Add notrack.
 830         * i386-tbl.h: Regenerated.
 831
 832 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 833
 834         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 835         (X_IMM2): Define.
 836         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 837         bfd_mach_sparc_v9m8.
 838         (print_insn_sparc): Handle new operand types.
 839         * sparc-opc.c (MASK_M8): Define.
 840         (v6): Add MASK_M8.
 841         (v6notlet): Likewise.
 842         (v7): Likewise.
 843         (v8): Likewise.
 844         (v9): Likewise.
 845         (v9a): Likewise.
 846         (v9b): Likewise.
 847         (v9c): Likewise.
 848         (v9d): Likewise.
 849         (v9e): Likewise.
 850         (v9v): Likewise.
 851         (v9m): Likewise.
 852         (v9andleon): Likewise.
 853         (m8): Define.
 854         (HWS_VM8): Define.
 855         (HWS2_VM8): Likewise.
 856         (sparc_opcode_archs): Add entry for "m8".
 857         (sparc_opcodes): Add OSA2017 and M8 instructions
 858         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 859         fpx{ll,ra,rl}64x,
 860         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 861         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 862         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 863         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 864         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 865         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 866         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 867         ASI_CORE_SELECT_COMMIT_NHT.
 868
 869 2017-05-18  Alan Modra  <amodra@gmail.com>
 870
 871         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 872         * aarch64-dis.c: Likewise.
 873         * aarch64-gen.c: Likewise.
 874         * aarch64-opc.c: Likewise.
 875
 876 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 877             Matthew Fortune  <matthew.fortune@imgtec.com>
 878
 879         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 880         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 881         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 882         (print_insn_arg) <OP_REG28>: Add handler.
 883         (validate_insn_args) <OP_REG28>: Handle.
 884         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 885         32-bit encoding and 9-bit immediates.
 886         (print_insn_mips16): Handle MIPS16 instructions that require
 887         32-bit encoding and MFC0/MTC0 operand decoding.
 888         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 889         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 890         (RD_C0, WR_C0, E2, E2MT): New macros.
 891         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 892         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 893         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 894         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 895         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 896         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 897         instructions, "swl", "swr", "sync" and its "sync_acquire",
 898         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 899         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 900         regular/extended entries for original MIPS16 ISA revision
 901         instructions whose extended forms are subdecoded in the MIPS16e2
 902         ISA revision: "li", "sll" and "srl".
 903
 904 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 905
 906         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 907         reference in CP0 move operand decoding.
 908
 909 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 910
 911         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 912         type to hexadecimal.
 913         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 914
 915 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 916
 917         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 918         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 919         "sync_rmb" and "sync_wmb" as aliases.
 920         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 921         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 922
 923 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 924
 925         * arc-dis.c (parse_option): Update quarkse_em option..
 926         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 927         QUARKSE1.
 928         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 929
 930 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 931
 932         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 933
 934 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 935
 936         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 937         register.
 938
 939 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 940
 941         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 942         and branches and not synthetic data instructions.
 943
 944 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 945
 946         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 947
 948 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 949
 950         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 951         * arc-opc.c (insert_r13el): New function.
 952         (R13_EL): Define.
 953         * arc-tbl.h: Add new enter/leave variants.
 954
 955 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 956
 957         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 958
 959 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 960
 961         * mips-dis.c (print_mips_disassembler_options): Add
 962         `no-aliases'.
 963
 964 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 965
 966         * mips16-opc.c (AL): New macro.
 967         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 968         of "ld" and "lw" as aliases.
 969
 970 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 971
 972         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 973         arguments.
 974
 975 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 976             Alan Modra  <amodra@gmail.com>
 977
 978         * ppc-opc.c (ELEV): Define.
 979         (vle_opcodes): Add se_rfgi and e_sc.
 980         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 981         for E200Z4.
 982
 983 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 984
 985         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 986
 987 2017-04-21  Nick Clifton  <nickc@redhat.com>
 988
 989         PR binutils/21380
 990         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 991         LD3R and LD4R.
 992
 993 2017-04-13  Alan Modra  <amodra@gmail.com>
 994
 995         * epiphany-desc.c: Regenerate.
 996         * fr30-desc.c: Regenerate.
 997         * frv-desc.c: Regenerate.
 998         * ip2k-desc.c: Regenerate.
 999         * iq2000-desc.c: Regenerate.
1000         * lm32-desc.c: Regenerate.
1001         * m32c-desc.c: Regenerate.
1002         * m32r-desc.c: Regenerate.
1003         * mep-desc.c: Regenerate.
1004         * mt-desc.c: Regenerate.
1005         * or1k-desc.c: Regenerate.
1006         * xc16x-desc.c: Regenerate.
1007         * xstormy16-desc.c: Regenerate.
1008
1009 2017-04-11  Alan Modra  <amodra@gmail.com>
1010
1011         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1012         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1013         PPC_OPCODE_TMR for e6500.
1014         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1015         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1016         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1017         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1018         (PPCHTM): Define as PPC_OPCODE_POWER8.
1019         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1020
1021 2017-04-10  Alan Modra  <amodra@gmail.com>
1022
1023         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1024         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1025         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1026         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1027
1028 2017-04-09  Pip Cet  <pipcet@gmail.com>
1029
1030         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1031         appropriate floating-point precision directly.
1032
1033 2017-04-07  Alan Modra  <amodra@gmail.com>
1034
1035         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1036         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1037         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1038         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1039         vector instructions with E6500 not PPCVEC2.
1040
1041 2017-04-06  Pip Cet  <pipcet@gmail.com>
1042
1043         * Makefile.am: Add wasm32-dis.c.
1044         * configure.ac: Add wasm32-dis.c to wasm32 target.
1045         * disassemble.c: Add wasm32 disassembler code.
1046         * wasm32-dis.c: New file.
1047         * Makefile.in: Regenerate.
1048         * configure: Regenerate.
1049         * po/POTFILES.in: Regenerate.
1050         * po/opcodes.pot: Regenerate.
1051
1052 2017-04-05  Pedro Alves  <palves@redhat.com>
1053
1054         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1055         * arm-dis.c (parse_arm_disassembler_options): Constify.
1056         * ppc-dis.c (powerpc_init_dialect): Constify local.
1057         * vax-dis.c (parse_disassembler_options): Constify.
1058
1059 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1060
1061         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1062         RISCV_GP_SYMBOL.
1063
1064 2017-03-30  Pip Cet  <pipcet@gmail.com>
1065
1066         * configure.ac: Add (empty) bfd_wasm32_arch target.
1067         * configure: Regenerate
1068         * po/opcodes.pot: Regenerate.
1069
1070 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1071
1072         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1073         OSA2015.
1074         * opcodes/sparc-opc.c (asi_table): New ASIs.
1075
1076 2017-03-29  Alan Modra  <amodra@gmail.com>
1077
1078         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1079         "raw" option.
1080         (lookup_powerpc): Don't special case -1 dialect.  Handle
1081         PPC_OPCODE_RAW.
1082         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1083         lookup_powerpc call, pass it on second.
1084
1085 2017-03-27  Alan Modra  <amodra@gmail.com>
1086
1087         PR 21303
1088         * ppc-dis.c (struct ppc_mopt): Comment.
1089         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1090
1091 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1092
1093         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1094         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1095         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1096         (insert_nps_misc_imm_offset): New function.
1097         (extract_nps_misc imm_offset): New function.
1098         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1099         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1100
1101 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1102
1103         * s390-mkopc.c (main): Remove vx2 check.
1104         * s390-opc.txt: Remove vx2 instruction flags.
1105
1106 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1107
1108         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1109         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1110         (insert_nps_imm_offset): New function.
1111         (extract_nps_imm_offset): New function.
1112         (insert_nps_imm_entry): New function.
1113         (extract_nps_imm_entry): New function.
1114
1115 2017-03-17  Alan Modra  <amodra@gmail.com>
1116
1117         PR 21248
1118         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1119         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1120         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1121
1122 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1123
1124         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1125         <c.andi>: Likewise.
1126         <c.addiw> Likewise.
1127
1128 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1129
1130         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1131
1132 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1133
1134         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1135         <srl> Likewise.
1136         <srai> Likewise.
1137         <sra> Likewise.
1138
1139 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1140
1141         * i386-gen.c (opcode_modifiers): Replace S with Load.
1142         * i386-opc.h (S): Removed.
1143         (Load): New.
1144         (i386_opcode_modifier): Replace s with load.
1145         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1146         and {evex}.  Replace S with Load.
1147         * i386-tbl.h: Regenerated.
1148
1149 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1150
1151         * i386-opc.tbl: Use CpuCET on rdsspq.
1152         * i386-tbl.h: Regenerated.
1153
1154 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1155
1156         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1157         <vsx>: Do not use PPC_OPCODE_VSX3;
1158
1159 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1160
1161         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1162
1163 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1164
1165         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1166         (MOD_0F1E_PREFIX_1): Likewise.
1167         (MOD_0F38F5_PREFIX_2): Likewise.
1168         (MOD_0F38F6_PREFIX_0): Likewise.
1169         (RM_0F1E_MOD_3_REG_7): Likewise.
1170         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1171         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1172         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1173         (PREFIX_0F1E): Likewise.
1174         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1175         (PREFIX_0F38F5): Likewise.
1176         (dis386_twobyte): Use PREFIX_0F1E.
1177         (reg_table): Add REG_0F1E_MOD_3.
1178         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1179         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1180         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1181         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1182         (three_byte_table): Use PREFIX_0F38F5.
1183         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1184         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1185         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1186         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1187         PREFIX_MOD_3_0F01_REG_5_RM_2.
1188         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1189         (cpu_flags): Add CpuCET.
1190         * i386-opc.h (CpuCET): New enum.
1191         (CpuUnused): Commented out.
1192         (i386_cpu_flags): Add cpucet.
1193         * i386-opc.tbl: Add Intel CET instructions.
1194         * i386-init.h: Regenerated.
1195         * i386-tbl.h: Likewise.
1196
1197 2017-03-06  Alan Modra  <amodra@gmail.com>
1198
1199         PR 21124
1200         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1201         (extract_raq, extract_ras, extract_rbx): New functions.
1202         (powerpc_operands): Use opposite corresponding insert function.
1203         (Q_MASK): Define.
1204         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1205         register restriction.
1206
1207 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1208
1209         * disassemble.c Include "safe-ctype.h".
1210         (disassemble_init_for_target): Handle s390 init.
1211         (remove_whitespace_and_extra_commas): New function.
1212         (disassembler_options_cmp): Likewise.
1213         * arm-dis.c: Include "libiberty.h".
1214         (NUM_ELEM): Delete.
1215         (regnames): Use long disassembler style names.
1216         Add force-thumb and no-force-thumb options.
1217         (NUM_ARM_REGNAMES): Rename from this...
1218         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1219         (get_arm_regname_num_options): Delete.
1220         (set_arm_regname_option): Likewise.
1221         (get_arm_regnames): Likewise.
1222         (parse_disassembler_options): Likewise.
1223         (parse_arm_disassembler_option): Rename from this...
1224         (parse_arm_disassembler_options): ...to this.  Make static.
1225         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1226         (print_insn): Use parse_arm_disassembler_options.
1227         (disassembler_options_arm): New function.
1228         (print_arm_disassembler_options): Handle updated regnames.
1229         * ppc-dis.c: Include "libiberty.h".
1230         (ppc_opts): Add "32" and "64" entries.
1231         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1232         (powerpc_init_dialect): Add break to switch statement.
1233         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1234         (disassembler_options_powerpc): New function.
1235         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1236         Remove printing of "32" and "64".
1237         * s390-dis.c: Include "libiberty.h".
1238         (init_flag): Remove unneeded variable.
1239         (struct s390_options_t): New structure type.
1240         (options): New structure.
1241         (init_disasm): Rename from this...
1242         (disassemble_init_s390): ...to this.  Add initializations for
1243         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1244         (print_insn_s390): Delete call to init_disasm.
1245         (disassembler_options_s390): New function.
1246         (print_s390_disassembler_options): Print using information from
1247         struct 'options'.
1248         * po/opcodes.pot: Regenerate.
1249
1250 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1251
1252         * i386-dis.c (PCMPESTR_Fixup): New.
1253         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1254         (prefix_table): Use PCMPESTR_Fixup.
1255         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1256         PCMPESTR_Fixup.
1257         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1258         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1259         Split 64-bit and non-64-bit variants.
1260         * opcodes/i386-tbl.h: Re-generate.
1261
1262 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1263
1264         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1265         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1266         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1267         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1268         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1269         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1270         (OP_SVE_V_HSD): New macros.
1271         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1272         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1273         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1274         (aarch64_opcode_table): Add new SVE instructions.
1275         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1276         for rotation operands.  Add new SVE operands.
1277         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1278         (ins_sve_quad_index): Likewise.
1279         (ins_imm_rotate): Split into...
1280         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1281         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1282         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1283         functions.
1284         (aarch64_ins_sve_addr_ri_s4): New function.
1285         (aarch64_ins_sve_quad_index): Likewise.
1286         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1287         * aarch64-asm-2.c: Regenerate.
1288         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1289         (ext_sve_quad_index): Likewise.
1290         (ext_imm_rotate): Split into...
1291         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1292         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1293         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1294         functions.
1295         (aarch64_ext_sve_addr_ri_s4): New function.
1296         (aarch64_ext_sve_quad_index): Likewise.
1297         (aarch64_ext_sve_index): Allow quad indices.
1298         (do_misc_decoding): Likewise.
1299         * aarch64-dis-2.c: Regenerate.
1300         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1301         aarch64_field_kinds.
1302         (OPD_F_OD_MASK): Widen by one bit.
1303         (OPD_F_NO_ZR): Bump accordingly.
1304         (get_operand_field_width): New function.
1305         * aarch64-opc.c (fields): Add new SVE fields.
1306         (operand_general_constraint_met_p): Handle new SVE operands.
1307         (aarch64_print_operand): Likewise.
1308         * aarch64-opc-2.c: Regenerate.
1309
1310 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1311
1312         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1313         (aarch64_feature_compnum): ...this.
1314         (SIMD_V8_3): Replace with...
1315         (COMPNUM): ...this.
1316         (CNUM_INSN): New macro.
1317         (aarch64_opcode_table): Use it for the complex number instructions.
1318
1319 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1320
1321         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1322
1323 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1324
1325         Add support for associating SPARC ASIs with an architecture level.
1326         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1327         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1328         decoding of SPARC ASIs.
1329
1330 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1331
1332         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1333         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1334
1335 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1336
1337         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1338         1 (instead of to itself). Correct typo.
1339
1340 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1341
1342         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1343         pseudoinstructions.
1344
1345 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1346
1347         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1348         (aarch64_sys_reg_supported_p): Handle them.
1349
1350 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1351
1352         * arc-opc.c (UIMM6_20R): Define.
1353         (SIMM12_20): Use above.
1354         (SIMM12_20R): Define.
1355         (SIMM3_5_S): Use above.
1356         (UIMM7_A32_11R_S): Define.
1357         (UIMM7_9_S): Use above.
1358         (UIMM3_13R_S): Define.
1359         (SIMM11_A32_7_S): Use above.
1360         (SIMM9_8R): Define.
1361         (UIMM10_A32_8_S): Use above.
1362         (UIMM8_8R_S): Define.
1363         (W6): Use above.
1364         (arc_relax_opcodes): Use all above defines.
1365
1366 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1367
1368         * arc-regs.h: Distinguish some of the registers different on
1369         ARC700 and HS38 cpus.
1370
1371 2017-02-14  Alan Modra  <amodra@gmail.com>
1372
1373         PR 21118
1374         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1375         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1376
1377 2017-02-11  Stafford Horne  <shorne@gmail.com>
1378             Alan Modra  <amodra@gmail.com>
1379
1380         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1381         Use insn_bytes_value and insn_int_value directly instead.  Don't
1382         free allocated memory until function exit.
1383
1384 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1385
1386         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1387
1388 2017-02-03  Nick Clifton  <nickc@redhat.com>
1389
1390         PR 21096
1391         * aarch64-opc.c (print_register_list): Ensure that the register
1392         list index will fir into the tb buffer.
1393         (print_register_offset_address): Likewise.
1394         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1395
1396 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1397
1398         PR 21056
1399         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1400         instructions when the previous fetch packet ends with a 32-bit
1401         instruction.
1402
1403 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1404
1405         * pru-opc.c: Remove vague reference to a future GDB port.
1406
1407 2017-01-20  Nick Clifton  <nickc@redhat.com>
1408
1409         * po/ga.po: Updated Irish translation.
1410
1411 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1412
1413         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1414
1415 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1416
1417         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1418         if FETCH_DATA returns 0.
1419         (m68k_scan_mask): Likewise.
1420         (print_insn_m68k): Update code to handle -1 return value.
1421
1422 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1423
1424         * m68k-dis.c (enum print_insn_arg_error): New.
1425         (NEXTBYTE): Replace -3 with
1426         PRINT_INSN_ARG_MEMORY_ERROR.
1427         (NEXTULONG): Likewise.
1428         (NEXTSINGLE): Likewise.
1429         (NEXTDOUBLE): Likewise.
1430         (NEXTDOUBLE): Likewise.
1431         (NEXTPACKED): Likewise.
1432         (FETCH_ARG): Likewise.
1433         (FETCH_DATA): Update comments.
1434         (print_insn_arg): Update comments. Replace magic numbers with
1435         enum.
1436         (match_insn_m68k): Likewise.
1437
1438 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1439
1440         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1441         * i386-dis-evex.h (evex_table): Updated.
1442         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1443         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1444         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1445         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1446         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1447         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1448         * i386-init.h: Regenerate.
1449         * i386-tbl.h: Ditto.
1450
1451 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1452
1453         * msp430-dis.c (msp430_singleoperand): Return -1 if
1454         msp430dis_opcode_signed returns false.
1455         (msp430_doubleoperand): Likewise.
1456         (msp430_branchinstr): Return -1 if
1457         msp430dis_opcode_unsigned returns false.
1458         (msp430x_calla_instr): Likewise.
1459         (print_insn_msp430): Likewise.
1460
1461 2017-01-05  Nick Clifton  <nickc@redhat.com>
1462
1463         PR 20946
1464         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1465         could not be matched.
1466         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1467         NULL.
1468
1469 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1470
1471         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1472         (aarch64_opcode_table): Use RCPC_INSN.
1473
1474 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1475
1476         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1477         extension.
1478         * riscv-opcodes/all-opcodes: Likewise.
1479
1480 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1481
1482         * riscv-dis.c (print_insn_args): Add fall through comment.
1483
1484 2017-01-03  Nick Clifton  <nickc@redhat.com>
1485
1486         * po/sr.po: New Serbian translation.
1487         * configure.ac (ALL_LINGUAS): Add sr.
1488         * configure: Regenerate.
1489
1490 2017-01-02  Alan Modra  <amodra@gmail.com>
1491
1492         * epiphany-desc.h: Regenerate.
1493         * epiphany-opc.h: Regenerate.
1494         * fr30-desc.h: Regenerate.
1495         * fr30-opc.h: Regenerate.
1496         * frv-desc.h: Regenerate.
1497         * frv-opc.h: Regenerate.
1498         * ip2k-desc.h: Regenerate.
1499         * ip2k-opc.h: Regenerate.
1500         * iq2000-desc.h: Regenerate.
1501         * iq2000-opc.h: Regenerate.
1502         * lm32-desc.h: Regenerate.
1503         * lm32-opc.h: Regenerate.
1504         * m32c-desc.h: Regenerate.
1505         * m32c-opc.h: Regenerate.
1506         * m32r-desc.h: Regenerate.
1507         * m32r-opc.h: Regenerate.
1508         * mep-desc.h: Regenerate.
1509         * mep-opc.h: Regenerate.
1510         * mt-desc.h: Regenerate.
1511         * mt-opc.h: Regenerate.
1512         * or1k-desc.h: Regenerate.
1513         * or1k-opc.h: Regenerate.
1514         * xc16x-desc.h: Regenerate.
1515         * xc16x-opc.h: Regenerate.
1516         * xstormy16-desc.h: Regenerate.
1517         * xstormy16-opc.h: Regenerate.
1518
1519 2017-01-02  Alan Modra  <amodra@gmail.com>
1520
1521         Update year range in copyright notice of all files.
1522
1523 For older changes see ChangeLog-2016
1524 \f
1525 Copyright (C) 2017 Free Software Foundation, Inc.
1526
1527 Copying and distribution of this file, with or without modification,
1528 are permitted in any medium without royalty provided the copyright
1529 notice and this notice are preserved.
1530
1531 Local Variables:
1532 mode: change-log
1533 left-margin: 8
1534 fill-column: 74
1535 version-control: never
1536 End: