opcodes/ChangeLog

   1 2010-10-08  Pierre Muller  <muller@ics.u-strasbg.fr>
   2
   3         Fix build with -DDEBUG=7
   4         * frv-opc.c: Regenerate.
   5         * or32-dis.c (DEBUG): Don't redefine.
   6         (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
   7         Adapt DEBUG code to some type changes throughout.
   8         * or32-opc.c (or32_extract): Likewise.
   9
  10 2010-10-07  Bernd Schmidt  <bernds@codesourcery.com>
  11
  12         * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
  13         in SPKERNEL instructions.
  14
  15 2010-10-02  H.J. Lu  <hongjiu.lu@intel.com>
  16
  17         PR binutils/12076
  18         * i386-dis.c (RMAL): Remove duplicate.
  19
  20 2010-09-30  Pierre Muller  <muller@ics.u-strasbg.fr>
  21
  22         * s390-mkopc.c (main): Exit with error 1 if sscanf fails
  23         to parse all 6 parameters.
  24
  25 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
  26
  27         * s390-mkopc.c (main): Change description array size to 80.
  28         Add maximum length of 79 to description parsing.
  29
  30 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
  31
  32         * configure: Regenerate.
  33
  34 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  35
  36         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
  37         (main): Recognize the new CPU string.
  38         * s390-opc.c: Add new instruction formats and masks.
  39         * s390-opc.txt: Add new z196 instructions.
  40
  41 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  42
  43         * s390-dis.c (print_insn_s390): Pick instruction with most
  44         specific mask.
  45         * s390-opc.c: Add unused bits to the insn mask.
  46         * s390-opc.txt: Reorder some instructions to prefer more recent
  47         versions.
  48
  49 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
  50
  51         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
  52         correction to unaligned PCs while printing comment.
  53
  54 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  55
  56         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
  57         (thumb32_opcodes): Likewise.
  58         (banked_regname): New function.
  59         (print_insn_arm): Add Virtualization Extensions support.
  60         (print_insn_thumb32): Likewise.
  61
  62 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  63
  64         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
  65         ARM state.
  66
  67 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  68
  69         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
  70         (thumb32_opcodes): Likewise.
  71
  72 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  73
  74         * arm-dis.c (arm_opcodes): Add support for pldw.
  75         (thumb32_opcodes): Likewise.
  76
  77 2010-09-22  Robin Getz  <robin.getz@analog.com>
  78
  79         * bfin-dis.c (fmtconst): Cast address to 32bits.
  80
  81 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  82
  83         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
  84
  85 2010-09-22  Robin Getz  <robin.getz@analog.com>
  86
  87         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
  88         Reject P6/P7 to TESTSET.
  89         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
  90         SP onto the stack.
  91         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
  92         P/D fields match all the time.
  93         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
  94         are 0 for accumulator compares.
  95         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
  96         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
  97         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
  98         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
  99         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 100         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
 101         insns.
 102         (decode_dagMODim_0): Verify br field for IREG ops.
 103         (decode_LDST_0): Reject preg load into same preg.
 104         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
 105         (print_insn_bfin): Likewise.
 106
 107 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 108
 109         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
 110
 111 2010-09-22  Robin Getz  <robin.getz@analog.com>
 112
 113         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
 114
 115 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 116
 117         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
 118
 119 2010-09-22  Robin Getz  <robin.getz@analog.com>
 120
 121         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
 122         register values greater than 8.
 123         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 124         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 125         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 126         (decode_CC2dreg_0): Check valid CC register number.
 127
 128 2010-09-22  Robin Getz  <robin.getz@analog.com>
 129
 130         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 131
 132 2010-09-22  Robin Getz  <robin.getz@analog.com>
 133
 134         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 135         (reg_names): Likewise.
 136         (decode_statbits): Likewise; while reformatting to make manageable.
 137
 138 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 139
 140         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 141         (decode_pseudoOChar_0): New function.
 142         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 143
 144 2010-09-22  Robin Getz  <robin.getz@analog.com>
 145
 146         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 147         LSHIFT instead of SHIFT.
 148
 149 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 150
 151         * bfin-dis.c (constant_formats): Constify the whole structure.
 152         (fmtconst): Add const to return value.
 153         (reg_names): Mark const.
 154         (decode_multfunc): Mark s0/s1 as const.
 155         (decode_macfunc): Mark a/sop as const.
 156
 157 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 158
 159         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 160
 161 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 162
 163         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 164         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 165
 166 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 167
 168         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 169         dlx_insn_type array.
 170
 171 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 172
 173         PR binutils/11960
 174         * i386-dis.c (sIv): New.
 175         (dis386): Replace Iq with sIv on "pushT".
 176         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 177         (x86_64_table): Replace {T|}/{P|} with P.
 178         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 179         (OP_sI): Update v_mode.  Remove w_mode.
 180
 181 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 182
 183         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 184         on E500 and E500MC.
 185
 186 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 187
 188         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 189         prefetchw.
 190
 191 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 192
 193         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 194         to processor flags for PENTIUMPRO processors and later.
 195         * i386-opc.h (enum): Add CpuNop.
 196         (i386_cpu_flags): Add cpunop bit.
 197         * i386-opc.tbl: Change nop cpu_flags.
 198         * i386-init.h: Regenerated.
 199         * i386-tbl.h: Likewise.
 200
 201 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 202
 203         * i386-opc.h (enum): Fix typos in comments.
 204
 205 2010-08-06  Alan Modra  <amodra@gmail.com>
 206
 207         * disassemble.c: Formatting.
 208         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 209
 210 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 213         * i386-tbl.h: Regenerated.
 214
 215 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 218
 219         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 220         * i386-tbl.h: Regenerated.
 221
 222 2010-07-29  DJ Delorie  <dj@redhat.com>
 223
 224         * rx-decode.opc (SRR): New.
 225         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 226         r0,r0) and NOP3 (max r0,r0) special cases.
 227         * rx-decode.c: Regenerate.
 228
 229 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 230
 231         * i386-dis.c: Add 0F to VEX opcode enums.
 232
 233 2010-07-27  DJ Delorie  <dj@redhat.com>
 234
 235         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 236         (rx_decode_opcode): Likewise.
 237         * rx-decode.c: Regenerate.
 238
 239 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 240             Ina Pandit  <ina.pandit@kpitcummins.com>
 241
 242         * v850-dis.c (v850_sreg_names): Updated structure for system
 243         registers.
 244         (float_cc_names): new structure for condition codes.
 245         (print_value): Update the function that prints value.
 246         (get_operand_value): New function to get the operand value.
 247         (disassemble): Updated to handle the disassembly of instructions.
 248         (print_insn_v850): Updated function to print instruction for different
 249         families.
 250         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 251         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 252         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 253         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 254         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 255         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 256         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 257         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 258         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 259         (v850_operands): Update with the relocation name. Also update
 260         the instructions with specific set of processors.
 261
 262 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 263
 264         * arm-dis.c (print_insn_arm): Add cases for printing more
 265         symbolic operands.
 266         (print_insn_thumb32): Likewise.
 267
 268 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 269
 270         * mips-dis.c (print_insn_mips): Correct branch instruction type
 271         determination.
 272
 273 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 274
 275         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 276         type and delay slot determination.
 277         (print_insn_mips16): Extend branch instruction type and delay
 278         slot determination to cover all instructions.
 279         * mips16-opc.c (BR): Remove macro.
 280         (UBR, CBR): New macros.
 281         (mips16_opcodes): Update branch annotation for "b", "beqz",
 282         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 283         and "jrc".
 284
 285 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 286
 287         AVX Programming Reference (June, 2010)
 288         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 289         * i386-opc.tbl: Likewise.
 290         * i386-tbl.h: Regenerated.
 291
 292 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 295
 296 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 297
 298         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 299         ppc_cpu_t before inverting.
 300         (ppc_parse_cpu): Likewise.
 301         (print_insn_powerpc): Likewise.
 302
 303 2010-07-03  Alan Modra  <amodra@gmail.com>
 304
 305         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 306         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 307         (PPC64, MFDEC2): Update.
 308         (NON32, NO371): Define.
 309         (powerpc_opcode): Update to not use old opcode flags, and avoid
 310         -m601 duplicates.
 311
 312 2010-07-03  DJ Delorie  <dj@delorie.com>
 313
 314         * m32c-ibld.c: Regenerate.
 315
 316 2010-07-03  Alan Modra  <amodra@gmail.com>
 317
 318         * ppc-opc.c (PWR2COM): Define.
 319         (PPCPWR2): Add PPC_OPCODE_COMMON.
 320         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 321         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 322         "rac" from -mcom.
 323
 324 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 325
 326         AVX Programming Reference (June, 2010)
 327         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 328         (PREFIX_0FAE_REG_1): Likewise.
 329         (PREFIX_0FAE_REG_2): Likewise.
 330         (PREFIX_0FAE_REG_3): Likewise.
 331         (PREFIX_VEX_3813): Likewise.
 332         (PREFIX_VEX_3A1D): Likewise.
 333         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 334         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 335         PREFIX_VEX_3A1D.
 336         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 337         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 338         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 339
 340         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 341         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 342         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 343
 344         * i386-opc.h (CpuXsaveopt): New.
 345         (CpuFSGSBase): Likewise.
 346         (CpuRdRnd): Likewise.
 347         (CpuF16C): Likewise.
 348         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 349         cpuf16c.
 350
 351         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 352         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 353         * i386-init.h: Regenerated.
 354         * i386-tbl.h: Likewise.
 355
 356 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 357
 358         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 359         and mtocrf on EFS.
 360
 361 2010-06-29  Alan Modra  <amodra@gmail.com>
 362
 363         * maxq-dis.c: Delete file.
 364         * Makefile.am: Remove references to maxq.
 365         * configure.in: Likewise.
 366         * disassemble.c: Likewise.
 367         * Makefile.in: Regenerate.
 368         * configure: Regenerate.
 369         * po/POTFILES.in: Regenerate.
 370
 371 2010-06-29  Alan Modra  <amodra@gmail.com>
 372
 373         * mep-dis.c: Regenerate.
 374
 375 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 376
 377         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 378
 379 2010-06-27  Alan Modra  <amodra@gmail.com>
 380
 381         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 382         (decodeInstr): Likewise.
 383         * dlx-dis.c (print_insn_dlx): Likewise.
 384         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 385         * maxq-dis.c (check_move, print_insn): Likewise.
 386         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 387         * msp430-dis.c (msp430_branchinstr): Likewise.
 388         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 389         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 390         * sparc-dis.c (print_insn_sparc): Likewise.
 391         * fr30-asm.c: Regenerate.
 392         * frv-asm.c: Regenerate.
 393         * ip2k-asm.c: Regenerate.
 394         * iq2000-asm.c: Regenerate.
 395         * lm32-asm.c: Regenerate.
 396         * m32c-asm.c: Regenerate.
 397         * m32r-asm.c: Regenerate.
 398         * mep-asm.c: Regenerate.
 399         * mt-asm.c: Regenerate.
 400         * openrisc-asm.c: Regenerate.
 401         * xc16x-asm.c: Regenerate.
 402         * xstormy16-asm.c: Regenerate.
 403
 404 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 405
 406         PR gas/11673
 407         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 408
 409 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 410
 411         PR binutils/11676
 412         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 413
 414 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 415
 416         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 417         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 418         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 419         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 420         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 421         Treat lwsync as msync on e500.
 422
 423 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 424
 425         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 426
 427 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 428
 429         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 430         constants is the same on 32-bit and 64-bit hosts.
 431
 432 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 433
 434         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 435         .short directives so that they can be reassembled.
 436
 437 2010-05-26  Catherine Moore <clm@codesourcery.com>
 438             David Ung  <davidu@mips.com>
 439
 440         * mips-opc.c: Change membership to I1 for instructions ssnop and
 441         ehb.
 442
 443 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 444
 445         * i386-dis.c (sib): New.
 446         (get_sib): Likewise.
 447         (print_insn): Call get_sib.
 448         OP_E_memory): Use sib.
 449
 450 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 451
 452         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 453         * mips-opc.c (I16): Remove.
 454         (mips_builtin_op): Reclassify jalx.
 455
 456 2010-05-19  Alan Modra  <amodra@gmail.com>
 457
 458         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 459         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 460
 461 2010-05-13  Alan Modra  <amodra@gmail.com>
 462
 463         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 464
 465 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 466
 467         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 468         format.
 469         (print_insn_thumb16): Add support for new %W format.
 470
 471 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 472
 473         * Makefile.in: Regenerate with automake 1.11.1.
 474         * aclocal.m4: Ditto.
 475
 476 2010-05-05  Nick Clifton  <nickc@redhat.com>
 477
 478         * po/es.po: Updated Spanish translation.
 479
 480 2010-04-22  Nick Clifton  <nickc@redhat.com>
 481
 482         * po/opcodes.pot: Updated by the Translation project.
 483         * po/vi.po: Updated Vietnamese translation.
 484
 485 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 486
 487         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 488         bits in opcode.
 489
 490 2010-04-09  Nick Clifton  <nickc@redhat.com>
 491
 492         * i386-dis.c (print_insn): Remove unused variable op.
 493         (OP_sI): Remove unused variable mask.
 494
 495 2010-04-07  Alan Modra  <amodra@gmail.com>
 496
 497         * configure: Regenerate.
 498
 499 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 500
 501         * ppc-opc.c (RBOPT): New define.
 502         ("dccci"): Enable for PPCA2.  Make operands optional.
 503         ("iccci"): Likewise.  Do not deprecate for PPC476.
 504
 505 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 506
 507         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 508
 509 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 510
 511         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 512         * Makefile.in: Regenerate.
 513         * configure.in (bfd_tic6x_arch): New.
 514         * configure: Regenerate.
 515         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 516         (disassembler): Handle TI C6X.
 517         * tic6x-dis.c: New.
 518
 519 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 520
 521         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 522
 523 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 524
 525         * dis-buf.c (buffer_read_memory): Give error for reading just
 526         before the start of memory.
 527
 528 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 529             Quentin Neill <quentin.neill@amd.com>
 530
 531         * i386-dis.c (OP_LWP_I): Removed.
 532         (reg_table): Do not use OP_LWP_I, use Iq.
 533         (OP_LWPCB_E): Remove use of names16.
 534         (OP_LWP_E): Same.
 535         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 536         should not set the Vex.length bit.
 537         * i386-tbl.h: Regenerated.
 538
 539 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 540
 541         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 542
 543 2010-02-24  Nick Clifton  <nickc@redhat.com>
 544
 545         PR binutils/6773
 546         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 547         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 548         (thumb32_opcodes): Likewise.
 549
 550 2010-02-15  Nick Clifton  <nickc@redhat.com>
 551
 552         * po/vi.po: Updated Vietnamese translation.
 553
 554 2010-02-12  Doug Evans  <dje@sebabeach.org>
 555
 556         * lm32-opinst.c: Regenerate.
 557
 558 2010-02-11  Doug Evans  <dje@sebabeach.org>
 559
 560         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 561         (print_address): Delete CGEN_PRINT_ADDRESS.
 562         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 563         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 564         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 565         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 566
 567         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 568         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 569         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 570         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 571         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 572         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 573         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 574         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 575         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 576         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 577         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 578         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 579
 580 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 581
 582         * i386-dis.c: Update copyright.
 583         * i386-gen.c: Likewise.
 584         * i386-opc.h: Likewise.
 585         * i386-opc.tbl: Likewise.
 586
 587 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 588             Sebastian Pop  <sebastian.pop@amd.com>
 589
 590         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 591         function to handle 5th imm8 operand.
 592         (PREFIX_VEX_3A48): Added.
 593         (PREFIX_VEX_3A49): Added.
 594         (VEX_W_3A48_P_2): Added.
 595         (VEX_W_3A49_P_2): Added.
 596         (prefix table): Added entries for PREFIX_VEX_3A48
 597         and PREFIX_VEX_3A49.
 598         (vex table): Added entries for VEX_W_3A48_P_2 and
 599         and VEX_W_3A49_P_2.
 600         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 601         for Vec_Imm4 operands.
 602         * i386-opc.h (enum): Added Vec_Imm4.
 603         (i386_operand_type): Added vec_imm4.
 604         * i386-opc.tbl: Add entries for vpermilp[ds].
 605         * i386-init.h: Regenerated.
 606         * i386-tbl.h: Regenerated.
 607
 608 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 609
 610         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 611         and "pwr7".  Move "a2" into alphabetical order.
 612
 613 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 614
 615         * ppc-dis.c (ppc_opts): Add titan entry.
 616         * ppc-opc.c (TITAN, MULHW): Define.
 617         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 618
 619 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 620
 621         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 622         to CPU_BDVER1_FLAGS
 623         * i386-init.h: Regenerated.
 624
 625 2010-02-03  Anthony Green  <green@moxielogic.com>
 626
 627         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 628         0x0f, and make 0x00 an illegal instruction.
 629
 630 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 631
 632         * opcodes/arm-dis.c (struct arm_private_data): New.
 633         (print_insn_coprocessor, print_insn_arm): Update to use struct
 634         arm_private_data.
 635         (is_mapping_symbol, get_map_sym_type): New functions.
 636         (get_sym_code_type): Check the symbol's section.  Do not check
 637         mapping symbols.
 638         (print_insn): Default to disassembling ARM mode code.  Check
 639         for mapping symbols separately from other symbols.  Use
 640         struct arm_private_data.
 641
 642 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 643
 644         * i386-dis.c (EXVexWdqScalar): New.
 645         (vex_scalar_w_dq_mode): Likewise.
 646         (prefix_table): Update entries for PREFIX_VEX_3899,
 647         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 648         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 649         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 650         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 651         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 652         (OP_EX): Likewise.
 653
 654 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 655
 656         * i386-dis.c (XMScalar): New.
 657         (EXdScalar): Likewise.
 658         (EXqScalar): Likewise.
 659         (EXqScalarS): Likewise.
 660         (VexScalar): Likewise.
 661         (EXdVexScalarS): Likewise.
 662         (EXqVexScalarS): Likewise.
 663         (XMVexScalar): Likewise.
 664         (scalar_mode): Likewise.
 665         (d_scalar_mode): Likewise.
 666         (d_scalar_swap_mode): Likewise.
 667         (q_scalar_mode): Likewise.
 668         (q_scalar_swap_mode): Likewise.
 669         (vex_scalar_mode): Likewise.
 670         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 671         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 672         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 673         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 674         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 675         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 676         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 677         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 678         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 679         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 680         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 681         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 682         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 683         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 684         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 685         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 686         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 687         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 688         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 689         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 690         q_scalar_mode, q_scalar_swap_mode.
 691         (OP_XMM): Handle scalar_mode.
 692         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 693         and q_scalar_swap_mode.
 694         (OP_VEX): Handle vex_scalar_mode.
 695
 696 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 697
 698         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 699
 700 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 701
 702         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 703
 704 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 705
 706         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 707
 708 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 709
 710         * i386-dis.c (Bad_Opcode): New.
 711         (bad_opcode): Likewise.
 712         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 713         (dis386_twobyte): Likewise.
 714         (reg_table): Likewise.
 715         (prefix_table): Likewise.
 716         (x86_64_table): Likewise.
 717         (vex_len_table): Likewise.
 718         (vex_w_table): Likewise.
 719         (mod_table): Likewise.
 720         (rm_table): Likewise.
 721         (float_reg): Likewise.
 722         (reg_table): Remove trailing "(bad)" entries.
 723         (prefix_table): Likewise.
 724         (x86_64_table): Likewise.
 725         (vex_len_table): Likewise.
 726         (vex_w_table): Likewise.
 727         (mod_table): Likewise.
 728         (rm_table): Likewise.
 729         (get_valid_dis386): Handle bytemode 0.
 730
 731 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 732
 733         * i386-opc.h (VEXScalar): New.
 734
 735         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 736         instructions.
 737         * i386-tbl.h: Regenerated.
 738
 739 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 740
 741         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 742
 743         * i386-opc.tbl: Add xsave64 and xrstor64.
 744         * i386-tbl.h: Regenerated.
 745
 746 2010-01-20  Nick Clifton  <nickc@redhat.com>
 747
 748         PR 11170
 749         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 750         based post-indexed addressing.
 751
 752 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 753
 754         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 755         * i386-tbl.h: Regenerated.
 756
 757 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 758
 759         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 760         comments.
 761
 762 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 763
 764         * i386-dis.c (names_mm): New.
 765         (intel_names_mm): Likewise.
 766         (att_names_mm): Likewise.
 767         (names_xmm): Likewise.
 768         (intel_names_xmm): Likewise.
 769         (att_names_xmm): Likewise.
 770         (names_ymm): Likewise.
 771         (intel_names_ymm): Likewise.
 772         (att_names_ymm): Likewise.
 773         (print_insn): Set names_mm, names_xmm and names_ymm.
 774         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 775         (OP_XMM): Likewise.
 776         (OP_EM): Likewise.
 777         (OP_EMC): Likewise.
 778         (OP_MXC): Likewise.
 779         (OP_EX): Likewise.
 780         (XMM_Fixup): Likewise.
 781         (OP_VEX): Likewise.
 782         (OP_EX_VexReg): Likewise.
 783         (OP_Vex_2src): Likewise.
 784         (OP_Vex_2src_1): Likewise.
 785         (OP_Vex_2src_2): Likewise.
 786         (OP_REG_VexI4): Likewise.
 787
 788 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 789
 790         * i386-dis.c (print_insn): Update comments.
 791
 792 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 793
 794         * i386-dis.c (rex_original): Removed.
 795         (ckprefix): Remove rex_original.
 796         (print_insn): Update comments.
 797
 798 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 799
 800         * Makefile.in: Regenerate.
 801         * configure: Regenerate.
 802
 803 2010-01-07  Doug Evans  <dje@sebabeach.org>
 804
 805         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 806         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 807         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 808         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 809         * xstormy16-ibld.c: Regenerate.
 810
 811 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 812
 813         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 814         * i386-init.h: Regenerated.
 815
 816 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 817
 818         * arm-dis.c (print_insn): Fixed search for next symbol and data
 819         dumping condition, and the initial mapping symbol state.
 820
 821 2010-01-05  Doug Evans  <dje@sebabeach.org>
 822
 823         * cgen-ibld.in: #include "cgen/basic-modes.h".
 824         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 825         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 826         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 827         * xstormy16-ibld.c: Regenerate.
 828
 829 2010-01-04  Nick Clifton  <nickc@redhat.com>
 830
 831         PR 11123
 832         * arm-dis.c (print_insn_coprocessor): Initialise value.
 833
 834 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 835
 836         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 837
 838 2010-01-02  Doug Evans  <dje@sebabeach.org>
 839
 840         * cgen-asm.in: Update copyright year.
 841         * cgen-dis.in: Update copyright year.
 842         * cgen-ibld.in: Update copyright year.
 843         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 844         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 845         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 846         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 847         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 848         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 849         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 850         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 851         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 852         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 853         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 854         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 855         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 856         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 857         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 858         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 859         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 860         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 861         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 862         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 863         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 864
 865 For older changes see ChangeLog-2009
 866 \f
 867 Local Variables:
 868 mode: change-log
 869 left-margin: 8
 870 fill-column: 74
 871 version-control: never
 872 End: