opcodes/ChangeLog

   1 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
   2
   3         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
   4         sve_size_tsz_bhs iclass encode.
   5         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
   6         sve_size_tsz_bhs iclass decode.
   7
   8 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
   9
  10         * aarch64-asm-2.c: Regenerated.
  11         * aarch64-dis-2.c: Regenerated.
  12         * aarch64-opc-2.c: Regenerated.
  13         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  14         for SVE_Zm4_11_INDEX.
  15         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
  16         (fields): Handle SVE_i2h field.
  17         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
  18         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
  19
  20 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  21
  22         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  23         sve_shift_tsz_bhsd iclass encode.
  24         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  25         sve_shift_tsz_bhsd iclass decode.
  26
  27 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  28
  29         * aarch64-asm-2.c: Regenerated.
  30         * aarch64-dis-2.c: Regenerated.
  31         * aarch64-opc-2.c: Regenerated.
  32         * aarch64-asm.c (aarch64_ins_sve_shrimm):
  33         (aarch64_encode_variant_using_iclass): Handle
  34         sve_shift_tsz_hsd iclass encode.
  35         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  36         sve_shift_tsz_hsd iclass decode.
  37         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  38         for SVE_SHRIMM_UNPRED_22.
  39         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
  40         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
  41         operand.
  42
  43 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  44
  45         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  46         sve_size_013 iclass encode.
  47         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  48         sve_size_013 iclass decode.
  49
  50 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  51
  52         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  53         sve_size_bh iclass encode.
  54         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  55         sve_size_bh iclass decode.
  56
  57 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  58
  59         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  60         sve_size_sd2 iclass encode.
  61         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  62         sve_size_sd2 iclass decode.
  63         * aarch64-opc.c (fields): Handle SVE_sz2 field.
  64         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
  65
  66 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  67
  68         * aarch64-asm-2.c: Regenerated.
  69         * aarch64-dis-2.c: Regenerated.
  70         * aarch64-opc-2.c: Regenerated.
  71         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  72         for SVE_ADDR_ZX.
  73         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
  74         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
  75
  76 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  77
  78         * aarch64-asm-2.c: Regenerated.
  79         * aarch64-dis-2.c: Regenerated.
  80         * aarch64-opc-2.c: Regenerated.
  81         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  82         for SVE_Zm3_11_INDEX.
  83         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
  84         (fields): Handle SVE_i3l and SVE_i3h2 fields.
  85         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
  86         fields.
  87         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
  88
  89 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  90
  91         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  92         sve_size_hsd2 iclass encode.
  93         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  94         sve_size_hsd2 iclass decode.
  95         * aarch64-opc.c (fields): Handle SVE_size field.
  96         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
  97
  98 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  99
 100         * aarch64-asm-2.c: Regenerated.
 101         * aarch64-dis-2.c: Regenerated.
 102         * aarch64-opc-2.c: Regenerated.
 103         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 104         for SVE_IMM_ROT3.
 105         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 106         (fields): Handle SVE_rot3 field.
 107         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 108         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 109
 110 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 111
 112         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 113         instructions.
 114
 115 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 116
 117         * aarch64-tbl.h
 118         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 119         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 120         aarch64_feature_sve2bitperm): New feature sets.
 121         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 122         for feature set addresses.
 123         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 124         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 125
 126 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 127             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 128
 129         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 130         argument and set ASE_EVA_R6 appropriately.
 131         (set_default_mips_dis_options): Pass ISA to above.
 132         (parse_mips_dis_option): Likewise.
 133         * mips-opc.c (EVAR6): New macro.
 134         (mips_builtin_opcodes): Add llwpe, scwpe.
 135
 136 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 137
 138         * aarch64-asm-2.c: Regenerated.
 139         * aarch64-dis-2.c: Regenerated.
 140         * aarch64-opc-2.c: Regenerated.
 141         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 142         AARCH64_OPND_TME_UIMM16.
 143         (aarch64_print_operand): Likewise.
 144         * aarch64-tbl.h (QL_IMM_NIL): New.
 145         (TME): New.
 146         (_TME_INSN): New.
 147         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 148
 149 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 150
 151         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 152
 153 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 154             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 155
 156         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 157
 158 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 159
 160         * s12z-opc.h: Add extern "C" bracketing to help
 161         users who wish to use this interface in c++ code.
 162
 163 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 164
 165         * s12z-opc.c (bm_decode): Handle bit map operations with the
 166         "reserved0" mode.
 167
 168 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 169
 170         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 171         specifier.  Add entries for VLDR and VSTR of system registers.
 172         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 173         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 174         of %J and %K format specifier.
 175
 176 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 177
 178         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 179         Add new entries for VSCCLRM instruction.
 180         (print_insn_coprocessor): Handle new %C format control code.
 181
 182 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 183
 184         * arm-dis.c (enum isa): New enum.
 185         (struct sopcode32): New structure.
 186         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 187         set isa field of all current entries to ANY.
 188         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 189         Only match an entry if its isa field allows the current mode.
 190
 191 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 192
 193         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 194         CLRM.
 195         (print_insn_thumb32): Add logic to print %n CLRM register list.
 196
 197 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 198
 199         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 200         and %Q patterns.
 201
 202 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 203
 204         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 205         (print_insn_thumb32): Edit the switch case for %Z.
 206
 207 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 208
 209         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 210
 211 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 212
 213         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 214
 215 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 216
 217         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 218
 219 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 220
 221         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 222         Arm register with r13 and r15 unpredictable.
 223         (thumb32_opcodes): New instructions for bfx and bflx.
 224
 225 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 226
 227         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 228
 229 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 230
 231         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 232
 233 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 234
 235         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 236
 237 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 238
 239         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 240
 241 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 242
 243         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 244         "optr". ("operator" is a reserved word in c++).
 245
 246 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 247
 248         * aarch64-opc.c (aarch64_print_operand): Add case for
 249         AARCH64_OPND_Rt_SP.
 250         (verify_constraints): Likewise.
 251         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 252         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 253         to accept Rt|SP as first operand.
 254         (AARCH64_OPERANDS): Add new Rt_SP.
 255         * aarch64-asm-2.c: Regenerated.
 256         * aarch64-dis-2.c: Regenerated.
 257         * aarch64-opc-2.c: Regenerated.
 258
 259 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 260
 261         * aarch64-asm-2.c: Regenerated.
 262         * aarch64-dis-2.c: Likewise.
 263         * aarch64-opc-2.c: Likewise.
 264         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 265
 266 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 267
 268         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 269
 270 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 271
 272         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 273         * i386-init.h: Regenerated.
 274
 275 2019-04-07  Alan Modra  <amodra@gmail.com>
 276
 277         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 278         op_separator to control printing of spaces, comma and parens
 279         rather than need_comma, need_paren and spaces vars.
 280
 281 2019-04-07  Alan Modra  <amodra@gmail.com>
 282
 283         PR 24421
 284         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 285         (print_insn_neon, print_insn_arm): Likewise.
 286
 287 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 288
 289         * i386-dis-evex.h (evex_table): Updated to support BF16
 290         instructions.
 291         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 292         and EVEX_W_0F3872_P_3.
 293         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 294         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 295         * i386-opc.h (enum): Add CpuAVX512_BF16.
 296         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 297         * i386-opc.tbl: Add AVX512 BF16 instructions.
 298         * i386-init.h: Regenerated.
 299         * i386-tbl.h: Likewise.
 300
 301 2019-04-05  Alan Modra  <amodra@gmail.com>
 302
 303         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 304         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 305         to favour printing of "-" branch hint when using the "y" bit.
 306         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 307
 308 2019-04-05  Alan Modra  <amodra@gmail.com>
 309
 310         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 311         opcode until first operand is output.
 312
 313 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 314
 315         PR gas/24349
 316         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 317         (valid_bo_post_v2): Add support for 'at' branch hints.
 318         (insert_bo): Only error on branch on ctr.
 319         (get_bo_hint_mask): New function.
 320         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 321         for inserting 'at' branch hints.
 322         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 323         for extracting 'at' branch hints.
 324         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 325         (BOE): Delete operand.
 326         (BOM, BOP): New operands.
 327         (RM): Update value.
 328         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 329         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 330         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 331         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 332         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 333         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 334         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 335         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 336         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 337         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 338         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 339         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 340         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 341         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 342         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 343         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 344         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 345         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 346         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 347         bttarl+>: New extended mnemonics.
 348
 349 2019-03-28  Alan Modra  <amodra@gmail.com>
 350
 351         PR 24390
 352         * ppc-opc.c (BTF): Define.
 353         (powerpc_opcodes): Use for mtfsb*.
 354         * ppc-dis.c (print_insn_powerpc): Print fields with both
 355         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 356
 357 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 358
 359         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 360         (mapping_symbol_for_insn): Implement new algorithm.
 361         (print_insn): Remove duplicate code.
 362
 363 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 364
 365         * aarch64-dis.c (print_insn_aarch64):
 366         Implement override.
 367
 368 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 369
 370         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 371         order.
 372
 373 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 374
 375         * aarch64-dis.c (last_stop_offset): New.
 376         (print_insn_aarch64): Use stop_offset.
 377
 378 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 379
 380         PR gas/24359
 381         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 382         CPU_ANY_AVX2_FLAGS.
 383         * i386-init.h: Regenerated.
 384
 385 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 386
 387         PR gas/24348
 388         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 389         vmovdqu16, vmovdqu32 and vmovdqu64.
 390         * i386-tbl.h: Regenerated.
 391
 392 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 393
 394         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 395         from vstrszb, vstrszh, and vstrszf.
 396
 397 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 398
 399         * s390-opc.txt: Add instruction descriptions.
 400
 401 2019-02-08  Jim Wilson  <jimw@sifive.com>
 402
 403         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 404         <bne>: Likewise.
 405
 406 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 407
 408         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 409
 410 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 411
 412         PR binutils/23212
 413         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 414         * aarch64-opc.c (verify_elem_sd): New.
 415         (fields): Add FLD_sz entr.
 416         * aarch64-tbl.h (_SIMD_INSN): New.
 417         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 418         fmulx scalar and vector by element isns.
 419
 420 2019-02-07  Nick Clifton  <nickc@redhat.com>
 421
 422         * po/sv.po: Updated Swedish translation.
 423
 424 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 425
 426         * s390-mkopc.c (main): Accept arch13 as cpu string.
 427         * s390-opc.c: Add new instruction formats and instruction opcode
 428         masks.
 429         * s390-opc.txt: Add new arch13 instructions.
 430
 431 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 432
 433         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 434         (aarch64_opcode): Change encoding for stg, stzg
 435         st2g and st2zg.
 436         * aarch64-asm-2.c: Regenerated.
 437         * aarch64-dis-2.c: Regenerated.
 438         * aarch64-opc-2.c: Regenerated.
 439
 440 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 441
 442         * aarch64-asm-2.c: Regenerated.
 443         * aarch64-dis-2.c: Likewise.
 444         * aarch64-opc-2.c: Likewise.
 445         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 446
 447 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 448             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 449
 450         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 451         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 452         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 453         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 454         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 455         case for ldstgv_indexed.
 456         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 457         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 458         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 459         * aarch64-asm-2.c: Regenerated.
 460         * aarch64-dis-2.c: Regenerated.
 461         * aarch64-opc-2.c: Regenerated.
 462
 463 2019-01-23  Nick Clifton  <nickc@redhat.com>
 464
 465         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 466
 467 2019-01-21  Nick Clifton  <nickc@redhat.com>
 468
 469         * po/de.po: Updated German translation.
 470         * po/uk.po: Updated Ukranian translation.
 471
 472 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 473         * mips-dis.c (mips_arch_choices): Fix typo in
 474         gs464, gs464e and gs264e descriptors.
 475
 476 2019-01-19  Nick Clifton  <nickc@redhat.com>
 477
 478         * configure: Regenerate.
 479         * po/opcodes.pot: Regenerate.
 480
 481 2018-06-24  Nick Clifton  <nickc@redhat.com>
 482
 483         2.32 branch created.
 484
 485 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 486
 487         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 488         if it is null.
 489         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 490         zero.
 491
 492 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 493
 494         * configure: Regenerate.
 495
 496 2019-01-07  Alan Modra  <amodra@gmail.com>
 497
 498         * configure: Regenerate.
 499         * po/POTFILES.in: Regenerate.
 500
 501 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 502
 503         * s12z-opc.c: New file.
 504         * s12z-opc.h: New file.
 505         * s12z-dis.c: Removed all code not directly related to display
 506         of instructions.  Used the interface provided by the new files
 507         instead.
 508         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 509         * Makefile.in: Regenerate.
 510         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 511         * configure: Regenerate.
 512
 513 2019-01-01  Alan Modra  <amodra@gmail.com>
 514
 515         Update year range in copyright notice of all files.
 516
 517 For older changes see ChangeLog-2018
 518 \f
 519 Copyright (C) 2019 Free Software Foundation, Inc.
 520
 521 Copying and distribution of this file, with or without modification,
 522 are permitted in any medium without royalty provided the copyright
 523 notice and this notice are preserved.
 524
 525 Local Variables:
 526 mode: change-log
 527 left-margin: 8
 528 fill-column: 74
 529 version-control: never
 530 End: