1 2016-06-30 Yao Qi <yao.qi@linaro.org>
3 * arm-dis.c (print_insn): Fix typo in comment.
5 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
7 * aarch64-opc.c (operand_general_constraint_met_p): Check the
8 range of ldst_elemlist operands.
9 (print_register_list): Use PRIi64 to print the index.
10 (aarch64_print_operand): Likewise.
12 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
14 * mcore-opc.h: Remove sentinal.
15 * mcore-dis.c (print_insn_mcore): Adjust.
17 2016-06-23 Graham Markall <graham.markall@embecosm.com>
19 * arc-opc.c: Correct description of availability of NPS400
22 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
24 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
25 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
26 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
28 <setb>: Change to a VX form instruction.
29 (insert_sh6): Add support for rldixor.
30 (extract_sh6): Likewise.
32 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
34 * arc-ext.h: Wrap in extern C.
36 2016-06-21 Graham Markall <graham.markall@embecosm.com>
38 * arc-dis.c (arc_insn_length): Add comment on instruction length.
39 Use same method for determining instruction length on ARC700 and
41 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
42 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
43 with the NPS400 subclass.
44 * arc-opc.c: Likewise.
46 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
48 * sparc-opc.c (rdasr): New macro.
54 (sparc_opcodes): Use the macros above to fix and expand the
55 definition of read/write instructions from/to
56 asr/privileged/hyperprivileged instructions.
57 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
58 %hva_mask_nz. Prefer softint_set and softint_clear over
59 set_softint and clear_softint.
60 (print_insn_sparc): Support %ver in Rd.
62 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
64 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
65 architecture according to the hardware capabilities they require.
67 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
69 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
70 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
71 bfd_mach_sparc_v9{c,d,e,v,m}.
72 * sparc-opc.c (MASK_V9C): Define.
77 (v6): Add MASK_V9{C,D,E,V,M}.
82 (v9andleon): Likewise.
90 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
92 2016-06-15 Nick Clifton <nickc@redhat.com>
94 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
95 constants to match expected behaviour.
96 (nds32_parse_opcode): Likewise. Also for whitespace.
98 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
100 * arc-opc.c (extract_rhv1): Extract value from insn.
102 2016-06-14 Graham Markall <graham.markall@embecosm.com>
104 * arc-nps400-tbl.h: Add ldbit instruction.
105 * arc-opc.c: Add flag classes required for ldbit.
107 2016-06-14 Graham Markall <graham.markall@embecosm.com>
109 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
110 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
111 support the above instructions.
113 2016-06-14 Graham Markall <graham.markall@embecosm.com>
115 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
116 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
117 csma, cbba, zncv, and hofs.
118 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
119 support the above instructions.
121 2016-06-06 Graham Markall <graham.markall@embecosm.com>
123 * arc-nps400-tbl.h: Add andab and orab instructions.
125 2016-06-06 Graham Markall <graham.markall@embecosm.com>
127 * arc-nps400-tbl.h: Add addl-like instructions.
129 2016-06-06 Graham Markall <graham.markall@embecosm.com>
131 * arc-nps400-tbl.h: Add mxb and imxb instructions.
133 2016-06-06 Graham Markall <graham.markall@embecosm.com>
135 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
138 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
140 * s390-dis.c (option_use_insn_len_bits_p): New file scope
142 (init_disasm): Handle new command line option "insnlength".
143 (print_s390_disassembler_options): Mention new option in help
145 (print_insn_s390): Use the encoded insn length when dumping
146 unknown instructions.
148 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
150 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
151 to the address and set as symbol address for LDS/ STS immediate operands.
153 2016-06-07 Alan Modra <amodra@gmail.com>
155 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
156 cpu for "vle" to e500.
157 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
158 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
159 (PPCNONE): Delete, substitute throughout.
160 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
161 except for major opcode 4 and 31.
162 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
164 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
166 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
167 ARM_EXT_RAS in relevant entries.
169 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
172 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
175 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
178 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
180 Add comments for '&'.
181 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
183 (intel_operand_size): Handle indir_v_mode.
184 (OP_E_register): Likewise.
185 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
186 64-bit indirect call/jmp for AMD64.
187 * i386-tbl.h: Regenerated
189 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
191 * arc-dis.c (struct arc_operand_iterator): New structure.
192 (find_format_from_table): All the old content from find_format,
193 with some minor adjustments, and parameter renaming.
194 (find_format_long_instructions): New function.
195 (find_format): Rewritten.
196 (arc_insn_length): Add LSB parameter.
197 (extract_operand_value): New function.
198 (operand_iterator_next): New function.
199 (print_insn_arc): Use new functions to find opcode, and iterator
201 * arc-opc.c (insert_nps_3bit_dst_short): New function.
202 (extract_nps_3bit_dst_short): New function.
203 (insert_nps_3bit_src2_short): New function.
204 (extract_nps_3bit_src2_short): New function.
205 (insert_nps_bitop1_size): New function.
206 (extract_nps_bitop1_size): New function.
207 (insert_nps_bitop2_size): New function.
208 (extract_nps_bitop2_size): New function.
209 (insert_nps_bitop_mod4_msb): New function.
210 (extract_nps_bitop_mod4_msb): New function.
211 (insert_nps_bitop_mod4_lsb): New function.
212 (extract_nps_bitop_mod4_lsb): New function.
213 (insert_nps_bitop_dst_pos3_pos4): New function.
214 (extract_nps_bitop_dst_pos3_pos4): New function.
215 (insert_nps_bitop_ins_ext): New function.
216 (extract_nps_bitop_ins_ext): New function.
217 (arc_operands): Add new operands.
218 (arc_long_opcodes): New global array.
219 (arc_num_long_opcodes): New global.
220 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
222 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
224 * nds32-asm.h: Add extern "C".
225 * sh-opc.h: Likewise.
227 2016-06-01 Graham Markall <graham.markall@embecosm.com>
229 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
230 0,b,limm to the rflt instruction.
232 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
234 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
237 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
240 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
241 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
242 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
243 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
244 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
245 * i386-init.h: Regenerated.
247 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
250 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
251 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
252 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
253 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
254 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
255 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
256 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
257 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
258 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
259 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
260 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
261 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
262 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
263 CpuRegMask for AVX512.
264 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
266 (set_bitfield_from_cpu_flag_init): New function.
267 (set_bitfield): Remove const on f. Call
268 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
269 * i386-opc.h (CpuRegMMX): New.
270 (CpuRegXMM): Likewise.
271 (CpuRegYMM): Likewise.
272 (CpuRegZMM): Likewise.
273 (CpuRegMask): Likewise.
274 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
276 * i386-init.h: Regenerated.
277 * i386-tbl.h: Likewise.
279 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
282 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
283 (opcode_modifiers): Add AMD64 and Intel64.
284 (main): Properly verify CpuMax.
285 * i386-opc.h (CpuAMD64): Removed.
286 (CpuIntel64): Likewise.
287 (CpuMax): Set to CpuNo64.
288 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
291 (i386_opcode_modifier): Add amd64 and intel64.
292 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
294 * i386-init.h: Regenerated.
295 * i386-tbl.h: Likewise.
297 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
300 * i386-gen.c (main): Fail if CpuMax is incorrect.
301 * i386-opc.h (CpuMax): Set to CpuIntel64.
302 * i386-tbl.h: Regenerated.
304 2016-05-27 Nick Clifton <nickc@redhat.com>
307 * msp430-dis.c (msp430dis_read_two_bytes): New function.
308 (msp430dis_opcode_unsigned): New function.
309 (msp430dis_opcode_signed): New function.
310 (msp430_singleoperand): Use the new opcode reading functions.
311 Only disassenmble bytes if they were successfully read.
312 (msp430_doubleoperand): Likewise.
313 (msp430_branchinstr): Likewise.
314 (msp430x_callx_instr): Likewise.
315 (print_insn_msp430): Check that it is safe to read bytes before
316 attempting disassembly. Use the new opcode reading functions.
318 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
320 * ppc-opc.c (CY): New define. Document it.
321 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
323 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
325 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
326 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
327 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
328 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
330 * i386-init.h: Regenerated.
332 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
335 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
336 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
337 * i386-init.h: Regenerated.
339 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
341 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
342 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
343 * i386-init.h: Regenerated.
345 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
347 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
349 (print_insn_arc): Set insn_type information.
350 * arc-opc.c (C_CC): Add F_CLASS_COND.
351 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
352 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
353 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
354 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
355 (brne, brne_s, jeq_s, jne_s): Likewise.
357 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
359 * arc-tbl.h (neg): New instruction variant.
361 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
363 * arc-dis.c (find_format, find_format, get_auxreg)
364 (print_insn_arc): Changed.
365 * arc-ext.h (INSERT_XOP): Likewise.
367 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
369 * tic54x-dis.c (sprint_mmr): Adjust.
370 * tic54x-opc.c: Likewise.
372 2016-05-19 Alan Modra <amodra@gmail.com>
374 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
376 2016-05-19 Alan Modra <amodra@gmail.com>
378 * ppc-opc.c: Formatting.
379 (NSISIGNOPT): Define.
380 (powerpc_opcodes <subis>): Use NSISIGNOPT.
382 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
384 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
385 replacing references to `micromips_ase' throughout.
386 (_print_insn_mips): Don't use file-level microMIPS annotation to
387 determine the disassembly mode with the symbol table.
389 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
391 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
393 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
395 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
397 * mips-opc.c (D34): New macro.
398 (mips_builtin_opcodes): Define bposge32c for DSPr3.
400 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
402 * i386-dis.c (prefix_table): Add RDPID instruction.
403 * i386-gen.c (cpu_flag_init): Add RDPID flag.
404 (cpu_flags): Add RDPID bitfield.
405 * i386-opc.h (enum): Add RDPID element.
406 (i386_cpu_flags): Add RDPID field.
407 * i386-opc.tbl: Add RDPID instruction.
408 * i386-init.h: Regenerate.
409 * i386-tbl.h: Regenerate.
411 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
413 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
414 branch type of a symbol.
415 (print_insn): Likewise.
417 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
419 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
420 Mainline Security Extensions instructions.
421 (thumb_opcodes): Add entries for narrow ARMv8-M Security
422 Extensions instructions.
423 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
425 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
428 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
430 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
432 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
434 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
435 (arcExtMap_genOpcode): Likewise.
436 * arc-opc.c (arg_32bit_rc): Define new variable.
437 (arg_32bit_u6): Likewise.
438 (arg_32bit_limm): Likewise.
440 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
442 * aarch64-gen.c (VERIFIER): Define.
443 * aarch64-opc.c (VERIFIER): Define.
444 (verify_ldpsw): Use static linkage.
445 * aarch64-opc.h (verify_ldpsw): Remove.
446 * aarch64-tbl.h: Use VERIFIER for verifiers.
448 2016-04-28 Nick Clifton <nickc@redhat.com>
451 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
452 * aarch64-opc.c (verify_ldpsw): New function.
453 * aarch64-opc.h (verify_ldpsw): New prototype.
454 * aarch64-tbl.h: Add initialiser for verifier field.
455 (LDPSW): Set verifier to verify_ldpsw.
457 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
461 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
462 smaller than address size.
464 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
466 * alpha-dis.c: Regenerate.
467 * crx-dis.c: Likewise.
468 * disassemble.c: Likewise.
469 * epiphany-opc.c: Likewise.
470 * fr30-opc.c: Likewise.
471 * frv-opc.c: Likewise.
472 * ip2k-opc.c: Likewise.
473 * iq2000-opc.c: Likewise.
474 * lm32-opc.c: Likewise.
475 * lm32-opinst.c: Likewise.
476 * m32c-opc.c: Likewise.
477 * m32r-opc.c: Likewise.
478 * m32r-opinst.c: Likewise.
479 * mep-opc.c: Likewise.
480 * mt-opc.c: Likewise.
481 * or1k-opc.c: Likewise.
482 * or1k-opinst.c: Likewise.
483 * tic80-opc.c: Likewise.
484 * xc16x-opc.c: Likewise.
485 * xstormy16-opc.c: Likewise.
487 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
489 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
490 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
491 calcsd, and calcxd instructions.
492 * arc-opc.c (insert_nps_bitop_size): Delete.
493 (extract_nps_bitop_size): Delete.
494 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
495 (extract_nps_qcmp_m3): Define.
496 (extract_nps_qcmp_m2): Define.
497 (extract_nps_qcmp_m1): Define.
498 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
499 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
500 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
501 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
502 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
505 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
507 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
509 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
511 * Makefile.in: Regenerated with automake 1.11.6.
512 * aclocal.m4: Likewise.
514 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
516 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
518 * arc-opc.c (insert_nps_cmem_uimm16): New function.
519 (extract_nps_cmem_uimm16): New function.
520 (arc_operands): Add NPS_XLDST_UIMM16 operand.
522 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
524 * arc-dis.c (arc_insn_length): New function.
525 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
526 (find_format): Change insnLen parameter to unsigned.
528 2016-04-13 Nick Clifton <nickc@redhat.com>
531 * v850-opc.c (v850_opcodes): Correct masks for long versions of
532 the LD.B and LD.BU instructions.
534 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
536 * arc-dis.c (find_format): Check for extension flags.
537 (print_flags): New function.
538 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
540 * arc-ext.c (arcExtMap_coreRegName): Use
541 LAST_EXTENSION_CORE_REGISTER.
542 (arcExtMap_coreReadWrite): Likewise.
543 (dump_ARC_extmap): Update printing.
544 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
545 (arc_aux_regs): Add cpu field.
546 * arc-regs.h: Add cpu field, lower case name aux registers.
548 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
550 * arc-tbl.h: Add rtsc, sleep with no arguments.
552 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
554 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
556 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
557 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
558 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
559 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
560 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
561 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
562 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
563 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
564 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
565 (arc_opcode arc_opcodes): Null terminate the array.
566 (arc_num_opcodes): Remove.
567 * arc-ext.h (INSERT_XOP): Define.
568 (extInstruction_t): Likewise.
569 (arcExtMap_instName): Delete.
570 (arcExtMap_insn): New function.
571 (arcExtMap_genOpcode): Likewise.
572 * arc-ext.c (ExtInstruction): Remove.
573 (create_map): Zero initialize instruction fields.
574 (arcExtMap_instName): Remove.
575 (arcExtMap_insn): New function.
576 (dump_ARC_extmap): More info while debuging.
577 (arcExtMap_genOpcode): New function.
578 * arc-dis.c (find_format): New function.
579 (print_insn_arc): Use find_format.
580 (arc_get_disassembler): Enable dump_ARC_extmap only when
583 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
585 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
586 instruction bits out.
588 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
590 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
591 * arc-opc.c (arc_flag_operands): Add new flags.
592 (arc_flag_classes): Add new classes.
594 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
596 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
598 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
600 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
601 encode1, rflt, crc16, and crc32 instructions.
602 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
603 (arc_flag_classes): Add C_NPS_R.
604 (insert_nps_bitop_size_2b): New function.
605 (extract_nps_bitop_size_2b): Likewise.
606 (insert_nps_bitop_uimm8): Likewise.
607 (extract_nps_bitop_uimm8): Likewise.
608 (arc_operands): Add new operand entries.
610 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
612 * arc-regs.h: Add a new subclass field. Add double assist
613 accumulator register values.
614 * arc-tbl.h: Use DPA subclass to mark the double assist
615 instructions. Use DPX/SPX subclas to mark the FPX instructions.
616 * arc-opc.c (RSP): Define instead of SP.
617 (arc_aux_regs): Add the subclass field.
619 2016-04-05 Jiong Wang <jiong.wang@arm.com>
621 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
623 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
625 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
628 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
630 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
631 issues. No functional changes.
633 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
635 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
636 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
637 (RTT): Remove duplicate.
638 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
639 (PCT_CONFIG*): Remove.
640 (D1L, D1H, D2H, D2L): Define.
642 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
644 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
646 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
648 * arc-tbl.h (invld07): Remove.
649 * arc-ext-tbl.h: New file.
650 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
651 * arc-opc.c (arc_opcodes): Add ext-tbl include.
653 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
655 Fix -Wstack-usage warnings.
656 * aarch64-dis.c (print_operands): Substitute size.
657 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
659 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
661 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
662 to get a proper diagnostic when an invalid ASR register is used.
664 2016-03-22 Nick Clifton <nickc@redhat.com>
666 * configure: Regenerate.
668 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
670 * arc-nps400-tbl.h: New file.
671 * arc-opc.c: Add top level comment.
672 (insert_nps_3bit_dst): New function.
673 (extract_nps_3bit_dst): New function.
674 (insert_nps_3bit_src2): New function.
675 (extract_nps_3bit_src2): New function.
676 (insert_nps_bitop_size): New function.
677 (extract_nps_bitop_size): New function.
678 (arc_flag_operands): Add nps400 entries.
679 (arc_flag_classes): Add nps400 entries.
680 (arc_operands): Add nps400 entries.
681 (arc_opcodes): Add nps400 include.
683 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
685 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
686 the new class enum values.
688 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
690 * arc-dis.c (print_insn_arc): Handle nps400.
692 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
694 * arc-opc.c (BASE): Delete.
696 2016-03-18 Nick Clifton <nickc@redhat.com>
699 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
700 of MOV insn that aliases an ORR insn.
702 2016-03-16 Jiong Wang <jiong.wang@arm.com>
704 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
706 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
708 * mcore-opc.h: Add const qualifiers.
709 * microblaze-opc.h (struct op_code_struct): Likewise.
710 * sh-opc.h: Likewise.
711 * tic4x-dis.c (tic4x_print_indirect): Likewise.
712 (tic4x_print_op): Likewise.
714 2016-03-02 Alan Modra <amodra@gmail.com>
716 * or1k-desc.h: Regenerate.
717 * fr30-ibld.c: Regenerate.
718 * rl78-decode.c: Regenerate.
720 2016-03-01 Nick Clifton <nickc@redhat.com>
723 * rl78-dis.c (print_insn_rl78_common): Fix typo.
725 2016-02-24 Renlin Li <renlin.li@arm.com>
727 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
728 (print_insn_coprocessor): Support fp16 instructions.
730 2016-02-24 Renlin Li <renlin.li@arm.com>
732 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
735 2016-02-24 Renlin Li <renlin.li@arm.com>
737 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
738 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
740 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
742 * i386-dis.c (print_insn): Parenthesize expression to prevent
746 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
747 Janek van Oirschot <jvanoirs@synopsys.com>
749 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
752 2016-02-04 Nick Clifton <nickc@redhat.com>
755 * msp430-dis.c (print_insn_msp430): Add a special case for
756 decoding an RRC instruction with the ZC bit set in the extension
759 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
761 * cgen-ibld.in (insert_normal): Rework calculation of shift.
762 * epiphany-ibld.c: Regenerate.
763 * fr30-ibld.c: Regenerate.
764 * frv-ibld.c: Regenerate.
765 * ip2k-ibld.c: Regenerate.
766 * iq2000-ibld.c: Regenerate.
767 * lm32-ibld.c: Regenerate.
768 * m32c-ibld.c: Regenerate.
769 * m32r-ibld.c: Regenerate.
770 * mep-ibld.c: Regenerate.
771 * mt-ibld.c: Regenerate.
772 * or1k-ibld.c: Regenerate.
773 * xc16x-ibld.c: Regenerate.
774 * xstormy16-ibld.c: Regenerate.
776 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
778 * epiphany-dis.c: Regenerated from latest cpu files.
780 2016-02-01 Michael McConville <mmcco@mykolab.com>
782 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
785 2016-01-25 Renlin Li <renlin.li@arm.com>
787 * arm-dis.c (mapping_symbol_for_insn): New function.
788 (find_ifthen_state): Call mapping_symbol_for_insn().
790 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
792 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
793 of MSR UAO immediate operand.
795 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
797 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
800 2016-01-17 Alan Modra <amodra@gmail.com>
802 * configure: Regenerate.
804 2016-01-14 Nick Clifton <nickc@redhat.com>
806 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
807 instructions that can support stack pointer operations.
808 * rl78-decode.c: Regenerate.
809 * rl78-dis.c: Fix display of stack pointer in MOVW based
812 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
814 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
815 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
816 erxtatus_el1 and erxaddr_el1.
818 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
820 * arm-dis.c (arm_opcodes): Add "esb".
821 (thumb_opcodes): Likewise.
823 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
825 * ppc-opc.c <xscmpnedp>: Delete.
826 <xvcmpnedp>: Likewise.
827 <xvcmpnedp.>: Likewise.
828 <xvcmpnesp>: Likewise.
829 <xvcmpnesp.>: Likewise.
831 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
834 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
837 2016-01-01 Alan Modra <amodra@gmail.com>
839 Update year range in copyright notice of all files.
841 For older changes see ChangeLog-2015
843 Copyright (C) 2016 Free Software Foundation, Inc.
845 Copying and distribution of this file, with or without modification,
846 are permitted in any medium without royalty provided the copyright
847 notice and this notice are preserved.
853 version-control: never