opcodes/ChangeLog

   1 2013-09-20  Alan Modra  <amodra@gmail.com>
   2
   3         * configure: Regenerate.
   4
   5 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
   6
   7         * s390-opc.txt (clih): Make the immediate unsigned.
   8
   9 2013-09-04  Roland McGrath  <mcgrathr@google.com>
  10
  11         PR gas/15914
  12         * arm-dis.c (arm_opcodes): Add udf.
  13         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
  14         (thumb32_opcodes): Add udf.w.
  15         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
  16
  17 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  18
  19         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
  20         For the load fp integer instructions only the suppression flag was
  21         new with z196 version.
  22
  23 2013-08-28  Nick Clifton  <nickc@redhat.com>
  24
  25         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
  26         immediate is not suitable for the 32-bit ABI.
  27
  28 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
  29
  30         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
  31         replacing NODS.
  32
  33 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  34
  35         PR binutils/15834
  36         * aarch64-asm.c: Fix typos.
  37         * aarch64-dis.c: Likewise.
  38         * msp430-dis.c: Likewise.
  39
  40 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  41
  42         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
  43         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
  44         Use +H rather than +C for the real "dext".
  45         * mips-opc.c (mips_builtin_opcodes): Likewise.
  46
  47 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  48
  49         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  50         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  51         and OPTIONAL_MAPPED_REG.
  52         * mips-opc.c (decode_mips_operand): Likewise.
  53         * mips16-opc.c (decode_mips16_operand): Likewise.
  54         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  55
  56 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  57
  58         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
  59         (PREFIX_EVEX_0F3A3F): Likewise.
  60         * i386-dis-evex.h (evex_table): Updated.
  61
  62 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
  63
  64         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
  65         VCLIPW.
  66
  67 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
  68             Konrad Eisele  <konrad@gaisler.com>
  69
  70         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
  71         bfd_mach_sparc.
  72         * sparc-opc.c (MASK_LEON): Define.
  73         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
  74         (letandleon): New macro.
  75         (v9andleon): Likewise.
  76         (sparc_opc): Add leon.
  77         (umac): Enable for letandleon.
  78         (smac): Likewise.
  79         (casa): Enable for v9andleon.
  80         (cas): Likewise.
  81         (casl): Likewise.
  82
  83 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  84             Richard Sandiford  <rdsandiford@googlemail.com>
  85
  86         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
  87         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
  88         (print_vu0_channel): New function.
  89         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
  90         (print_insn_args): Handle '#'.
  91         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
  92         * mips-opc.c (mips_vu0_channel_mask): New constant.
  93         (decode_mips_operand): Handle new VU0 operand types.
  94         (VU0, VU0CH): New macros.
  95         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
  96         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
  97         Use "+6" rather than "G" for QMFC2 and QMTC2.
  98
  99 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 100
 101         * mips-formats.h (PCREL): Reorder parameters and update the definition
 102         to match new mips_pcrel_operand layout.
 103         (JUMP, JALX, BRANCH): Update accordingly.
 104         * mips16-opc.c (decode_mips16_operand): Likewise.
 105
 106 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 107
 108         * micromips-opc.c (WR_s): Delete.
 109
 110 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 111
 112         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 113         New macros.
 114         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 115         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 116         (mips_builtin_opcodes): Use the new position-based read-write flags
 117         instead of field-based ones.  Use UDI for "udi..." instructions.
 118         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 119         New macros.
 120         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 121         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 122         (WR_SP, RD_16): New macros.
 123         (RD_SP): Redefine as an INSN2_* flag.
 124         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 125         (mips16_opcodes): Use the new position-based read-write flags
 126         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 127         pinfo2 field.
 128         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 129         New macros.
 130         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 131         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 132         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 133         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 134         (micromips_opcodes): Use the new position-based read-write flags
 135         instead of field-based ones.
 136         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 137         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 138         of field-based flags.
 139
 140 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 141
 142         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 143         (WR_SP): Replace with...
 144         (MOD_SP): ...this.
 145         (mips16_opcodes): Update accordingly.
 146         * mips-dis.c (print_insn_mips16): Likewise.
 147
 148 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 149
 150         * mips16-opc.c (mips16_opcodes): Reformat.
 151
 152 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 153
 154         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 155         for operands that are hard-coded to $0.
 156         * micromips-opc.c (micromips_opcodes): Likewise.
 157
 158 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 159
 160         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 161         for the single-operand forms of JALR and JALR.HB.
 162         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 163         and JALRS.HB.
 164
 165 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 166
 167         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 168         instructions.  Fix them to use WR_MACC instead of WR_CC and
 169         add missing RD_MACCs.
 170
 171 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 172
 173         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 174
 175 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 176
 177         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 178
 179 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 180             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 181             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 182             Sergey Lega  <sergey.s.lega@intel.com>
 183             Anna Tikhonova  <anna.tikhonova@intel.com>
 184             Ilya Tocar  <ilya.tocar@intel.com>
 185             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 186             Ilya Verbin  <ilya.verbin@intel.com>
 187             Kirill Yukhin  <kirill.yukhin@intel.com>
 188             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 189
 190         * i386-dis-evex.h: New.
 191         * i386-dis.c (OP_Rounding): New.
 192         (VPCMP_Fixup): New.
 193         (OP_Mask): New.
 194         (Rdq): New.
 195         (XMxmmq): New.
 196         (EXdScalarS): New.
 197         (EXymm): New.
 198         (EXEvexHalfBcstXmmq): New.
 199         (EXxmm_mdq): New.
 200         (EXEvexXGscat): New.
 201         (EXEvexXNoBcst): New.
 202         (VPCMP): New.
 203         (EXxEVexR): New.
 204         (EXxEVexS): New.
 205         (XMask): New.
 206         (MaskG): New.
 207         (MaskE): New.
 208         (MaskR): New.
 209         (MaskVex): New.
 210         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 211         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 212         evex_rounding_mode, evex_sae_mode, mask_mode.
 213         (USE_EVEX_TABLE): New.
 214         (EVEX_TABLE): New.
 215         (EVEX enum): New.
 216         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 217         REG_EVEX_0F38C7.
 218         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 219         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 220         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 221         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 222         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 223         MOD_EVEX_0F38C7_REG_6.
 224         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 225         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 226         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 227         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 228         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 229         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 230         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 231         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 232         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 233         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 234         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 235         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 236         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 237         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 238         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 239         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 240         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 241         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 242         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 243         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 244         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 245         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 246         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 247         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 248         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 249         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 250         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 251         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 252         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 253         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 254         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 255         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 256         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 257         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 258         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 259         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 260         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 261         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 262         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 263         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 264         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 265         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 266         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 267         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 268         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 269         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 270         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 271         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 272         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 273         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 274         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 275         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 276         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 277         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 278         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 279         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 280         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 281         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 282         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 283         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 284         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 285         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 286         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 287         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 288         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 289         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 290         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 291         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 292         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 293         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 294         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 295         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 296         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 297         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 298         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 299         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 300         PREFIX_EVEX_0F3A55.
 301         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 302         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 303         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 304         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 305         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 306         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 307         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 308         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 309         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 310         VEX_W_0F3A32_P_2_LEN_0.
 311         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 312         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 313         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 314         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 315         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 316         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 317         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 318         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 319         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 320         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 321         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 322         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 323         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 324         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 325         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 326         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 327         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 328         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 329         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 330         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 331         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 332         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 333         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 334         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 335         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 336         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 337         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 338         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 339         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 340         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 341         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 342         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 343         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 344         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 345         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 346         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 347         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 348         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 349         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 350         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 351         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 352         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 353         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 354         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 355         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 356         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 357         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 358         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 359         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 360         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 361         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 362         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 363         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 364         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 365         (struct vex): Add fields evex, r, v, mask_register_specifier,
 366         zeroing, ll, b.
 367         (intel_names_xmm): Add upper 16 registers.
 368         (att_names_xmm): Ditto.
 369         (intel_names_ymm): Ditto.
 370         (att_names_ymm): Ditto.
 371         (names_zmm): New.
 372         (intel_names_zmm): Ditto.
 373         (att_names_zmm): Ditto.
 374         (names_mask): Ditto.
 375         (intel_names_mask): Ditto.
 376         (att_names_mask): Ditto.
 377         (names_rounding): Ditto.
 378         (names_broadcast): Ditto.
 379         (x86_64_table): Add escape to evex-table.
 380         (reg_table): Include reg_table evex-entries from
 381         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 382         (prefix_table): Add entries for new instructions.
 383         (vex_table): Ditto.
 384         (vex_len_table): Ditto.
 385         (vex_w_table): Ditto.
 386         (mod_table): Ditto.
 387         (get_valid_dis386): Properly handle new instructions.
 388         (print_insn): Handle zmm and mask registers, print mask operand.
 389         (intel_operand_size): Support EVEX, new modes and sizes.
 390         (OP_E_register): Handle new modes.
 391         (OP_E_memory): Ditto.
 392         (OP_G): Ditto.
 393         (OP_XMM): Ditto.
 394         (OP_EX): Ditto.
 395         (OP_VEX): Ditto.
 396         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 397         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 398         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 399         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 400         CpuAVX512PF and CpuVREX.
 401         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 402         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 403         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 404         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 405         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 406         * i386-init.h: Regenerate.
 407         * i386-opc.h (CpuAVX512F): New.
 408         (CpuAVX512CD): New.
 409         (CpuAVX512ER): New.
 410         (CpuAVX512PF): New.
 411         (CpuVREX): New.
 412         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 413         cpuavx512pf and cpuvrex fields.
 414         (VecSIB): Add VecSIB512.
 415         (EVex): New.
 416         (Masking): New.
 417         (VecESize): New.
 418         (Broadcast): New.
 419         (StaticRounding): New.
 420         (SAE): New.
 421         (Disp8MemShift): New.
 422         (NoDefMask): New.
 423         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 424         staticrounding, sae, disp8memshift and nodefmask.
 425         (RegZMM): New.
 426         (Zmmword): Ditto.
 427         (Vec_Disp8): Ditto.
 428         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 429         fields.
 430         (RegVRex): New.
 431         * i386-opc.tbl: Add AVX512 instructions.
 432         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 433         registers, mask registers.
 434         * i386-tbl.h: Regenerate.
 435
 436 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 437
 438         PR gas/15220
 439         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 440         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 441
 442 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 443
 444         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 445         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 446         PREFIX_0F3ACC.
 447         (prefix_table): Updated.
 448         (three_byte_table): Likewise.
 449         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 450         (cpu_flags): Add CpuSHA.
 451         (i386_cpu_flags): Add cpusha.
 452         * i386-init.h: Regenerate.
 453         * i386-opc.h (CpuSHA): New.
 454         (CpuUnused): Restored.
 455         (i386_cpu_flags): Add cpusha.
 456         * i386-opc.tbl: Add SHA instructions.
 457         * i386-tbl.h: Regenerate.
 458
 459 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 460             Kirill Yukhin  <kirill.yukhin@intel.com>
 461             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 462
 463         * i386-dis.c (BND_Fixup): New.
 464         (Ebnd): New.
 465         (Ev_bnd): New.
 466         (Gbnd): New.
 467         (BND): New.
 468         (v_bnd_mode): New.
 469         (bnd_mode): New.
 470         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 471         MOD_0F1B_PREFIX_1.
 472         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 473         (dis tables): Replace XX with BND for near branch and call
 474         instructions.
 475         (prefix_table): Add new entries.
 476         (mod_table): Likewise.
 477         (names_bnd): New.
 478         (intel_names_bnd): New.
 479         (att_names_bnd): New.
 480         (BND_PREFIX): New.
 481         (prefix_name): Handle BND_PREFIX.
 482         (print_insn): Initialize names_bnd.
 483         (intel_operand_size): Handle new modes.
 484         (OP_E_register): Likewise.
 485         (OP_E_memory): Likewise.
 486         (OP_G): Likewise.
 487         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 488         (cpu_flags): Add CpuMPX.
 489         (operand_type_init): Add RegBND.
 490         (opcode_modifiers): Add BNDPrefixOk.
 491         (operand_types): Add RegBND.
 492         * i386-init.h: Regenerate.
 493         * i386-opc.h (CpuMPX): New.
 494         (CpuUnused): Comment out.
 495         (i386_cpu_flags): Add cpumpx.
 496         (BNDPrefixOk): New.
 497         (i386_opcode_modifier): Add bndprefixok.
 498         (RegBND): New.
 499         (i386_operand_type): Add regbnd.
 500         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 501         Add MPX instructions and bnd prefix.
 502         * i386-reg.tbl: Add bnd0-bnd3 registers.
 503         * i386-tbl.h: Regenerate.
 504
 505 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 506
 507         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 508         ATTRIBUTE_UNUSED.
 509
 510 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 511
 512         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 513         special rules.
 514         * Makefile.in: Regenerate.
 515         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 516         all fields.  Reformat.
 517
 518 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 519
 520         * mips16-opc.c: Include mips-formats.h.
 521         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 522         static arrays.
 523         (decode_mips16_operand): New function.
 524         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 525         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 526         Abort for OP_SAVE_RESTORE_LIST.
 527         (print_mips16_insn_arg): Change interface.  Use mips_operand
 528         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 529         (print_insn_mips16): ...here.  Call init_print_arg_state.
 530         Update the call to print_mips16_insn_arg.
 531
 532 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 533
 534         * mips-formats.h: New file.
 535         * mips-opc.c: Include mips-formats.h.
 536         (reg_0_map): New static array.
 537         (decode_mips_operand): New function.
 538         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 539         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 540         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 541         (int_c_map): New static arrays.
 542         (decode_micromips_operand): New function.
 543         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 544         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 545         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 546         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 547         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 548         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 549         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 550         (print_reg): New function.
 551         (mips_print_arg_state): New structure.
 552         (init_print_arg_state, print_insn_arg): New functions.
 553         (print_insn_args): Change interface and use mips_operand structures.
 554         Delete GET_OP_S.  Move GET_OP definition to...
 555         (print_insn_mips): ...here.  Update the call to print_insn_args.
 556         (print_insn_micromips): Use print_insn_args.
 557
 558 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 559
 560         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 561         in macros.
 562
 563 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 564
 565         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 566         ADDA.S, MULA.S and SUBA.S.
 567
 568 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 569
 570         PR gas/13572
 571         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 572         * i386-tbl.h: Regenerated.
 573
 574 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 575
 576         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 577         and SD A(B) macros up.
 578         * micromips-opc.c (micromips_opcodes): Likewise.
 579
 580 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 581
 582         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 583         instructions.
 584
 585 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 586
 587         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 588         MDMX-like instructions.
 589         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 590         printing "Q" operands for INSN_5400 instructions.
 591
 592 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 593
 594         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 595         "+S" for "cins".
 596         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 597         Combine cases.
 598
 599 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 600
 601         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 602         "jalx".
 603         * mips16-opc.c (mips16_opcodes): Likewise.
 604         * micromips-opc.c (micromips_opcodes): Likewise.
 605         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 606         (print_insn_mips16): Handle "+i".
 607         (print_insn_micromips): Likewise.  Conditionally preserve the
 608         ISA bit for "a" but not for "+i".
 609
 610 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 611
 612         * micromips-opc.c (WR_mhi): Rename to..
 613         (WR_mh): ...this.
 614         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 615         "mh,mi" with "mh".
 616         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 617         (micromips_to_32_reg_h_map1): ...this.
 618         (micromips_to_32_reg_i_map): Rename to...
 619         (micromips_to_32_reg_h_map2): ...this.
 620         (print_micromips_insn): Remove "mi" case.  Print both registers
 621         in the pair for "mh".
 622
 623 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 624
 625         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 626         * micromips-opc.c (micromips_opcodes): Likewise.
 627         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 628         and "+T" handling.  Check for a "0" suffix when deciding whether to
 629         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 630
 631 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 632
 633         * s390-opc.c (J12_12, J24_24): New macros.
 634         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 635         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 636         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 637
 638 2013-07-04  Alan Modra  <amodra@gmail.com>
 639
 640         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 641
 642 2013-06-26  Nick Clifton  <nickc@redhat.com>
 643
 644         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 645         field when checking for type 2 nop.
 646         * rx-decode.c: Regenerate.
 647
 648 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 649
 650         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 651         and "movep" macros.
 652
 653 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 654
 655         * mips-dis.c (is_mips16_plt_tail): New function.
 656         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 657         word.
 658         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 659
 660 2013-06-21  DJ Delorie  <dj@redhat.com>
 661
 662         * msp430-decode.opc: New.
 663         * msp430-decode.c: New/generated.
 664         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 665         (MAINTAINER_CLEANFILES): Likewise.
 666         Add rule to build msp430-decode.c frommsp430decode.opc
 667         using the opc2c program.
 668         * Makefile.in: Regenerate.
 669         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 670         * configure: Regenerate.
 671
 672 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 673
 674         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 675         (SYMTAB_AVAILABLE): Removed.
 676         (#include "elf/aarch64.h): Ditto.
 677
 678 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 679             Maciej W. Rozycki  <macro@codesourcery.com>
 680             Chao-Ying Fu  <fu@mips.com>
 681
 682         * micromips-opc.c (EVA): Define.
 683         (TLBINV): Define.
 684         (micromips_opcodes): Add EVA opcodes.
 685         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 686         (print_insn_args): Handle EVA offsets.
 687         (print_insn_micromips): Likewise.
 688         * mips-opc.c (EVA): Define.
 689         (TLBINV): Define.
 690         (mips_builtin_opcodes): Add EVA opcodes.
 691
 692 2013-06-17  Alan Modra  <amodra@gmail.com>
 693
 694         * Makefile.am (mips-opc.lo): Add rules to create automatic
 695         dependency files.  Pass archdefs.
 696         (micromips-opc.lo, mips16-opc.lo): Likewise.
 697         * Makefile.in: Regenerate.
 698
 699 2013-06-14  DJ Delorie  <dj@redhat.com>
 700
 701         * rx-decode.opc (rx_decode_opcode): Bit operations on
 702         registers are 32-bit operations, not 8-bit operations.
 703         * rx-decode.c: Regenerate.
 704
 705 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 706
 707         * micromips-opc.c (IVIRT): New define.
 708         (IVIRT64): New define.
 709         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 710         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 711
 712         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 713         dmtgc0 to print cp0 names.
 714
 715 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 716
 717         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 718         argument.
 719
 720 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 721             Richard Sandiford  <rdsandiford@googlemail.com>
 722
 723         * micromips-opc.c (D32, D33, MC): Update definitions.
 724         (micromips_opcodes):  Initialize ase field.
 725         * mips-dis.c (mips_arch_choice): Add ase field.
 726         (mips_arch_choices): Initialize ase field.
 727         (set_default_mips_dis_options): Declare and setup mips_ase.
 728         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 729         MT32, MC): Update definitions.
 730         (mips_builtin_opcodes): Initialize ase field.
 731
 732 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 733
 734         * s390-opc.txt (flogr): Require a register pair destination.
 735
 736 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 737
 738         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 739         instruction format.
 740
 741 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 742
 743         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 744
 745 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 746
 747         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 748         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 749         XLS_MASK, PPCVSX2): New defines.
 750         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 751         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 752         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 753         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 754         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 755         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 756         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 757         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 758         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 759         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 760         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 761         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 762         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 763         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 764         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 765         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 766         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 767         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 768         <lxvx, stxvx>: New extended mnemonics.
 769
 770 2013-05-17  Alan Modra  <amodra@gmail.com>
 771
 772         * ia64-raw.tbl: Replace non-ASCII char.
 773         * ia64-waw.tbl: Likewise.
 774         * ia64-asmtab.c: Regenerate.
 775
 776 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 777
 778         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 779         * i386-init.h: Regenerated.
 780
 781 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 782
 783         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 784         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 785         check from [0, 255] to [-128, 255].
 786
 787 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 788
 789         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 790         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 791         (parse_mips_dis_option): Handle the virt option.
 792         (print_insn_args): Handle "+J".
 793         (print_mips_disassembler_options): Print out message about virt64.
 794         * mips-opc.c (IVIRT): New define.
 795         (IVIRT64): New define.
 796         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 797         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 798         Move rfe to the bottom as it conflicts with tlbgp.
 799
 800 2013-05-09  Alan Modra  <amodra@gmail.com>
 801
 802         * ppc-opc.c (extract_vlesi): Properly sign extend.
 803         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 804
 805 2013-05-02  Nick Clifton  <nickc@redhat.com>
 806
 807         * msp430-dis.c: Add support for MSP430X instructions.
 808
 809 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 810
 811         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 812         to "eccinj".
 813
 814 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 815
 816         PR binutils/15369
 817         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 818         of CGEN_CPU_ENDIAN.
 819         (hash_insns_list): Likewise.
 820
 821 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 822
 823         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 824         warning workaround.
 825
 826 2013-04-08  Jan Beulich <jbeulich@suse.com>
 827
 828         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 829         * i386-tbl.h: Re-generate.
 830
 831 2013-04-06  David S. Miller  <davem@davemloft.net>
 832
 833         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 834         of an opcode, prefer the one with F_PREFERRED set.
 835         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 836         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 837         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 838         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 839         instructions generating condition codes, mark existing mnenomics
 840         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 841         existing mnenomics as aliases.
 842
 843 2013-04-03  Nick Clifton  <nickc@redhat.com>
 844
 845         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 846         destination address by subtracting the operand from the current
 847         address.
 848         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 849         a positive value in the insn.
 850         (extract_u16_loop): Do not negate the returned value.
 851         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 852
 853         (ceilf.sw): Remove duplicate entry.
 854         (cvtf.hs): New entry.
 855         (cvtf.sh): Likewise.
 856         (fmaf.s): Likewise.
 857         (fmsf.s): Likewise.
 858         (fnmaf.s): Likewise.
 859         (fnmsf.s): Likewise.
 860         (maddf.s): Restrict to E3V5 architectures.
 861         (msubf.s): Likewise.
 862         (nmaddf.s): Likewise.
 863         (nmsubf.s): Likewise.
 864
 865 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 866
 867         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 868         check address mode.
 869         (print_insn): Pass sizeflag to get_sib.
 870
 871 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 872
 873         PR binutils/15068
 874         * tic6x-dis.c: Add support for displaying 16-bit insns.
 875
 876 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 877
 878         PR gas/15095
 879         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 880         individual msb and lsb halves in src1 & src2 fields.  Discard the
 881         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 882         follow what Ti SDK does in that case as any value in the src1
 883         field yields the same output with SDK disassembler.
 884
 885 2013-03-12  Michael Eager <eager@eagercon.com>
 886
 887         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 888
 889 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 890
 891         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 892
 893 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 894
 895         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 896
 897 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 898
 899         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 900
 901 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 902
 903         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 904         (thumb32_opcodes): Likewise.
 905         (print_insn_thumb32): Handle 'S' control char.
 906
 907 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 908
 909         * lm32-desc.c: Regenerate.
 910
 911 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 912
 913         * i386-reg.tbl (riz): Add RegRex64.
 914         * i386-tbl.h: Regenerated.
 915
 916 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 917
 918         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 919         (aarch64_feature_crc): New static.
 920         (CRC): New macro.
 921         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 922         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 923         * aarch64-asm-2.c: Re-generate.
 924         * aarch64-dis-2.c: Ditto.
 925         * aarch64-opc-2.c: Ditto.
 926
 927 2013-02-27  Alan Modra  <amodra@gmail.com>
 928
 929         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 930         * rl78-decode.c: Regenerate.
 931
 932 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 933
 934         * rl78-decode.opc: Fix encoding of DIVWU insn.
 935         * rl78-decode.c: Regenerate.
 936
 937 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 938
 939         PR gas/15159
 940         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 941
 942         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 943         (cpu_flags): Add CpuSMAP.
 944
 945         * i386-opc.h (CpuSMAP): New.
 946         (i386_cpu_flags): Add cpusmap.
 947
 948         * i386-opc.tbl: Add clac and stac.
 949
 950         * i386-init.h: Regenerated.
 951         * i386-tbl.h: Likewise.
 952
 953 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 954
 955         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 956         which also makes the disassembler output be in little
 957         endian like it should be.
 958
 959 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 960
 961         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 962         fields to NULL.
 963         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 964
 965 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 966
 967         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 968         section disassembled.
 969
 970 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 971
 972         * arm-dis.c: Update strht pattern.
 973
 974 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 975
 976         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 977         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 978         trunc.w.s macro for EE.
 979
 980 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 981             Andrew Jenner <andrew@codesourcery.com>
 982
 983         Based on patches from Altera Corporation.
 984
 985         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 986         nios2-opc.c.
 987         * Makefile.in: Regenerated.
 988         * configure.in: Add case for bfd_nios2_arch.
 989         * configure: Regenerated.
 990         * disassemble.c (ARCH_nios2): Define.
 991         (disassembler): Add case for bfd_arch_nios2.
 992         * nios2-dis.c: New file.
 993         * nios2-opc.c: New file.
 994
 995 2013-02-04  Alan Modra  <amodra@gmail.com>
 996
 997         * po/POTFILES.in: Regenerate.
 998         * rl78-decode.c: Regenerate.
 999         * rx-decode.c: Regenerate.
1000
1001 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1002
1003         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1004         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1005         * aarch64-asm.c (convert_xtl_to_shll): New function.
1006         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1007         calling convert_xtl_to_shll.
1008         * aarch64-dis.c (convert_shll_to_xtl): New function.
1009         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1010         calling convert_shll_to_xtl.
1011         * aarch64-gen.c: Update copyright year.
1012         * aarch64-asm-2.c: Re-generate.
1013         * aarch64-dis-2.c: Re-generate.
1014         * aarch64-opc-2.c: Re-generate.
1015
1016 2013-01-24  Nick Clifton  <nickc@redhat.com>
1017
1018         * v850-dis.c: Add support for e3v5 architecture.
1019         * v850-opc.c: Likewise.
1020
1021 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1022
1023         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1024         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1025         * aarch64-opc.c (operand_general_constraint_met_p): For
1026         AARCH64_MOD_LSL, move the range check on the shift amount before the
1027         alignment check; change to call set_sft_amount_out_of_range_error
1028         instead of set_imm_out_of_range_error.
1029         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1030         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1031         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1032         SIMD_IMM_SFT.
1033
1034 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1035
1036         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1037
1038         * i386-init.h: Regenerated.
1039         * i386-tbl.h: Likewise.
1040
1041 2013-01-15  Nick Clifton  <nickc@redhat.com>
1042
1043         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1044         values.
1045         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1046
1047 2013-01-14  Will Newton <will.newton@imgtec.com>
1048
1049         * metag-dis.c (REG_WIDTH): Increase to 64.
1050
1051 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1052
1053         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1054         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1055         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1056         (SH6): Update.
1057         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1058         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1059         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1060         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1061
1062 2013-01-10  Will Newton <will.newton@imgtec.com>
1063
1064         * Makefile.am: Add Meta.
1065         * configure.in: Add Meta.
1066         * disassemble.c: Add Meta support.
1067         * metag-dis.c: New file.
1068         * Makefile.in: Regenerate.
1069         * configure: Regenerate.
1070
1071 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1072
1073         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1074         (match_opcode): Rename to cr16_match_opcode.
1075
1076 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1077
1078         * mips-dis.c: Add names for CP0 registers of r5900.
1079         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1080         instructions sq and lq.
1081         Add support for MIPS r5900 CPU.
1082         Add support for 128 bit MMI (Multimedia Instructions).
1083         Add support for EE instructions (Emotion Engine).
1084         Disable unsupported floating point instructions (64 bit and
1085         undefined compare operations).
1086         Enable instructions of MIPS ISA IV which are supported by r5900.
1087         Disable 64 bit co processor instructions.
1088         Disable 64 bit multiplication and division instructions.
1089         Disable instructions for co-processor 2 and 3, because these are
1090         not supported (preparation for later VU0 support (Vector Unit)).
1091         Disable cvt.w.s because this behaves like trunc.w.s and the
1092         correct execution can't be ensured on r5900.
1093         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1094         will confuse less developers and compilers.
1095
1096 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1097
1098         * aarch64-opc.c (aarch64_print_operand): Change to print
1099         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1100         in comment.
1101         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1102         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1103         OP_MOV_IMM_WIDE.
1104
1105 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1106
1107         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1108         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1109
1110 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1111
1112         * i386-gen.c (process_copyright): Update copyright year to 2013.
1113
1114 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1115
1116         * cr16-dis.c (match_opcode,make_instruction): Remove static
1117         declaration.
1118         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1119         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1120
1121 For older changes see ChangeLog-2012
1122 \f
1123 Copyright (C) 2013 Free Software Foundation, Inc.
1124
1125 Copying and distribution of this file, with or without modification,
1126 are permitted in any medium without royalty provided the copyright
1127 notice and this notice are preserved.
1128
1129 Local Variables:
1130 mode: change-log
1131 left-margin: 8
1132 fill-column: 74
1133 version-control: never
1134 End: