1 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-dis.c: Add comments for '@'.
5 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
6 (enum x86_64_isa): New.
8 (print_i386_disassembler_options): Add amd64 and intel64.
9 (print_insn): Handle amd64 and intel64.
11 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
12 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
13 * i386-opc.h (AMD64): New.
14 (CpuIntel64): Likewise.
15 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
16 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
17 Mark direct call/jmp without Disp16|Disp32 as Intel64.
18 * i386-init.h: Regenerated.
19 * i386-tbl.h: Likewise.
21 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
23 * ppc-opc.c (IH) New define.
24 (powerpc_opcodes) <wait>: Do not enable for POWER7.
25 <tlbie>: Add RS operand for POWER7.
26 <slbia>: Add IH operand for POWER6.
28 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
30 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
33 * i386-tbl.h: Regenerated.
35 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
37 * configure.ac: Support bfd_iamcu_arch.
38 * disassemble.c (disassembler): Support bfd_iamcu_arch.
39 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
40 CPU_IAMCU_COMPAT_FLAGS.
41 (cpu_flags): Add CpuIAMCU.
42 * i386-opc.h (CpuIAMCU): New.
43 (i386_cpu_flags): Add cpuiamcu.
44 * configure: Regenerated.
45 * i386-init.h: Likewise.
46 * i386-tbl.h: Likewise.
48 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
51 * i386-dis.c (X86_64_E8): New.
52 (X86_64_E9): Likewise.
53 Update comments on 'T', 'U', 'V'. Add comments for '^'.
54 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
55 (x86_64_table): Add X86_64_E8 and X86_64_E9.
56 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
58 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
61 2015-04-30 DJ Delorie <dj@redhat.com>
63 * disassemble.c (disassembler): Choose suitable disassembler based
65 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
66 it to decode mul/div insns.
67 * rl78-decode.c: Regenerate.
68 * rl78-dis.c (print_insn_rl78): Rename to...
69 (print_insn_rl78_common): ...this, take ISA parameter.
70 (print_insn_rl78): New.
71 (print_insn_rl78_g10): New.
72 (print_insn_rl78_g13): New.
73 (print_insn_rl78_g14): New.
74 (rl78_get_disassembler): New.
76 2015-04-29 Nick Clifton <nickc@redhat.com>
78 * po/fr.po: Updated French translation.
80 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
82 * ppc-opc.c (DCBT_EO): New define.
83 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
87 <waitrsv>: Do not enable for POWER7 and later.
89 <dcbt>: Default to the two operand form of the instruction for all
90 "old" cpus. For "new" cpus, use the operand ordering that matches
91 whether the cpu is server or embedded.
94 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
96 * s390-opc.c: New instruction type VV0UU2.
97 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
100 2015-04-23 Jan Beulich <jbeulich@suse.com>
102 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
103 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
104 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
105 (vfpclasspd, vfpclassps): Add %XZ.
107 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
109 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
110 (PREFIX_UD_REPZ): Likewise.
111 (PREFIX_UD_REPNZ): Likewise.
112 (PREFIX_UD_DATA): Likewise.
113 (PREFIX_UD_ADDR): Likewise.
114 (PREFIX_UD_LOCK): Likewise.
116 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
118 * i386-dis.c (prefix_requirement): Removed.
119 (print_insn): Don't set prefix_requirement. Check
120 dp->prefix_requirement instead of prefix_requirement.
122 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
125 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
126 (PREFIX_MOD_0_0FC7_REG_6): This.
127 (PREFIX_MOD_3_0FC7_REG_6): New.
128 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
129 (prefix_table): Replace PREFIX_0FC7_REG_6 with
130 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
131 PREFIX_MOD_3_0FC7_REG_7.
132 (mod_table): Replace PREFIX_0FC7_REG_6 with
133 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
134 PREFIX_MOD_3_0FC7_REG_7.
136 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
138 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
139 (PREFIX_MANDATORY_REPNZ): Likewise.
140 (PREFIX_MANDATORY_DATA): Likewise.
141 (PREFIX_MANDATORY_ADDR): Likewise.
142 (PREFIX_MANDATORY_LOCK): Likewise.
143 (PREFIX_MANDATORY): Likewise.
144 (PREFIX_UD_SHIFT): Set to 8
145 (PREFIX_UD_REPZ): Updated.
146 (PREFIX_UD_REPNZ): Likewise.
147 (PREFIX_UD_DATA): Likewise.
148 (PREFIX_UD_ADDR): Likewise.
149 (PREFIX_UD_LOCK): Likewise.
150 (PREFIX_IGNORED_SHIFT): New.
151 (PREFIX_IGNORED_REPZ): Likewise.
152 (PREFIX_IGNORED_REPNZ): Likewise.
153 (PREFIX_IGNORED_DATA): Likewise.
154 (PREFIX_IGNORED_ADDR): Likewise.
155 (PREFIX_IGNORED_LOCK): Likewise.
156 (PREFIX_OPCODE): Likewise.
157 (PREFIX_IGNORED): Likewise.
158 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
159 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
160 (three_byte_table): Likewise.
161 (mod_table): Likewise.
162 (mandatory_prefix): Renamed to ...
163 (prefix_requirement): This.
164 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
165 Update PREFIX_90 entry.
166 (get_valid_dis386): Check prefix_requirement to see if a prefix
168 (print_insn): Replace mandatory_prefix with prefix_requirement.
170 2015-04-15 Renlin Li <renlin.li@arm.com>
172 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
173 use it for ssat and ssat16.
174 (print_insn_thumb32): Add handle case for 'D' control code.
176 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
177 H.J. Lu <hongjiu.lu@intel.com>
179 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
180 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
181 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
182 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
183 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
184 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
185 Fill prefix_requirement field.
186 (struct dis386): Add prefix_requirement field.
187 (dis386): Fill prefix_requirement field.
188 (dis386_twobyte): Ditto.
189 (twobyte_has_mandatory_prefix_: Remove.
190 (reg_table): Fill prefix_requirement field.
191 (prefix_table): Ditto.
192 (x86_64_table): Ditto.
193 (three_byte_table): Ditto.
196 (vex_len_table): Ditto.
197 (vex_w_table): Ditto.
200 (print_insn): Use prefix_requirement.
201 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
202 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
205 2015-03-30 Mike Frysinger <vapier@gentoo.org>
207 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
209 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
211 * Makefile.in: Regenerated.
213 2015-03-25 Anton Blanchard <anton@samba.org>
215 * ppc-dis.c (disassemble_init_powerpc): Only initialise
216 powerpc_opcd_indices and vle_opcd_indices once.
218 2015-03-25 Anton Blanchard <anton@samba.org>
220 * ppc-opc.c (powerpc_opcodes): Add slbfee.
222 2015-03-24 Terry Guo <terry.guo@arm.com>
224 * arm-dis.c (opcode32): Updated to use new arm feature struct.
225 (opcode16): Likewise.
226 (coprocessor_opcodes): Replace bit with feature struct.
227 (neon_opcodes): Likewise.
228 (arm_opcodes): Likewise.
229 (thumb_opcodes): Likewise.
230 (thumb32_opcodes): Likewise.
231 (print_insn_coprocessor): Likewise.
232 (print_insn_arm): Likewise.
233 (select_arm_features): Follow new feature struct.
235 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
237 * i386-dis.c (rm_table): Add clzero.
238 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
239 Add CPU_CLZERO_FLAGS.
240 (cpu_flags): Add CpuCLZERO.
241 * i386-opc.h: Add CpuCLZERO.
242 * i386-opc.tbl: Add clzero.
243 * i386-init.h: Re-generated.
244 * i386-tbl.h: Re-generated.
246 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
248 * mips-opc.c (decode_mips_operand): Fix constraint issues
249 with u and y operands.
251 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
253 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
255 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
257 * s390-opc.c: Add new IBM z13 instructions.
258 * s390-opc.txt: Likewise.
260 2015-03-10 Renlin Li <renlin.li@arm.com>
262 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
263 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
265 * aarch64-asm-2.c: Regenerate.
266 * aarch64-dis-2.c: Likewise.
267 * aarch64-opc-2.c: Likewise.
269 2015-03-03 Jiong Wang <jiong.wang@arm.com>
271 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
273 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
275 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
277 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
278 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
280 2015-02-23 Vinay <Vinay.G@kpit.com>
282 * rl78-decode.opc (MOV): Added space between two operands for
283 'mov' instruction in index addressing mode.
284 * rl78-decode.c: Regenerate.
286 2015-02-19 Pedro Alves <palves@redhat.com>
288 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
290 2015-02-10 Pedro Alves <palves@redhat.com>
291 Tom Tromey <tromey@redhat.com>
293 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
294 microblaze_and, microblaze_xor.
295 * microblaze-opc.h (opcodes): Adjust.
297 2015-01-28 James Bowman <james.bowman@ftdichip.com>
299 * Makefile.am: Add FT32 files.
300 * configure.ac: Handle FT32.
301 * disassemble.c (disassembler): Call print_insn_ft32.
302 * ft32-dis.c: New file.
303 * ft32-opc.c: New file.
304 * Makefile.in: Regenerate.
305 * configure: Regenerate.
306 * po/POTFILES.in: Regenerate.
308 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
310 * nds32-asm.c (keyword_sr): Add new system registers.
312 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
314 * s390-dis.c (s390_extract_operand): Support vector register
316 (s390_print_insn_with_opcode): Support new operands types and add
317 new handling of optional operands.
318 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
319 and include opcode/s390.h instead.
320 (struct op_struct): New field `flags'.
321 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
322 (dumpTable): Dump flags.
323 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
325 * s390-opc.c: Add new operands types, instruction formats, and
327 (s390_opformats): Add new formats for .insn.
328 * s390-opc.txt: Add new instructions.
330 2015-01-01 Alan Modra <amodra@gmail.com>
332 Update year range in copyright notice of all files.
334 For older changes see ChangeLog-2014
336 Copyright (C) 2015 Free Software Foundation, Inc.
338 Copying and distribution of this file, with or without modification,
339 are permitted in any medium without royalty provided the copyright
340 notice and this notice are preserved.
346 version-control: never