1 2018-11-21 John Darrington <john@darrington.wattle.id.au>
3 * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
4 if the postbyte matches the appropriate pattern.
6 2018-11-13 Francois H. Theron <francois.theron@netronome.com>
8 * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
10 2018-11-12 Sudakshina Das <sudi.das@arm.com>
12 * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
13 IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
14 IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
16 (aarch64_sys_ins_reg_supported_p): New check for above.
18 2018-11-12 Sudakshina Das <sudi.das@arm.com>
20 * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
21 TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
23 (aarch64_sys_reg_supported_p): New check for above.
24 (aarch64_pstatefields): New entry for TCO.
25 (aarch64_pstatefield_supported_p): New check for above.
27 2018-11-12 Sudakshina Das <sudi.das@arm.com>
29 * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
30 * aarch64-asm.h (ins_addr_simple_2): Declare the above.
31 * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
32 * aarch64-dis.h (ext_addr_simple_2): Declare the above.
33 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
34 AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
35 (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
36 * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
37 (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
38 * aarch64-asm-2.c: Regenerated.
39 * aarch64-dis-2.c: Regenerated.
40 * aarch64-opc-2.c: Regenerated.
42 2018-11-12 Sudakshina Das <sudi.das@arm.com>
44 * aarch64-tbl.h (QL_LDG): New.
45 (aarch64_opcode_table): Add ldg.
46 * aarch64-asm-2.c: Regenerated.
47 * aarch64-dis-2.c: Regenerated.
48 * aarch64-opc-2.c: Regenerated.
50 2018-11-12 Sudakshina Das <sudi.das@arm.com>
52 * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
53 for AARCH64_OPND_QLF_imm_tag.
54 (operand_general_constraint_met_p): Add case for
55 AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
56 (aarch64_print_operand): Likewise.
57 * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
58 (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
59 for both offset and pre/post indexed versions.
60 (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
61 * aarch64-asm-2.c: Regenerated.
62 * aarch64-dis-2.c: Regenerated.
63 * aarch64-opc-2.c: Regenerated.
65 2018-11-12 Sudakshina Das <sudi.das@arm.com>
67 * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
68 * aarch64-asm-2.c: Regenerated.
69 * aarch64-dis-2.c: Regenerated.
70 * aarch64-opc-2.c: Regenerated.
72 2018-11-12 Sudakshina Das <sudi.das@arm.com>
74 * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
75 (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
76 * aarch64-opc.c (fields): Add entry for imm4_3.
77 (operand_general_constraint_met_p): Add cases for
78 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
79 (aarch64_print_operand): Likewise.
80 * aarch64-tbl.h (QL_ADDG): New.
81 (aarch64_opcode_table): Add addg, subg, irg and gmi.
82 (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
83 * aarch64-asm.c (aarch64_ins_imm): Add case for
84 operand_need_shift_by_four.
85 * aarch64-asm-2.c: Regenerated.
86 * aarch64-dis-2.c: Regenerated.
87 * aarch64-opc-2.c: Regenerated.
89 2018-11-12 Sudakshina Das <sudi.das@arm.com>
91 * aarch64-tbl.h (aarch64_feature_memtag): New.
92 (MEMTAG, MEMTAG_INSN): New.
94 2018-11-06 Sudakshina Das <sudi.das@arm.com>
96 * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
97 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
99 2018-11-06 Alan Modra <amodra@gmail.com>
101 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
102 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
103 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
104 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
105 Don't return zero on error, insert mask bits instead.
106 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
107 (insert_sh6, extract_sh6): Delete dead code.
108 (insert_sprbat, insert_sprg): Use unsigned comparisions.
109 (powerpc_operands <OIMM>): Set shift count rather than using
111 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
113 2018-11-06 Jan Beulich <jbeulich@suse.com>
115 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
116 vpbroadcast{d,q} with GPR operand.
118 2018-11-06 Jan Beulich <jbeulich@suse.com>
120 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
121 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
122 cases up one level in the hierarchy.
124 2018-11-06 Jan Beulich <jbeulich@suse.com>
126 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
127 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
128 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
129 into MOD_VEX_0F93_P_3_LEN_0.
130 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
131 operand cases up one level in the hierarchy.
133 2018-11-06 Jan Beulich <jbeulich@suse.com>
135 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
136 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
137 EVEX_W_0F3A22_P_2): Delete.
138 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
139 entries up one level in the hierarchy.
140 (OP_E_memory): Handle dq_mode when determining Disp8 shift
142 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
143 entries up one level in the hierarchy.
144 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
145 VexWIG for AVX flavors.
146 * i386-tbl.h: Re-generate.
148 2018-11-06 Jan Beulich <jbeulich@suse.com>
150 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
151 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
152 vcvtusi2ss, kmovd): Drop VexW=1.
153 * i386-tbl.h: Re-generate.
155 2018-11-06 Jan Beulich <jbeulich@suse.com>
157 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
158 EVex512, EVexLIG, EVexDYN): New.
159 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
160 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
161 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
162 of EVex=4 (aka EVexLIG).
163 * i386-tbl.h: Re-generate.
165 2018-11-06 Jan Beulich <jbeulich@suse.com>
167 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
168 (vpmaxub): Re-order attributes on AVX512BW flavor.
169 * i386-tbl.h: Re-generate.
171 2018-11-06 Jan Beulich <jbeulich@suse.com>
173 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
174 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
175 Vex=1 on AVX / AVX2 flavors.
176 (vpmaxub): Re-order attributes on AVX512BW flavor.
177 * i386-tbl.h: Re-generate.
179 2018-11-06 Jan Beulich <jbeulich@suse.com>
181 * i386-opc.tbl (VexW0, VexW1): New.
182 (vphadd*, vphsub*): Use VexW0 on XOP variants.
183 * i386-tbl.h: Re-generate.
185 2018-10-22 John Darrington <john@darrington.wattle.id.au>
187 * s12z-dis.c (decode_possible_symbol): Add fallback case.
188 (rel_15_7): Likewise.
190 2018-10-19 Tamar Christina <tamar.christina@arm.com>
192 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
193 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
194 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
196 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
198 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
199 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
201 2018-10-10 Jan Beulich <jbeulich@suse.com>
203 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
205 * i386-opc.h (Size16, Size32, Size64): Delete.
207 (SIZE16, SIZE32, SIZE64): Define.
208 (struct i386_opcode_modifier): Drop size16, size32, and size64.
210 * i386-opc.tbl (Size16, Size32, Size64): Define.
211 * i386-tbl.h: Re-generate.
213 2018-10-09 Sudakshina Das <sudi.das@arm.com>
215 * aarch64-opc.c (operand_general_constraint_met_p): Add
216 SSBS in the check for one-bit immediate.
217 (aarch64_sys_regs): New entry for SSBS.
218 (aarch64_sys_reg_supported_p): New check for above.
219 (aarch64_pstatefields): New entry for SSBS.
220 (aarch64_pstatefield_supported_p): New check for above.
222 2018-10-09 Sudakshina Das <sudi.das@arm.com>
224 * aarch64-opc.c (aarch64_sys_regs): New entries for
225 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
226 (aarch64_sys_reg_supported_p): New checks for above.
228 2018-10-09 Sudakshina Das <sudi.das@arm.com>
230 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
231 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
232 with the hint immediate.
233 * aarch64-opc.c (aarch64_hint_options): New entries for
234 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
235 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
236 while checking for HINT_OPD_F_NOPRINT flag.
237 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
239 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
240 (aarch64_opcode_table): Add entry for BTI.
241 (AARCH64_OPERANDS): Add new description for BTI targets.
242 * aarch64-asm-2.c: Regenerate.
243 * aarch64-dis-2.c: Regenerate.
244 * aarch64-opc-2.c: Regenerate.
246 2018-10-09 Sudakshina Das <sudi.das@arm.com>
248 * aarch64-opc.c (aarch64_sys_regs): New entries for
250 (aarch64_sys_reg_supported_p): New check for above.
252 2018-10-09 Sudakshina Das <sudi.das@arm.com>
254 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
255 (aarch64_sys_ins_reg_supported_p): New check for above.
257 2018-10-09 Sudakshina Das <sudi.das@arm.com>
259 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
260 AARCH64_OPND_SYSREG_SR.
261 * aarch64-opc.c (aarch64_print_operand): Likewise.
262 (aarch64_sys_regs_sr): Define table.
263 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
264 AARCH64_FEATURE_PREDRES.
265 * aarch64-tbl.h (aarch64_feature_predres): New.
266 (PREDRES, PREDRES_INSN): New.
267 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
268 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
269 * aarch64-asm-2.c: Regenerate.
270 * aarch64-dis-2.c: Regenerate.
271 * aarch64-opc-2.c: Regenerate.
273 2018-10-09 Sudakshina Das <sudi.das@arm.com>
275 * aarch64-tbl.h (aarch64_feature_sb): New.
277 (aarch64_opcode_table): Add entry for sb.
278 * aarch64-asm-2.c: Regenerate.
279 * aarch64-dis-2.c: Regenerate.
280 * aarch64-opc-2.c: Regenerate.
282 2018-10-09 Sudakshina Das <sudi.das@arm.com>
284 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
285 (aarch64_feature_frintts): New.
286 (FLAGMANIP, FRINTTS): New.
287 (aarch64_opcode_table): Add entries for xaflag, axflag
288 and frint[32,64][x,z] instructions.
289 * aarch64-asm-2.c: Regenerate.
290 * aarch64-dis-2.c: Regenerate.
291 * aarch64-opc-2.c: Regenerate.
293 2018-10-09 Sudakshina Das <sudi.das@arm.com>
295 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
296 (ARMV8_5, V8_5_INSN): New.
298 2018-10-08 Tamar Christina <tamar.christina@arm.com>
300 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
302 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
304 * i386-dis.c (rm_table): Add enclv.
305 * i386-opc.tbl: Add enclv.
306 * i386-tbl.h: Regenerated.
308 2018-10-05 Sudakshina Das <sudi.das@arm.com>
310 * arm-dis.c (arm_opcodes): Add sb.
311 (thumb32_opcodes): Likewise.
313 2018-10-05 Richard Henderson <rth@twiddle.net>
314 Stafford Horne <shorne@gmail.com>
316 * or1k-desc.c: Regenerate.
317 * or1k-desc.h: Regenerate.
318 * or1k-opc.c: Regenerate.
319 * or1k-opc.h: Regenerate.
320 * or1k-opinst.c: Regenerate.
322 2018-10-05 Richard Henderson <rth@twiddle.net>
324 * or1k-asm.c: Regenerated.
325 * or1k-desc.c: Regenerated.
326 * or1k-desc.h: Regenerated.
327 * or1k-dis.c: Regenerated.
328 * or1k-ibld.c: Regenerated.
329 * or1k-opc.c: Regenerated.
330 * or1k-opc.h: Regenerated.
331 * or1k-opinst.c: Regenerated.
333 2018-10-05 Richard Henderson <rth@twiddle.net>
335 * or1k-asm.c: Regenerate.
337 2018-10-03 Tamar Christina <tamar.christina@arm.com>
339 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
340 * aarch64-dis.c (print_operands): Refactor to take notes.
341 (print_verifier_notes): New.
342 (print_aarch64_insn): Apply constraint verifier.
343 (print_insn_aarch64_word): Update call to print_aarch64_insn.
344 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
346 2018-10-03 Tamar Christina <tamar.christina@arm.com>
348 * aarch64-opc.c (init_insn_block): New.
349 (verify_constraints, aarch64_is_destructive_by_operands): New.
350 * aarch64-opc.h (verify_constraints): New.
352 2018-10-03 Tamar Christina <tamar.christina@arm.com>
354 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
355 * aarch64-opc.c (verify_ldpsw): Update arguments.
357 2018-10-03 Tamar Christina <tamar.christina@arm.com>
359 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
360 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
362 2018-10-03 Tamar Christina <tamar.christina@arm.com>
364 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
365 * aarch64-dis.c (insn_sequence): New.
367 2018-10-03 Tamar Christina <tamar.christina@arm.com>
369 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
370 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
371 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
372 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
375 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
377 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
379 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
380 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
381 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
382 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
383 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
384 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
385 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
387 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
389 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
391 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
393 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
394 are used when extracting signed fields and converting them to
395 potentially 64-bit types.
397 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
399 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
400 * Makefile.in: Re-generate.
401 * aclocal.m4: Re-generate.
402 * configure: Re-generate.
403 * configure.ac: Remove check for -Wno-missing-field-initializers.
404 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
405 (csky_v2_opcodes): Likewise.
407 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
409 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
411 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
413 * nds32-asm.c (operand_fields): Remove the unused fields.
414 (nds32_opcodes): Remove the unused instructions.
415 * nds32-dis.c (nds32_ex9_info): Removed.
416 (nds32_parse_opcode): Updated.
417 (print_insn_nds32): Likewise.
418 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
419 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
420 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
421 build_opcode_hash_table): New functions.
422 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
423 nds32_opcode_table): New.
424 (hw_ktabs): Declare it to a pointer rather than an array.
425 (build_hash_table): Removed.
426 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
427 SYN_ROPT and upadte HW_GPR and HW_INT.
428 * nds32-dis.c (keywords): Remove const.
429 (match_field): New function.
430 (nds32_parse_opcode): Updated.
431 * disassemble.c (disassemble_init_for_target):
432 Add disassemble_init_nds32.
433 * nds32-dis.c (eum map_type): New.
434 (nds32_private_data): Likewise.
435 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
436 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
437 (print_insn_nds32): Updated.
438 * nds32-asm.c (parse_aext_reg): Add new parameter.
439 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
442 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
443 (operand_fields): Add new fields.
444 (nds32_opcodes): Add new instructions.
445 (keyword_aridxi_mx): New keyword.
446 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
448 (ALU2_1, ALU2_2, ALU2_3): New macros.
449 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
451 2018-09-17 Kito Cheng <kito@andestech.com>
453 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
455 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
458 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
459 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
460 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
461 (EVEX_LEN_0F7E_P_1): Likewise.
462 (EVEX_LEN_0F7E_P_2): Likewise.
463 (EVEX_LEN_0FD6_P_2): Likewise.
464 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
465 (EVEX_LEN_TABLE): Likewise.
466 (EVEX_LEN_0F6E_P_2): New enum.
467 (EVEX_LEN_0F7E_P_1): Likewise.
468 (EVEX_LEN_0F7E_P_2): Likewise.
469 (EVEX_LEN_0FD6_P_2): Likewise.
470 (evex_len_table): New.
471 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
472 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
473 * i386-tbl.h: Regenerated.
475 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
478 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
479 VEX_LEN_0F7E_P_2 entries.
480 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
481 * i386-tbl.h: Regenerated.
483 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
485 * i386-dis.c (VZERO_Fixup): Removed.
487 (VEX_LEN_0F10_P_1): Likewise.
488 (VEX_LEN_0F10_P_3): Likewise.
489 (VEX_LEN_0F11_P_1): Likewise.
490 (VEX_LEN_0F11_P_3): Likewise.
491 (VEX_LEN_0F2E_P_0): Likewise.
492 (VEX_LEN_0F2E_P_2): Likewise.
493 (VEX_LEN_0F2F_P_0): Likewise.
494 (VEX_LEN_0F2F_P_2): Likewise.
495 (VEX_LEN_0F51_P_1): Likewise.
496 (VEX_LEN_0F51_P_3): Likewise.
497 (VEX_LEN_0F52_P_1): Likewise.
498 (VEX_LEN_0F53_P_1): Likewise.
499 (VEX_LEN_0F58_P_1): Likewise.
500 (VEX_LEN_0F58_P_3): Likewise.
501 (VEX_LEN_0F59_P_1): Likewise.
502 (VEX_LEN_0F59_P_3): Likewise.
503 (VEX_LEN_0F5A_P_1): Likewise.
504 (VEX_LEN_0F5A_P_3): Likewise.
505 (VEX_LEN_0F5C_P_1): Likewise.
506 (VEX_LEN_0F5C_P_3): Likewise.
507 (VEX_LEN_0F5D_P_1): Likewise.
508 (VEX_LEN_0F5D_P_3): Likewise.
509 (VEX_LEN_0F5E_P_1): Likewise.
510 (VEX_LEN_0F5E_P_3): Likewise.
511 (VEX_LEN_0F5F_P_1): Likewise.
512 (VEX_LEN_0F5F_P_3): Likewise.
513 (VEX_LEN_0FC2_P_1): Likewise.
514 (VEX_LEN_0FC2_P_3): Likewise.
515 (VEX_LEN_0F3A0A_P_2): Likewise.
516 (VEX_LEN_0F3A0B_P_2): Likewise.
517 (VEX_W_0F10_P_0): Likewise.
518 (VEX_W_0F10_P_1): Likewise.
519 (VEX_W_0F10_P_2): Likewise.
520 (VEX_W_0F10_P_3): Likewise.
521 (VEX_W_0F11_P_0): Likewise.
522 (VEX_W_0F11_P_1): Likewise.
523 (VEX_W_0F11_P_2): Likewise.
524 (VEX_W_0F11_P_3): Likewise.
525 (VEX_W_0F12_P_0_M_0): Likewise.
526 (VEX_W_0F12_P_0_M_1): Likewise.
527 (VEX_W_0F12_P_1): Likewise.
528 (VEX_W_0F12_P_2): Likewise.
529 (VEX_W_0F12_P_3): Likewise.
530 (VEX_W_0F13_M_0): Likewise.
531 (VEX_W_0F14): Likewise.
532 (VEX_W_0F15): Likewise.
533 (VEX_W_0F16_P_0_M_0): Likewise.
534 (VEX_W_0F16_P_0_M_1): Likewise.
535 (VEX_W_0F16_P_1): Likewise.
536 (VEX_W_0F16_P_2): Likewise.
537 (VEX_W_0F17_M_0): Likewise.
538 (VEX_W_0F28): Likewise.
539 (VEX_W_0F29): Likewise.
540 (VEX_W_0F2B_M_0): Likewise.
541 (VEX_W_0F2E_P_0): Likewise.
542 (VEX_W_0F2E_P_2): Likewise.
543 (VEX_W_0F2F_P_0): Likewise.
544 (VEX_W_0F2F_P_2): Likewise.
545 (VEX_W_0F50_M_0): Likewise.
546 (VEX_W_0F51_P_0): Likewise.
547 (VEX_W_0F51_P_1): Likewise.
548 (VEX_W_0F51_P_2): Likewise.
549 (VEX_W_0F51_P_3): Likewise.
550 (VEX_W_0F52_P_0): Likewise.
551 (VEX_W_0F52_P_1): Likewise.
552 (VEX_W_0F53_P_0): Likewise.
553 (VEX_W_0F53_P_1): Likewise.
554 (VEX_W_0F58_P_0): Likewise.
555 (VEX_W_0F58_P_1): Likewise.
556 (VEX_W_0F58_P_2): Likewise.
557 (VEX_W_0F58_P_3): Likewise.
558 (VEX_W_0F59_P_0): Likewise.
559 (VEX_W_0F59_P_1): Likewise.
560 (VEX_W_0F59_P_2): Likewise.
561 (VEX_W_0F59_P_3): Likewise.
562 (VEX_W_0F5A_P_0): Likewise.
563 (VEX_W_0F5A_P_1): Likewise.
564 (VEX_W_0F5A_P_3): Likewise.
565 (VEX_W_0F5B_P_0): Likewise.
566 (VEX_W_0F5B_P_1): Likewise.
567 (VEX_W_0F5B_P_2): Likewise.
568 (VEX_W_0F5C_P_0): Likewise.
569 (VEX_W_0F5C_P_1): Likewise.
570 (VEX_W_0F5C_P_2): Likewise.
571 (VEX_W_0F5C_P_3): Likewise.
572 (VEX_W_0F5D_P_0): Likewise.
573 (VEX_W_0F5D_P_1): Likewise.
574 (VEX_W_0F5D_P_2): Likewise.
575 (VEX_W_0F5D_P_3): Likewise.
576 (VEX_W_0F5E_P_0): Likewise.
577 (VEX_W_0F5E_P_1): Likewise.
578 (VEX_W_0F5E_P_2): Likewise.
579 (VEX_W_0F5E_P_3): Likewise.
580 (VEX_W_0F5F_P_0): Likewise.
581 (VEX_W_0F5F_P_1): Likewise.
582 (VEX_W_0F5F_P_2): Likewise.
583 (VEX_W_0F5F_P_3): Likewise.
584 (VEX_W_0F60_P_2): Likewise.
585 (VEX_W_0F61_P_2): Likewise.
586 (VEX_W_0F62_P_2): Likewise.
587 (VEX_W_0F63_P_2): Likewise.
588 (VEX_W_0F64_P_2): Likewise.
589 (VEX_W_0F65_P_2): Likewise.
590 (VEX_W_0F66_P_2): Likewise.
591 (VEX_W_0F67_P_2): Likewise.
592 (VEX_W_0F68_P_2): Likewise.
593 (VEX_W_0F69_P_2): Likewise.
594 (VEX_W_0F6A_P_2): Likewise.
595 (VEX_W_0F6B_P_2): Likewise.
596 (VEX_W_0F6C_P_2): Likewise.
597 (VEX_W_0F6D_P_2): Likewise.
598 (VEX_W_0F6F_P_1): Likewise.
599 (VEX_W_0F6F_P_2): Likewise.
600 (VEX_W_0F70_P_1): Likewise.
601 (VEX_W_0F70_P_2): Likewise.
602 (VEX_W_0F70_P_3): Likewise.
603 (VEX_W_0F71_R_2_P_2): Likewise.
604 (VEX_W_0F71_R_4_P_2): Likewise.
605 (VEX_W_0F71_R_6_P_2): Likewise.
606 (VEX_W_0F72_R_2_P_2): Likewise.
607 (VEX_W_0F72_R_4_P_2): Likewise.
608 (VEX_W_0F72_R_6_P_2): Likewise.
609 (VEX_W_0F73_R_2_P_2): Likewise.
610 (VEX_W_0F73_R_3_P_2): Likewise.
611 (VEX_W_0F73_R_6_P_2): Likewise.
612 (VEX_W_0F73_R_7_P_2): Likewise.
613 (VEX_W_0F74_P_2): Likewise.
614 (VEX_W_0F75_P_2): Likewise.
615 (VEX_W_0F76_P_2): Likewise.
616 (VEX_W_0F77_P_0): Likewise.
617 (VEX_W_0F7C_P_2): Likewise.
618 (VEX_W_0F7C_P_3): Likewise.
619 (VEX_W_0F7D_P_2): Likewise.
620 (VEX_W_0F7D_P_3): Likewise.
621 (VEX_W_0F7E_P_1): Likewise.
622 (VEX_W_0F7F_P_1): Likewise.
623 (VEX_W_0F7F_P_2): Likewise.
624 (VEX_W_0FAE_R_2_M_0): Likewise.
625 (VEX_W_0FAE_R_3_M_0): Likewise.
626 (VEX_W_0FC2_P_0): Likewise.
627 (VEX_W_0FC2_P_1): Likewise.
628 (VEX_W_0FC2_P_2): Likewise.
629 (VEX_W_0FC2_P_3): Likewise.
630 (VEX_W_0FD0_P_2): Likewise.
631 (VEX_W_0FD0_P_3): Likewise.
632 (VEX_W_0FD1_P_2): Likewise.
633 (VEX_W_0FD2_P_2): Likewise.
634 (VEX_W_0FD3_P_2): Likewise.
635 (VEX_W_0FD4_P_2): Likewise.
636 (VEX_W_0FD5_P_2): Likewise.
637 (VEX_W_0FD6_P_2): Likewise.
638 (VEX_W_0FD7_P_2_M_1): Likewise.
639 (VEX_W_0FD8_P_2): Likewise.
640 (VEX_W_0FD9_P_2): Likewise.
641 (VEX_W_0FDA_P_2): Likewise.
642 (VEX_W_0FDB_P_2): Likewise.
643 (VEX_W_0FDC_P_2): Likewise.
644 (VEX_W_0FDD_P_2): Likewise.
645 (VEX_W_0FDE_P_2): Likewise.
646 (VEX_W_0FDF_P_2): Likewise.
647 (VEX_W_0FE0_P_2): Likewise.
648 (VEX_W_0FE1_P_2): Likewise.
649 (VEX_W_0FE2_P_2): Likewise.
650 (VEX_W_0FE3_P_2): Likewise.
651 (VEX_W_0FE4_P_2): Likewise.
652 (VEX_W_0FE5_P_2): Likewise.
653 (VEX_W_0FE6_P_1): Likewise.
654 (VEX_W_0FE6_P_2): Likewise.
655 (VEX_W_0FE6_P_3): Likewise.
656 (VEX_W_0FE7_P_2_M_0): Likewise.
657 (VEX_W_0FE8_P_2): Likewise.
658 (VEX_W_0FE9_P_2): Likewise.
659 (VEX_W_0FEA_P_2): Likewise.
660 (VEX_W_0FEB_P_2): Likewise.
661 (VEX_W_0FEC_P_2): Likewise.
662 (VEX_W_0FED_P_2): Likewise.
663 (VEX_W_0FEE_P_2): Likewise.
664 (VEX_W_0FEF_P_2): Likewise.
665 (VEX_W_0FF0_P_3_M_0): Likewise.
666 (VEX_W_0FF1_P_2): Likewise.
667 (VEX_W_0FF2_P_2): Likewise.
668 (VEX_W_0FF3_P_2): Likewise.
669 (VEX_W_0FF4_P_2): Likewise.
670 (VEX_W_0FF5_P_2): Likewise.
671 (VEX_W_0FF6_P_2): Likewise.
672 (VEX_W_0FF7_P_2): Likewise.
673 (VEX_W_0FF8_P_2): Likewise.
674 (VEX_W_0FF9_P_2): Likewise.
675 (VEX_W_0FFA_P_2): Likewise.
676 (VEX_W_0FFB_P_2): Likewise.
677 (VEX_W_0FFC_P_2): Likewise.
678 (VEX_W_0FFD_P_2): Likewise.
679 (VEX_W_0FFE_P_2): Likewise.
680 (VEX_W_0F3800_P_2): Likewise.
681 (VEX_W_0F3801_P_2): Likewise.
682 (VEX_W_0F3802_P_2): Likewise.
683 (VEX_W_0F3803_P_2): Likewise.
684 (VEX_W_0F3804_P_2): Likewise.
685 (VEX_W_0F3805_P_2): Likewise.
686 (VEX_W_0F3806_P_2): Likewise.
687 (VEX_W_0F3807_P_2): Likewise.
688 (VEX_W_0F3808_P_2): Likewise.
689 (VEX_W_0F3809_P_2): Likewise.
690 (VEX_W_0F380A_P_2): Likewise.
691 (VEX_W_0F380B_P_2): Likewise.
692 (VEX_W_0F3817_P_2): Likewise.
693 (VEX_W_0F381C_P_2): Likewise.
694 (VEX_W_0F381D_P_2): Likewise.
695 (VEX_W_0F381E_P_2): Likewise.
696 (VEX_W_0F3820_P_2): Likewise.
697 (VEX_W_0F3821_P_2): Likewise.
698 (VEX_W_0F3822_P_2): Likewise.
699 (VEX_W_0F3823_P_2): Likewise.
700 (VEX_W_0F3824_P_2): Likewise.
701 (VEX_W_0F3825_P_2): Likewise.
702 (VEX_W_0F3828_P_2): Likewise.
703 (VEX_W_0F3829_P_2): Likewise.
704 (VEX_W_0F382A_P_2_M_0): Likewise.
705 (VEX_W_0F382B_P_2): Likewise.
706 (VEX_W_0F3830_P_2): Likewise.
707 (VEX_W_0F3831_P_2): Likewise.
708 (VEX_W_0F3832_P_2): Likewise.
709 (VEX_W_0F3833_P_2): Likewise.
710 (VEX_W_0F3834_P_2): Likewise.
711 (VEX_W_0F3835_P_2): Likewise.
712 (VEX_W_0F3837_P_2): Likewise.
713 (VEX_W_0F3838_P_2): Likewise.
714 (VEX_W_0F3839_P_2): Likewise.
715 (VEX_W_0F383A_P_2): Likewise.
716 (VEX_W_0F383B_P_2): Likewise.
717 (VEX_W_0F383C_P_2): Likewise.
718 (VEX_W_0F383D_P_2): Likewise.
719 (VEX_W_0F383E_P_2): Likewise.
720 (VEX_W_0F383F_P_2): Likewise.
721 (VEX_W_0F3840_P_2): Likewise.
722 (VEX_W_0F3841_P_2): Likewise.
723 (VEX_W_0F38DB_P_2): Likewise.
724 (VEX_W_0F3A08_P_2): Likewise.
725 (VEX_W_0F3A09_P_2): Likewise.
726 (VEX_W_0F3A0A_P_2): Likewise.
727 (VEX_W_0F3A0B_P_2): Likewise.
728 (VEX_W_0F3A0C_P_2): Likewise.
729 (VEX_W_0F3A0D_P_2): Likewise.
730 (VEX_W_0F3A0E_P_2): Likewise.
731 (VEX_W_0F3A0F_P_2): Likewise.
732 (VEX_W_0F3A21_P_2): Likewise.
733 (VEX_W_0F3A40_P_2): Likewise.
734 (VEX_W_0F3A41_P_2): Likewise.
735 (VEX_W_0F3A42_P_2): Likewise.
736 (VEX_W_0F3A62_P_2): Likewise.
737 (VEX_W_0F3A63_P_2): Likewise.
738 (VEX_W_0F3ADF_P_2): Likewise.
739 (VEX_LEN_0F77_P_0): New.
740 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
741 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
742 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
743 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
744 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
745 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
746 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
747 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
748 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
749 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
750 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
751 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
752 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
753 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
754 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
755 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
756 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
757 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
758 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
759 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
760 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
761 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
762 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
763 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
764 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
765 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
766 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
767 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
768 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
769 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
770 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
771 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
772 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
773 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
774 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
775 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
776 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
777 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
778 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
779 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
780 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
781 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
782 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
783 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
784 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
785 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
786 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
787 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
788 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
789 (vex_table): Update VEX 0F28 and 0F29 entries.
790 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
791 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
792 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
793 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
794 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
795 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
796 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
797 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
798 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
799 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
800 VEX_LEN_0F3A0B_P_2 entries.
801 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
802 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
803 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
804 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
805 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
806 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
807 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
808 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
809 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
810 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
811 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
812 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
813 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
814 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
815 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
816 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
817 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
818 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
819 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
820 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
821 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
822 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
823 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
824 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
825 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
826 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
827 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
828 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
829 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
830 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
831 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
832 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
833 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
834 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
835 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
836 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
837 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
838 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
839 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
840 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
841 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
842 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
843 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
844 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
845 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
846 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
847 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
848 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
849 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
850 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
851 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
852 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
853 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
854 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
855 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
856 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
857 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
858 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
859 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
860 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
861 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
862 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
863 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
864 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
865 VEX_W_0F3ADF_P_2 entries.
866 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
867 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
868 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
870 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
872 * i386-opc.tbl (VexWIG): New.
873 Replace VexW=3 with VexWIG.
875 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
877 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
878 * i386-tbl.h: Regenerated.
880 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
883 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
884 VEX_LEN_0FD6_P_2 entries.
885 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
886 * i386-tbl.h: Regenerated.
888 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
891 * i386-opc.h (VEXWIG): New.
892 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
893 * i386-tbl.h: Regenerated.
895 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
898 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
899 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
900 * i386-dis.c (EXxEVexR64): New.
901 (evex_rounding_64_mode): Likewise.
902 (OP_Rounding): Handle evex_rounding_64_mode.
904 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
907 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
908 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
909 * i386-dis.c (Edqa): New.
910 (dqa_mode): Likewise.
911 (intel_operand_size): Handle dqa_mode as m_mode.
912 (OP_E_register): Handle dqa_mode as dq_mode.
913 (OP_E_memory): Set shift for dqa_mode based on address_mode.
915 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
917 * i386-dis.c (OP_E_memory): Reformat.
919 2018-09-14 Jan Beulich <jbeulich@suse.com>
921 * i386-opc.tbl (crc32): Fold byte and word forms.
922 * i386-tbl.h: Re-generate.
924 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
926 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
927 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
928 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
929 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
930 * i386-tbl.h: Regenerated.
932 2018-09-13 Jan Beulich <jbeulich@suse.com>
934 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
936 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
937 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
938 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
939 * i386-tbl.h: Re-generate.
941 2018-09-13 Jan Beulich <jbeulich@suse.com>
943 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
945 * i386-tbl.h: Re-generate.
947 2018-09-13 Jan Beulich <jbeulich@suse.com>
949 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
951 * i386-tbl.h: Re-generate.
953 2018-09-13 Jan Beulich <jbeulich@suse.com>
955 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
957 * i386-tbl.h: Re-generate.
959 2018-09-13 Jan Beulich <jbeulich@suse.com>
961 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
963 * i386-tbl.h: Re-generate.
965 2018-09-13 Jan Beulich <jbeulich@suse.com>
967 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
969 * i386-tbl.h: Re-generate.
971 2018-09-13 Jan Beulich <jbeulich@suse.com>
973 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
975 * i386-tbl.h: Re-generate.
977 2018-09-13 Jan Beulich <jbeulich@suse.com>
979 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
980 * i386-tbl.h: Re-generate.
982 2018-09-13 Jan Beulich <jbeulich@suse.com>
984 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
985 * i386-tbl.h: Re-generate.
987 2018-09-13 Jan Beulich <jbeulich@suse.com>
989 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
991 * i386-tbl.h: Re-generate.
993 2018-09-13 Jan Beulich <jbeulich@suse.com>
995 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
997 * i386-tbl.h: Re-generate.
999 2018-09-13 Jan Beulich <jbeulich@suse.com>
1001 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
1002 * i386-tbl.h: Re-generate.
1004 2018-09-13 Jan Beulich <jbeulich@suse.com>
1006 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
1007 * i386-tbl.h: Re-generate.
1009 2018-09-13 Jan Beulich <jbeulich@suse.com>
1011 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1012 * i386-tbl.h: Re-generate.
1014 2018-09-13 Jan Beulich <jbeulich@suse.com>
1016 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1018 * i386-tbl.h: Re-generate.
1020 2018-09-13 Jan Beulich <jbeulich@suse.com>
1022 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1024 * i386-tbl.h: Re-generate.
1026 2018-09-13 Jan Beulich <jbeulich@suse.com>
1028 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1030 * i386-tbl.h: Re-generate.
1032 2018-09-13 Jan Beulich <jbeulich@suse.com>
1034 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1035 * i386-tbl.h: Re-generate.
1037 2018-09-13 Jan Beulich <jbeulich@suse.com>
1039 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1040 * i386-tbl.h: Re-generate.
1042 2018-09-13 Jan Beulich <jbeulich@suse.com>
1044 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1045 * i386-tbl.h: Re-generate.
1047 2018-09-13 Jan Beulich <jbeulich@suse.com>
1049 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1050 (vpbroadcastw, rdpid): Drop NoRex64.
1051 * i386-tbl.h: Re-generate.
1053 2018-09-13 Jan Beulich <jbeulich@suse.com>
1055 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1056 store templates, adding D.
1057 * i386-tbl.h: Re-generate.
1059 2018-09-13 Jan Beulich <jbeulich@suse.com>
1061 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1062 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1063 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1064 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1065 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1066 Fold load and store templates where possible, adding D. Drop
1067 IgnoreSize where it was pointlessly present. Drop redundant
1069 * i386-tbl.h: Re-generate.
1071 2018-09-13 Jan Beulich <jbeulich@suse.com>
1073 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1074 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1075 (intel_operand_size): Handle v_bndmk_mode.
1076 (OP_E_memory): Likewise. Produce (bad) when also riprel.
1078 2018-09-08 John Darrington <john@darrington.wattle.id.au>
1080 * disassemble.c (ARCH_s12z): Define if ARCH_all.
1082 2018-08-31 Kito Cheng <kito@andestech.com>
1084 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1085 compressed floating point instructions.
1087 2018-08-30 Kito Cheng <kito@andestech.com>
1089 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1090 riscv_opcode.xlen_requirement.
1091 * riscv-opc.c (riscv_opcodes): Update for struct change.
1093 2018-08-29 Martin Aberg <maberg@gaisler.com>
1095 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1096 psr (PWRPSR) instruction.
1098 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1100 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1102 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1104 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1106 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1108 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1109 loongson3a as an alias of gs464 for compatibility.
1110 * mips-opc.c (mips_opcodes): Change Comments.
1112 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1114 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1116 (print_mips_disassembler_options): Document -M loongson-ext.
1117 * mips-opc.c (LEXT2): New macro.
1118 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1120 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1122 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1124 (parse_mips_ase_option): Handle -M loongson-ext option.
1125 (print_mips_disassembler_options): Document -M loongson-ext.
1126 * mips-opc.c (IL3A): Delete.
1127 * mips-opc.c (LEXT): New macro.
1128 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1131 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1133 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1135 (parse_mips_ase_option): Handle -M loongson-cam option.
1136 (print_mips_disassembler_options): Document -M loongson-cam.
1137 * mips-opc.c (LCAM): New macro.
1138 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1141 2018-08-21 Alan Modra <amodra@gmail.com>
1143 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1144 (skip_optional_operands): Count optional operands, and update
1145 ppc_optional_operand_value call.
1146 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1147 (extract_vlensi): Likewise.
1148 (extract_fxm): Return default value for missing optional operand.
1149 (extract_ls, extract_raq, extract_tbr): Likewise.
1150 (insert_sxl, extract_sxl): New functions.
1151 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1152 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1153 flag and extra entry.
1154 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1157 2018-08-20 Alan Modra <amodra@gmail.com>
1159 * sh-opc.h (MASK): Simplify.
1161 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1163 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1164 BM_RESERVED0 or BM_RESERVED1
1165 (bm_rel_decode, bm_n_bytes): Ditto.
1167 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1171 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1173 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1174 address with the addr32 prefix and without base nor index
1177 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1179 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1180 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1181 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1182 (cpu_flags): Add CpuCMOV and CpuFXSR.
1183 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1184 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1185 * i386-init.h: Regenerated.
1186 * i386-tbl.h: Likewise.
1188 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1190 * arc-regs.h: Update auxiliary registers.
1192 2018-08-06 Jan Beulich <jbeulich@suse.com>
1194 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1195 (RegIP, RegIZ): Define.
1196 * i386-reg.tbl: Adjust comments.
1197 (rip): Use Qword instead of BaseIndex. Use RegIP.
1198 (eip): Use Dword instead of BaseIndex. Use RegIP.
1199 (riz): Add Qword. Use RegIZ.
1200 (eiz): Add Dword. Use RegIZ.
1201 * i386-tbl.h: Re-generate.
1203 2018-08-03 Jan Beulich <jbeulich@suse.com>
1205 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1206 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1207 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1208 * i386-tbl.h: Re-generate.
1210 2018-08-03 Jan Beulich <jbeulich@suse.com>
1212 * i386-gen.c (operand_types): Remove Mem field.
1213 * i386-opc.h (union i386_operand_type): Remove mem field.
1214 * i386-init.h, i386-tbl.h: Re-generate.
1216 2018-08-01 Alan Modra <amodra@gmail.com>
1218 * po/POTFILES.in: Regenerate.
1220 2018-07-31 Nick Clifton <nickc@redhat.com>
1222 * po/sv.po: Updated Swedish translation.
1224 2018-07-31 Jan Beulich <jbeulich@suse.com>
1226 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1227 * i386-init.h, i386-tbl.h: Re-generate.
1229 2018-07-31 Jan Beulich <jbeulich@suse.com>
1231 * i386-opc.h (ZEROING_MASKING) Rename to ...
1232 (DYNAMIC_MASKING): ... this. Adjust comment.
1233 * i386-opc.tbl (MaskingMorZ): Define.
1234 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1235 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1236 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1237 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1238 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1239 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1240 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1241 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1242 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1244 2018-07-31 Jan Beulich <jbeulich@suse.com>
1246 * i386-opc.tbl: Use element rather than vector size for AVX512*
1247 scatter/gather insns.
1248 * i386-tbl.h: Re-generate.
1250 2018-07-31 Jan Beulich <jbeulich@suse.com>
1252 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1253 (cpu_flags): Drop CpuVREX.
1254 * i386-opc.h (CpuVREX): Delete.
1255 (union i386_cpu_flags): Remove cpuvrex.
1256 * i386-init.h, i386-tbl.h: Re-generate.
1258 2018-07-30 Jim Wilson <jimw@sifive.com>
1260 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1262 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1264 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1266 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1267 * Makefile.in: Regenerated.
1268 * configure.ac: Add C-SKY.
1269 * configure: Regenerated.
1270 * csky-dis.c: New file.
1271 * csky-opc.h: New file.
1272 * disassemble.c (ARCH_csky): Define.
1273 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1274 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1276 2018-07-27 Alan Modra <amodra@gmail.com>
1278 * ppc-opc.c (insert_sprbat): Correct function parameter and
1280 (extract_sprbat): Likewise, variable too.
1282 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1283 Alan Modra <amodra@gmail.com>
1285 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1286 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1287 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1288 support disjointed BAT.
1289 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1290 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1291 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1293 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1294 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1296 * i386-gen.c (adjust_broadcast_modifier): New function.
1297 (process_i386_opcode_modifier): Add an argument for operands.
1298 Adjust the Broadcast value based on operands.
1299 (output_i386_opcode): Pass operand_types to
1300 process_i386_opcode_modifier.
1301 (process_i386_opcodes): Pass NULL as operands to
1302 process_i386_opcode_modifier.
1303 * i386-opc.h (BYTE_BROADCAST): New.
1304 (WORD_BROADCAST): Likewise.
1305 (DWORD_BROADCAST): Likewise.
1306 (QWORD_BROADCAST): Likewise.
1307 (i386_opcode_modifier): Expand broadcast to 3 bits.
1308 * i386-tbl.h: Regenerated.
1310 2018-07-24 Alan Modra <amodra@gmail.com>
1313 * or1k-desc.h: Regenerate.
1315 2018-07-24 Jan Beulich <jbeulich@suse.com>
1317 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1318 vcvtusi2ss, and vcvtusi2sd.
1319 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1320 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1321 * i386-tbl.h: Re-generate.
1323 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1325 * arc-opc.c (extract_w6): Fix extending the sign.
1327 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1329 * arc-tbl.h (vewt): Allow it for ARC EM family.
1331 2018-07-23 Alan Modra <amodra@gmail.com>
1334 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1335 opcode variants for mtspr/mfspr encodings.
1337 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1338 Maciej W. Rozycki <macro@mips.com>
1340 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1341 loongson3a descriptors.
1342 (parse_mips_ase_option): Handle -M loongson-mmi option.
1343 (print_mips_disassembler_options): Document -M loongson-mmi.
1344 * mips-opc.c (LMMI): New macro.
1345 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1348 2018-07-19 Jan Beulich <jbeulich@suse.com>
1350 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1351 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1352 IgnoreSize and [XYZ]MMword where applicable.
1353 * i386-tbl.h: Re-generate.
1355 2018-07-19 Jan Beulich <jbeulich@suse.com>
1357 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1358 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1359 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1360 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1361 * i386-tbl.h: Re-generate.
1363 2018-07-19 Jan Beulich <jbeulich@suse.com>
1365 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1366 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1367 VPCLMULQDQ templates into their respective AVX512VL counterparts
1368 where possible, using Disp8ShiftVL and CheckRegSize instead of
1369 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1370 * i386-tbl.h: Re-generate.
1372 2018-07-19 Jan Beulich <jbeulich@suse.com>
1374 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1375 AVX512VL counterparts where possible, using Disp8ShiftVL and
1376 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1377 IgnoreSize) as appropriate.
1378 * i386-tbl.h: Re-generate.
1380 2018-07-19 Jan Beulich <jbeulich@suse.com>
1382 * i386-opc.tbl: Fold AVX512BW templates into their respective
1383 AVX512VL counterparts where possible, using Disp8ShiftVL and
1384 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1385 IgnoreSize) as appropriate.
1386 * i386-tbl.h: Re-generate.
1388 2018-07-19 Jan Beulich <jbeulich@suse.com>
1390 * i386-opc.tbl: Fold AVX512CD templates into their respective
1391 AVX512VL counterparts where possible, using Disp8ShiftVL and
1392 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1393 IgnoreSize) as appropriate.
1394 * i386-tbl.h: Re-generate.
1396 2018-07-19 Jan Beulich <jbeulich@suse.com>
1398 * i386-opc.h (DISP8_SHIFT_VL): New.
1399 * i386-opc.tbl (Disp8ShiftVL): Define.
1400 (various): Fold AVX512VL templates into their respective
1401 AVX512F counterparts where possible, using Disp8ShiftVL and
1402 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1403 IgnoreSize) as appropriate.
1404 * i386-tbl.h: Re-generate.
1406 2018-07-19 Jan Beulich <jbeulich@suse.com>
1408 * Makefile.am: Change dependencies and rule for
1409 $(srcdir)/i386-init.h.
1410 * Makefile.in: Re-generate.
1411 * i386-gen.c (process_i386_opcodes): New local variable
1412 "marker". Drop opening of input file. Recognize marker and line
1414 * i386-opc.tbl (OPCODE_I386_H): Define.
1415 (i386-opc.h): Include it.
1418 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1421 * i386-opc.h (Byte): Update comments.
1427 (Xmmword): Likewise.
1428 (Ymmword): Likewise.
1429 (Zmmword): Likewise.
1430 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1432 * i386-tbl.h: Regenerated.
1434 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1436 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1437 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1438 * aarch64-asm-2.c: Regenerate.
1439 * aarch64-dis-2.c: Regenerate.
1440 * aarch64-opc-2.c: Regenerate.
1442 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1445 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1446 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1447 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1448 sqdmulh, sqrdmulh): Use Em16.
1450 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1452 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1453 csdb together with them.
1454 (thumb32_opcodes): Likewise.
1456 2018-07-11 Jan Beulich <jbeulich@suse.com>
1458 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1459 requiring 32-bit registers as operands 2 and 3. Improve
1461 (mwait, mwaitx): Fold templates. Improve comments.
1462 OPERAND_TYPE_INOUTPORTREG.
1463 * i386-tbl.h: Re-generate.
1465 2018-07-11 Jan Beulich <jbeulich@suse.com>
1467 * i386-gen.c (operand_type_init): Remove
1468 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1469 OPERAND_TYPE_INOUTPORTREG.
1470 * i386-init.h: Re-generate.
1472 2018-07-11 Jan Beulich <jbeulich@suse.com>
1474 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1475 (wrssq, wrussq): Add Qword.
1476 * i386-tbl.h: Re-generate.
1478 2018-07-11 Jan Beulich <jbeulich@suse.com>
1480 * i386-opc.h: Rename OTMax to OTNum.
1481 (OTNumOfUints): Adjust calculation.
1482 (OTUnused): Directly alias to OTNum.
1484 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1486 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1488 (lea_reg_xys): Likewise.
1489 (print_insn_loop_primitive): Rename `reg' local variable to
1492 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1495 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1497 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1500 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1501 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1503 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1506 * mips-dis.c (mips_option_arg_t): New enumeration.
1507 (mips_options): New variable.
1508 (disassembler_options_mips): New function.
1509 (print_mips_disassembler_options): Reimplement in terms of
1510 `disassembler_options_mips'.
1511 * arm-dis.c (disassembler_options_arm): Adapt to using the
1512 `disasm_options_and_args_t' structure.
1513 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1514 * s390-dis.c (disassembler_options_s390): Likewise.
1516 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1518 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1520 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1521 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1522 * testsuite/ld-arm/tls-longplt.d: Likewise.
1524 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1527 * aarch64-asm-2.c: Regenerate.
1528 * aarch64-dis-2.c: Likewise.
1529 * aarch64-opc-2.c: Likewise.
1530 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1531 * aarch64-opc.c (operand_general_constraint_met_p,
1532 aarch64_print_operand): Likewise.
1533 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1534 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1536 (AARCH64_OPERANDS): Add Em2.
1538 2018-06-26 Nick Clifton <nickc@redhat.com>
1540 * po/uk.po: Updated Ukranian translation.
1541 * po/de.po: Updated German translation.
1542 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1544 2018-06-26 Nick Clifton <nickc@redhat.com>
1546 * nfp-dis.c: Fix spelling mistake.
1548 2018-06-24 Nick Clifton <nickc@redhat.com>
1550 * configure: Regenerate.
1551 * po/opcodes.pot: Regenerate.
1553 2018-06-24 Nick Clifton <nickc@redhat.com>
1555 2.31 branch created.
1557 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1559 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1560 * aarch64-asm-2.c: Regenerate.
1561 * aarch64-dis-2.c: Likewise.
1563 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1565 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1566 `-M ginv' option description.
1568 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1571 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1574 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1576 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1577 * configure.ac: Remove AC_PREREQ.
1578 * Makefile.in: Re-generate.
1579 * aclocal.m4: Re-generate.
1580 * configure: Re-generate.
1582 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1584 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1585 mips64r6 descriptors.
1586 (parse_mips_ase_option): Handle -Mginv option.
1587 (print_mips_disassembler_options): Document -Mginv.
1588 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1590 (mips_opcodes): Define ginvi and ginvt.
1592 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1593 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1595 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1596 * mips-opc.c (CRC, CRC64): New macros.
1597 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1598 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1601 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1604 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1605 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1607 2018-06-06 Alan Modra <amodra@gmail.com>
1609 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1610 setjmp. Move init for some other vars later too.
1612 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1614 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1615 (dis_private): Add new fields for property section tracking.
1616 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1617 (xtensa_instruction_fits): New functions.
1618 (fetch_data): Bump minimal fetch size to 4.
1619 (print_insn_xtensa): Make struct dis_private static.
1620 Load and prepare property table on section change.
1621 Don't disassemble literals. Don't disassemble instructions that
1622 cross property table boundaries.
1624 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1626 * configure: Regenerated.
1628 2018-06-01 Jan Beulich <jbeulich@suse.com>
1630 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1631 * i386-tbl.h: Re-generate.
1633 2018-06-01 Jan Beulich <jbeulich@suse.com>
1635 * i386-opc.tbl (sldt, str): Add NoRex64.
1636 * i386-tbl.h: Re-generate.
1638 2018-06-01 Jan Beulich <jbeulich@suse.com>
1640 * i386-opc.tbl (invpcid): Add Oword.
1641 * i386-tbl.h: Re-generate.
1643 2018-06-01 Alan Modra <amodra@gmail.com>
1645 * sysdep.h (_bfd_error_handler): Don't declare.
1646 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1647 * rl78-decode.opc: Likewise.
1648 * msp430-decode.c: Regenerate.
1649 * rl78-decode.c: Regenerate.
1651 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1653 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1654 * i386-init.h : Regenerated.
1656 2018-05-25 Alan Modra <amodra@gmail.com>
1658 * Makefile.in: Regenerate.
1659 * po/POTFILES.in: Regenerate.
1661 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1663 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1664 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1665 (insert_bab, extract_bab, insert_btab, extract_btab,
1666 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1667 (BAT, BBA VBA RBS XB6S): Delete macros.
1668 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1669 (BB, BD, RBX, XC6): Update for new macros.
1670 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1671 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1672 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1673 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1675 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1677 * Makefile.am: Add support for s12z architecture.
1678 * configure.ac: Likewise.
1679 * disassemble.c: Likewise.
1680 * disassemble.h: Likewise.
1681 * Makefile.in: Regenerate.
1682 * configure: Regenerate.
1683 * s12z-dis.c: New file.
1686 2018-05-18 Alan Modra <amodra@gmail.com>
1688 * nfp-dis.c: Don't #include libbfd.h.
1689 (init_nfp3200_priv): Use bfd_get_section_contents.
1690 (nit_nfp6000_mecsr_sec): Likewise.
1692 2018-05-17 Nick Clifton <nickc@redhat.com>
1694 * po/zh_CN.po: Updated simplified Chinese translation.
1696 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1699 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1700 * aarch64-dis-2.c: Regenerate.
1702 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1705 * aarch64-asm.c (opintl.h): Include.
1706 (aarch64_ins_sysreg): Enforce read/write constraints.
1707 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1708 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1709 (F_REG_READ, F_REG_WRITE): New.
1710 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1711 AARCH64_OPND_SYSREG.
1712 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1713 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1714 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1715 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1716 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1717 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1718 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1719 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1720 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1721 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1722 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1723 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1724 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1725 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1726 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1727 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1728 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1730 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1733 * aarch64-dis.c (no_notes: New.
1734 (parse_aarch64_dis_option): Support notes.
1735 (aarch64_decode_insn, print_operands): Likewise.
1736 (print_aarch64_disassembler_options): Document notes.
1737 * aarch64-opc.c (aarch64_print_operand): Support notes.
1739 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1742 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1743 and take error struct.
1744 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1745 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1746 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1747 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1748 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1749 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1750 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1751 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1752 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1753 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1754 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1755 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1756 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1757 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1758 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1759 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1760 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1761 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1762 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1763 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1764 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1765 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1766 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1767 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1768 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1769 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1770 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1771 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1772 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1773 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1774 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1775 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1776 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1777 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1778 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1779 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1780 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1781 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1782 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1783 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1784 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1785 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1786 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1787 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1788 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1789 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1790 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1791 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1792 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1793 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1794 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1795 (determine_disassembling_preference, aarch64_decode_insn,
1796 print_insn_aarch64_word, print_insn_data): Take errors struct.
1797 (print_insn_aarch64): Use errors.
1798 * aarch64-asm-2.c: Regenerate.
1799 * aarch64-dis-2.c: Regenerate.
1800 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1801 boolean in aarch64_insert_operan.
1802 (print_operand_extractor): Likewise.
1803 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1805 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1807 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1809 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1811 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1813 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1815 * cr16-opc.c (cr16_instruction): Comment typo fix.
1816 * hppa-dis.c (print_insn_hppa): Likewise.
1818 2018-05-08 Jim Wilson <jimw@sifive.com>
1820 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1821 (match_c_slli64, match_srxi_as_c_srxi): New.
1822 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1823 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1824 <c.slli, c.srli, c.srai>: Use match_s_slli.
1825 <c.slli64, c.srli64, c.srai64>: New.
1827 2018-05-08 Alan Modra <amodra@gmail.com>
1829 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1830 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1831 partition opcode space for index lookup.
1833 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1835 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1836 <insn_length>: ...with this. Update usage.
1837 Remove duplicate call to *info->memory_error_func.
1839 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1840 H.J. Lu <hongjiu.lu@intel.com>
1842 * i386-dis.c (Gva): New.
1843 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1844 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1845 (prefix_table): New instructions (see prefix above).
1846 (mod_table): New instructions (see prefix above).
1847 (OP_G): Handle va_mode.
1848 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1849 CPU_MOVDIR64B_FLAGS.
1850 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1851 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1852 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1853 * i386-opc.tbl: Add movidir{i,64b}.
1854 * i386-init.h: Regenerated.
1855 * i386-tbl.h: Likewise.
1857 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1859 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1861 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1862 (AddrPrefixOpReg): This.
1863 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1864 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1866 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1868 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1869 (vle_num_opcodes): Likewise.
1870 (spe2_num_opcodes): Likewise.
1871 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1872 initialization loop.
1873 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1874 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1877 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1879 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1881 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1883 Makefile.am: Added nfp-dis.c.
1884 configure.ac: Added bfd_nfp_arch.
1885 disassemble.h: Added print_insn_nfp prototype.
1886 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1887 nfp-dis.c: New, for NFP support.
1888 po/POTFILES.in: Added nfp-dis.c to the list.
1889 Makefile.in: Regenerate.
1890 configure: Regenerate.
1892 2018-04-26 Jan Beulich <jbeulich@suse.com>
1894 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1895 templates into their base ones.
1896 * i386-tlb.h: Re-generate.
1898 2018-04-26 Jan Beulich <jbeulich@suse.com>
1900 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1901 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1902 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1903 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1904 * i386-init.h: Re-generate.
1906 2018-04-26 Jan Beulich <jbeulich@suse.com>
1908 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1909 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1910 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1911 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1913 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1915 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1917 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1918 cpuregzmm, and cpuregmask.
1919 * i386-init.h: Re-generate.
1920 * i386-tbl.h: Re-generate.
1922 2018-04-26 Jan Beulich <jbeulich@suse.com>
1924 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1925 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1926 * i386-init.h: Re-generate.
1928 2018-04-26 Jan Beulich <jbeulich@suse.com>
1930 * i386-gen.c (VexImmExt): Delete.
1931 * i386-opc.h (VexImmExt, veximmext): Delete.
1932 * i386-opc.tbl: Drop all VexImmExt uses.
1933 * i386-tlb.h: Re-generate.
1935 2018-04-25 Jan Beulich <jbeulich@suse.com>
1937 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1938 register-only forms.
1939 * i386-tlb.h: Re-generate.
1941 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1943 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1945 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1947 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1949 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1950 (cpu_flags): Add CpuCLDEMOTE.
1951 * i386-init.h: Regenerate.
1952 * i386-opc.h (enum): Add CpuCLDEMOTE,
1953 (i386_cpu_flags): Add cpucldemote.
1954 * i386-opc.tbl: Add cldemote.
1955 * i386-tbl.h: Regenerate.
1957 2018-04-16 Alan Modra <amodra@gmail.com>
1959 * Makefile.am: Remove sh5 and sh64 support.
1960 * configure.ac: Likewise.
1961 * disassemble.c: Likewise.
1962 * disassemble.h: Likewise.
1963 * sh-dis.c: Likewise.
1964 * sh64-dis.c: Delete.
1965 * sh64-opc.c: Delete.
1966 * sh64-opc.h: Delete.
1967 * Makefile.in: Regenerate.
1968 * configure: Regenerate.
1969 * po/POTFILES.in: Regenerate.
1971 2018-04-16 Alan Modra <amodra@gmail.com>
1973 * Makefile.am: Remove w65 support.
1974 * configure.ac: Likewise.
1975 * disassemble.c: Likewise.
1976 * disassemble.h: Likewise.
1977 * w65-dis.c: Delete.
1978 * w65-opc.h: Delete.
1979 * Makefile.in: Regenerate.
1980 * configure: Regenerate.
1981 * po/POTFILES.in: Regenerate.
1983 2018-04-16 Alan Modra <amodra@gmail.com>
1985 * configure.ac: Remove we32k support.
1986 * configure: Regenerate.
1988 2018-04-16 Alan Modra <amodra@gmail.com>
1990 * Makefile.am: Remove m88k support.
1991 * configure.ac: Likewise.
1992 * disassemble.c: Likewise.
1993 * disassemble.h: Likewise.
1994 * m88k-dis.c: Delete.
1995 * Makefile.in: Regenerate.
1996 * configure: Regenerate.
1997 * po/POTFILES.in: Regenerate.
1999 2018-04-16 Alan Modra <amodra@gmail.com>
2001 * Makefile.am: Remove i370 support.
2002 * configure.ac: Likewise.
2003 * disassemble.c: Likewise.
2004 * disassemble.h: Likewise.
2005 * i370-dis.c: Delete.
2006 * i370-opc.c: Delete.
2007 * Makefile.in: Regenerate.
2008 * configure: Regenerate.
2009 * po/POTFILES.in: Regenerate.
2011 2018-04-16 Alan Modra <amodra@gmail.com>
2013 * Makefile.am: Remove h8500 support.
2014 * configure.ac: Likewise.
2015 * disassemble.c: Likewise.
2016 * disassemble.h: Likewise.
2017 * h8500-dis.c: Delete.
2018 * h8500-opc.h: Delete.
2019 * Makefile.in: Regenerate.
2020 * configure: Regenerate.
2021 * po/POTFILES.in: Regenerate.
2023 2018-04-16 Alan Modra <amodra@gmail.com>
2025 * configure.ac: Remove tahoe support.
2026 * configure: Regenerate.
2028 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
2030 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2032 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2034 * i386-tbl.h: Regenerated.
2036 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2038 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2039 PREFIX_MOD_1_0FAE_REG_6.
2041 (OP_E_register): Use va_mode.
2042 * i386-dis-evex.h (prefix_table):
2043 New instructions (see prefixes above).
2044 * i386-gen.c (cpu_flag_init): Add WAITPKG.
2045 (cpu_flags): Likewise.
2046 * i386-opc.h (enum): Likewise.
2047 (i386_cpu_flags): Likewise.
2048 * i386-opc.tbl: Add umonitor, umwait, tpause.
2049 * i386-init.h: Regenerate.
2050 * i386-tbl.h: Likewise.
2052 2018-04-11 Alan Modra <amodra@gmail.com>
2054 * opcodes/i860-dis.c: Delete.
2055 * opcodes/i960-dis.c: Delete.
2056 * Makefile.am: Remove i860 and i960 support.
2057 * configure.ac: Likewise.
2058 * disassemble.c: Likewise.
2059 * disassemble.h: Likewise.
2060 * Makefile.in: Regenerate.
2061 * configure: Regenerate.
2062 * po/POTFILES.in: Regenerate.
2064 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
2067 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2069 (print_insn): Clear vex instead of vex.evex.
2071 2018-04-04 Nick Clifton <nickc@redhat.com>
2073 * po/es.po: Updated Spanish translation.
2075 2018-03-28 Jan Beulich <jbeulich@suse.com>
2077 * i386-gen.c (opcode_modifiers): Delete VecESize.
2078 * i386-opc.h (VecESize): Delete.
2079 (struct i386_opcode_modifier): Delete vecesize.
2080 * i386-opc.tbl: Drop VecESize.
2081 * i386-tlb.h: Re-generate.
2083 2018-03-28 Jan Beulich <jbeulich@suse.com>
2085 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2086 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2087 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2088 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2089 * i386-tlb.h: Re-generate.
2091 2018-03-28 Jan Beulich <jbeulich@suse.com>
2093 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2095 * i386-tlb.h: Re-generate.
2097 2018-03-28 Jan Beulich <jbeulich@suse.com>
2099 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2100 (vex_len_table): Drop Y for vcvt*2si.
2101 (putop): Replace plain 'Y' handling by abort().
2103 2018-03-28 Nick Clifton <nickc@redhat.com>
2106 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2107 instructions with only a base address register.
2108 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2109 handle AARHC64_OPND_SVE_ADDR_R.
2110 (aarch64_print_operand): Likewise.
2111 * aarch64-asm-2.c: Regenerate.
2112 * aarch64_dis-2.c: Regenerate.
2113 * aarch64-opc-2.c: Regenerate.
2115 2018-03-22 Jan Beulich <jbeulich@suse.com>
2117 * i386-opc.tbl: Drop VecESize from register only insn forms and
2118 memory forms not allowing broadcast.
2119 * i386-tlb.h: Re-generate.
2121 2018-03-22 Jan Beulich <jbeulich@suse.com>
2123 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2124 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2125 sha256*): Drop Disp<N>.
2127 2018-03-22 Jan Beulich <jbeulich@suse.com>
2129 * i386-dis.c (EbndS, bnd_swap_mode): New.
2130 (prefix_table): Use EbndS.
2131 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2132 * i386-opc.tbl (bndmov): Move misplaced Load.
2133 * i386-tlb.h: Re-generate.
2135 2018-03-22 Jan Beulich <jbeulich@suse.com>
2137 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2138 templates allowing memory operands and folded ones for register
2140 * i386-tlb.h: Re-generate.
2142 2018-03-22 Jan Beulich <jbeulich@suse.com>
2144 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2145 256-bit templates. Drop redundant leftover Disp<N>.
2146 * i386-tlb.h: Re-generate.
2148 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
2150 * riscv-opc.c (riscv_insn_types): New.
2152 2018-03-13 Nick Clifton <nickc@redhat.com>
2154 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2156 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2158 * i386-opc.tbl: Add Optimize to clr.
2159 * i386-tbl.h: Regenerated.
2161 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2163 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2164 * i386-opc.h (OldGcc): Removed.
2165 (i386_opcode_modifier): Remove oldgcc.
2166 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2167 instructions for old (<= 2.8.1) versions of gcc.
2168 * i386-tbl.h: Regenerated.
2170 2018-03-08 Jan Beulich <jbeulich@suse.com>
2172 * i386-opc.h (EVEXDYN): New.
2173 * i386-opc.tbl: Fold various AVX512VL templates.
2174 * i386-tlb.h: Re-generate.
2176 2018-03-08 Jan Beulich <jbeulich@suse.com>
2178 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2179 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2180 vpexpandd, vpexpandq): Fold AFX512VF templates.
2181 * i386-tlb.h: Re-generate.
2183 2018-03-08 Jan Beulich <jbeulich@suse.com>
2185 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2186 Fold 128- and 256-bit VEX-encoded templates.
2187 * i386-tlb.h: Re-generate.
2189 2018-03-08 Jan Beulich <jbeulich@suse.com>
2191 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2192 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2193 vpexpandd, vpexpandq): Fold AVX512F templates.
2194 * i386-tlb.h: Re-generate.
2196 2018-03-08 Jan Beulich <jbeulich@suse.com>
2198 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2199 64-bit templates. Drop Disp<N>.
2200 * i386-tlb.h: Re-generate.
2202 2018-03-08 Jan Beulich <jbeulich@suse.com>
2204 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2205 and 256-bit templates.
2206 * i386-tlb.h: Re-generate.
2208 2018-03-08 Jan Beulich <jbeulich@suse.com>
2210 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2211 * i386-tlb.h: Re-generate.
2213 2018-03-08 Jan Beulich <jbeulich@suse.com>
2215 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2217 * i386-tlb.h: Re-generate.
2219 2018-03-08 Jan Beulich <jbeulich@suse.com>
2221 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2222 * i386-tlb.h: Re-generate.
2224 2018-03-08 Jan Beulich <jbeulich@suse.com>
2226 * i386-gen.c (opcode_modifiers): Delete FloatD.
2227 * i386-opc.h (FloatD): Delete.
2228 (struct i386_opcode_modifier): Delete floatd.
2229 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2231 * i386-tlb.h: Re-generate.
2233 2018-03-08 Jan Beulich <jbeulich@suse.com>
2235 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2237 2018-03-08 Jan Beulich <jbeulich@suse.com>
2239 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2240 * i386-tlb.h: Re-generate.
2242 2018-03-08 Jan Beulich <jbeulich@suse.com>
2244 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2246 * i386-tlb.h: Re-generate.
2248 2018-03-07 Alan Modra <amodra@gmail.com>
2250 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2252 * disassemble.h (print_insn_rs6000): Delete.
2253 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2254 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2255 (print_insn_rs6000): Delete.
2257 2018-03-03 Alan Modra <amodra@gmail.com>
2259 * sysdep.h (opcodes_error_handler): Define.
2260 (_bfd_error_handler): Declare.
2261 * Makefile.am: Remove stray #.
2262 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2264 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2265 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2266 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2267 opcodes_error_handler to print errors. Standardize error messages.
2268 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2269 and include opintl.h.
2270 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2271 * i386-gen.c: Standardize error messages.
2272 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2273 * Makefile.in: Regenerate.
2274 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2275 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2276 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2277 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2278 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2279 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2280 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2281 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2282 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2283 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2284 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2285 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2286 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2288 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2290 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2291 vpsub[bwdq] instructions.
2292 * i386-tbl.h: Regenerated.
2294 2018-03-01 Alan Modra <amodra@gmail.com>
2296 * configure.ac (ALL_LINGUAS): Sort.
2297 * configure: Regenerate.
2299 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2301 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2302 macro by assignements.
2304 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2307 * i386-gen.c (opcode_modifiers): Add Optimize.
2308 * i386-opc.h (Optimize): New enum.
2309 (i386_opcode_modifier): Add optimize.
2310 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2311 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2312 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2313 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2314 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2316 * i386-tbl.h: Regenerated.
2318 2018-02-26 Alan Modra <amodra@gmail.com>
2320 * crx-dis.c (getregliststring): Allocate a large enough buffer
2321 to silence false positive gcc8 warning.
2323 2018-02-22 Shea Levy <shea@shealevy.com>
2325 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2327 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2329 * i386-opc.tbl: Add {rex},
2330 * i386-tbl.h: Regenerated.
2332 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2334 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2335 (mips16_opcodes): Replace `M' with `m' for "restore".
2337 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2339 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2341 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2343 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2344 variable to `function_index'.
2346 2018-02-13 Nick Clifton <nickc@redhat.com>
2349 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2350 about truncation of printing.
2352 2018-02-12 Henry Wong <henry@stuffedcow.net>
2354 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2356 2018-02-05 Nick Clifton <nickc@redhat.com>
2358 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2360 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2362 * i386-dis.c (enum): Add pconfig.
2363 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2364 (cpu_flags): Add CpuPCONFIG.
2365 * i386-opc.h (enum): Add CpuPCONFIG.
2366 (i386_cpu_flags): Add cpupconfig.
2367 * i386-opc.tbl: Add PCONFIG instruction.
2368 * i386-init.h: Regenerate.
2369 * i386-tbl.h: Likewise.
2371 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2373 * i386-dis.c (enum): Add PREFIX_0F09.
2374 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2375 (cpu_flags): Add CpuWBNOINVD.
2376 * i386-opc.h (enum): Add CpuWBNOINVD.
2377 (i386_cpu_flags): Add cpuwbnoinvd.
2378 * i386-opc.tbl: Add WBNOINVD instruction.
2379 * i386-init.h: Regenerate.
2380 * i386-tbl.h: Likewise.
2382 2018-01-17 Jim Wilson <jimw@sifive.com>
2384 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2386 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2388 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2389 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2390 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2391 (cpu_flags): Add CpuIBT, CpuSHSTK.
2392 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2393 (i386_cpu_flags): Add cpuibt, cpushstk.
2394 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2395 * i386-init.h: Regenerate.
2396 * i386-tbl.h: Likewise.
2398 2018-01-16 Nick Clifton <nickc@redhat.com>
2400 * po/pt_BR.po: Updated Brazilian Portugese translation.
2401 * po/de.po: Updated German translation.
2403 2018-01-15 Jim Wilson <jimw@sifive.com>
2405 * riscv-opc.c (match_c_nop): New.
2406 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2408 2018-01-15 Nick Clifton <nickc@redhat.com>
2410 * po/uk.po: Updated Ukranian translation.
2412 2018-01-13 Nick Clifton <nickc@redhat.com>
2414 * po/opcodes.pot: Regenerated.
2416 2018-01-13 Nick Clifton <nickc@redhat.com>
2418 * configure: Regenerate.
2420 2018-01-13 Nick Clifton <nickc@redhat.com>
2422 2.30 branch created.
2424 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2426 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2427 * i386-tbl.h: Regenerate.
2429 2018-01-10 Jan Beulich <jbeulich@suse.com>
2431 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2432 * i386-tbl.h: Re-generate.
2434 2018-01-10 Jan Beulich <jbeulich@suse.com>
2436 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2437 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2438 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2439 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2440 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2441 Disp8MemShift of AVX512VL forms.
2442 * i386-tbl.h: Re-generate.
2444 2018-01-09 Jim Wilson <jimw@sifive.com>
2446 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2447 then the hi_addr value is zero.
2449 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2451 * arm-dis.c (arm_opcodes): Add csdb.
2452 (thumb32_opcodes): Add csdb.
2454 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2456 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2457 * aarch64-asm-2.c: Regenerate.
2458 * aarch64-dis-2.c: Regenerate.
2459 * aarch64-opc-2.c: Regenerate.
2461 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2464 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2465 Remove AVX512 vmovd with 64-bit operands.
2466 * i386-tbl.h: Regenerated.
2468 2018-01-05 Jim Wilson <jimw@sifive.com>
2470 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2473 2018-01-03 Alan Modra <amodra@gmail.com>
2475 Update year range in copyright notice of all files.
2477 2018-01-02 Jan Beulich <jbeulich@suse.com>
2479 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2480 and OPERAND_TYPE_REGZMM entries.
2482 For older changes see ChangeLog-2017
2484 Copyright (C) 2018 Free Software Foundation, Inc.
2486 Copying and distribution of this file, with or without modification,
2487 are permitted in any medium without royalty provided the copyright
2488 notice and this notice are preserved.
2494 version-control: never