1 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
3 * riscv-opc.c (riscv_ext_version_table): The table used to store
4 all information about the supported spec and the corresponding ISA
5 versions. Currently, only Zicsr is supported to verify the
6 correctness of Z sub extension settings. Others will be supported
8 (struct isa_spec_t, isa_specs): List for all supported ISA spec
9 classes and the corresponding strings.
10 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
11 spec class by giving a ISA spec string.
12 * riscv-opc.c (struct priv_spec_t): New structure.
13 (struct priv_spec_t priv_specs): List for all supported privilege spec
14 classes and the corresponding strings.
15 (riscv_get_priv_spec_class): New function. Get the corresponding
16 privilege spec class by giving a spec string.
17 (riscv_get_priv_spec_name): New function. Get the corresponding
18 privilege spec string by giving a CSR version class.
19 * riscv-dis.c: Updated since DECLARE_CSR is changed.
20 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
21 according to the chosen version. Build a hash table riscv_csr_hash to
22 store the valid CSR for the chosen pirv verison. Dump the direct
23 CSR address rather than it's name if it is invalid.
24 (parse_riscv_dis_option_without_args): New function. Parse the options
26 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
27 parse the options without arguments first, and then handle the options
28 with arguments. Add the new option -Mpriv-spec, which has argument.
29 * riscv-dis.c (print_riscv_disassembler_options): Add description
30 about the new OBJDUMP option.
32 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
34 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
35 WC values on POWER10 sync, dcbf and wait instructions.
36 (insert_pl, extract_pl): New functions.
37 (L2OPT, LS, WC): Use insert_ls and extract_ls.
38 (LS3): New , 3-bit L for sync.
39 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
40 (SC2, PL): New, 2-bit SC and PL for sync and wait.
41 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
42 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
43 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
44 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
45 <wait>: Enable PL operand on POWER10.
46 <dcbf>: Enable L3OPT operand on POWER10.
47 <sync>: Enable SC2 operand on POWER10.
49 2020-05-19 Stafford Horne <shorne@gmail.com>
52 * or1k-asm.c: Regenerate.
53 * or1k-desc.c: Regenerate.
54 * or1k-desc.h: Regenerate.
55 * or1k-dis.c: Regenerate.
56 * or1k-ibld.c: Regenerate.
57 * or1k-opc.c: Regenerate.
58 * or1k-opc.h: Regenerate.
59 * or1k-opinst.c: Regenerate.
61 2020-05-11 Alan Modra <amodra@gmail.com>
63 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
66 2020-05-11 Alan Modra <amodra@gmail.com>
68 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
69 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
71 2020-05-11 Alan Modra <amodra@gmail.com>
73 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
75 2020-05-11 Alan Modra <amodra@gmail.com>
77 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
78 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
80 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
82 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
85 2020-05-11 Alan Modra <amodra@gmail.com>
87 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
88 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
89 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
90 (prefix_opcodes): Add xxeval.
92 2020-05-11 Alan Modra <amodra@gmail.com>
94 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
95 xxgenpcvwm, xxgenpcvdm.
97 2020-05-11 Alan Modra <amodra@gmail.com>
99 * ppc-opc.c (MP, VXVAM_MASK): Define.
100 (VXVAPS_MASK): Use VXVA_MASK.
101 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
102 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
103 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
104 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
106 2020-05-11 Alan Modra <amodra@gmail.com>
107 Peter Bergner <bergner@linux.ibm.com>
109 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
111 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
112 YMSK2, XA6a, XA6ap, XB6a entries.
113 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
114 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
116 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
117 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
118 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
119 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
120 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
121 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
122 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
123 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
124 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
125 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
126 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
127 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
128 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
129 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
131 2020-05-11 Alan Modra <amodra@gmail.com>
133 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
134 (insert_xts, extract_xts): New functions.
135 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
136 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
137 (VXRC_MASK, VXSH_MASK): Define.
138 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
139 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
140 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
141 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
142 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
143 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
144 xxblendvh, xxblendvw, xxblendvd, xxpermx.
146 2020-05-11 Alan Modra <amodra@gmail.com>
148 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
149 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
150 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
151 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
152 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
154 2020-05-11 Alan Modra <amodra@gmail.com>
156 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
157 (XTP, DQXP, DQXP_MASK): Define.
158 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
159 (prefix_opcodes): Add plxvp and pstxvp.
161 2020-05-11 Alan Modra <amodra@gmail.com>
163 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
164 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
165 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
167 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
169 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
171 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
173 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
175 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
177 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
179 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
181 2020-05-11 Alan Modra <amodra@gmail.com>
183 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
185 2020-05-11 Alan Modra <amodra@gmail.com>
187 * ppc-dis.c (ppc_opts): Add "power10" entry.
188 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
189 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
191 2020-05-11 Nick Clifton <nickc@redhat.com>
193 * po/fr.po: Updated French translation.
195 2020-04-30 Alex Coplan <alex.coplan@arm.com>
197 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
198 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
199 (operand_general_constraint_met_p): validate
200 AARCH64_OPND_UNDEFINED.
201 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
203 * aarch64-asm-2.c: Regenerated.
204 * aarch64-dis-2.c: Regenerated.
205 * aarch64-opc-2.c: Regenerated.
207 2020-04-29 Nick Clifton <nickc@redhat.com>
210 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
213 2020-04-29 Nick Clifton <nickc@redhat.com>
215 * po/sv.po: Updated Swedish translation.
217 2020-04-29 Nick Clifton <nickc@redhat.com>
220 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
221 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
222 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
225 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
228 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
229 cmpi only on m68020up and cpu32.
231 2020-04-20 Sudakshina Das <sudi.das@arm.com>
233 * aarch64-asm.c (aarch64_ins_none): New.
234 * aarch64-asm.h (ins_none): New declaration.
235 * aarch64-dis.c (aarch64_ext_none): New.
236 * aarch64-dis.h (ext_none): New declaration.
237 * aarch64-opc.c (aarch64_print_operand): Update case for
238 AARCH64_OPND_BARRIER_PSB.
239 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
240 (AARCH64_OPERANDS): Update inserter/extracter for
241 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
242 * aarch64-asm-2.c: Regenerated.
243 * aarch64-dis-2.c: Regenerated.
244 * aarch64-opc-2.c: Regenerated.
246 2020-04-20 Sudakshina Das <sudi.das@arm.com>
248 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
249 (aarch64_feature_ras, RAS): Likewise.
250 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
251 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
252 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
253 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
254 * aarch64-asm-2.c: Regenerated.
255 * aarch64-dis-2.c: Regenerated.
256 * aarch64-opc-2.c: Regenerated.
258 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
260 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
261 (print_insn_neon): Support disassembly of conditional
264 2020-02-16 David Faust <david.faust@oracle.com>
266 * bpf-desc.c: Regenerate.
267 * bpf-desc.h: Likewise.
268 * bpf-opc.c: Regenerate.
269 * bpf-opc.h: Likewise.
271 2020-04-07 Lili Cui <lili.cui@intel.com>
273 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
274 (prefix_table): New instructions (see prefixes above).
276 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
277 CPU_ANY_TSXLDTRK_FLAGS.
278 (cpu_flags): Add CpuTSXLDTRK.
279 * i386-opc.h (enum): Add CpuTSXLDTRK.
280 (i386_cpu_flags): Add cputsxldtrk.
281 * i386-opc.tbl: Add XSUSPLDTRK insns.
282 * i386-init.h: Regenerate.
283 * i386-tbl.h: Likewise.
285 2020-04-02 Lili Cui <lili.cui@intel.com>
287 * i386-dis.c (prefix_table): New instructions serialize.
288 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
289 CPU_ANY_SERIALIZE_FLAGS.
290 (cpu_flags): Add CpuSERIALIZE.
291 * i386-opc.h (enum): Add CpuSERIALIZE.
292 (i386_cpu_flags): Add cpuserialize.
293 * i386-opc.tbl: Add SERIALIZE insns.
294 * i386-init.h: Regenerate.
295 * i386-tbl.h: Likewise.
297 2020-03-26 Alan Modra <amodra@gmail.com>
299 * disassemble.h (opcodes_assert): Declare.
300 (OPCODES_ASSERT): Define.
301 * disassemble.c: Don't include assert.h. Include opintl.h.
302 (opcodes_assert): New function.
303 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
304 (bfd_h8_disassemble): Reduce size of data array. Correctly
305 calculate maxlen. Omit insn decoding when insn length exceeds
306 maxlen. Exit from nibble loop when looking for E, before
307 accessing next data byte. Move processing of E outside loop.
308 Replace tests of maxlen in loop with assertions.
310 2020-03-26 Alan Modra <amodra@gmail.com>
312 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
314 2020-03-25 Alan Modra <amodra@gmail.com>
316 * z80-dis.c (suffix): Init mybuf.
318 2020-03-22 Alan Modra <amodra@gmail.com>
320 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
321 successflly read from section.
323 2020-03-22 Alan Modra <amodra@gmail.com>
325 * arc-dis.c (find_format): Use ISO C string concatenation rather
326 than line continuation within a string. Don't access needs_limm
327 before testing opcode != NULL.
329 2020-03-22 Alan Modra <amodra@gmail.com>
331 * ns32k-dis.c (print_insn_arg): Update comment.
332 (print_insn_ns32k): Reduce size of index_offset array, and
333 initialize, passing -1 to print_insn_arg for args that are not
334 an index. Don't exit arg loop early. Abort on bad arg number.
336 2020-03-22 Alan Modra <amodra@gmail.com>
338 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
339 * s12z-opc.c: Formatting.
340 (operands_f): Return an int.
341 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
342 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
343 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
344 (exg_sex_discrim): Likewise.
345 (create_immediate_operand, create_bitfield_operand),
346 (create_register_operand_with_size, create_register_all_operand),
347 (create_register_all16_operand, create_simple_memory_operand),
348 (create_memory_operand, create_memory_auto_operand): Don't
349 segfault on malloc failure.
350 (z_ext24_decode): Return an int status, negative on fail, zero
352 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
353 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
354 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
355 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
356 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
357 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
358 (loop_primitive_decode, shift_decode, psh_pul_decode),
359 (bit_field_decode): Similarly.
360 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
361 to return value, update callers.
362 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
363 Don't segfault on NULL operand.
364 (decode_operation): Return OP_INVALID on first fail.
365 (decode_s12z): Check all reads, returning -1 on fail.
367 2020-03-20 Alan Modra <amodra@gmail.com>
369 * metag-dis.c (print_insn_metag): Don't ignore status from
372 2020-03-20 Alan Modra <amodra@gmail.com>
374 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
375 Initialize parts of buffer not written when handling a possible
376 2-byte insn at end of section. Don't attempt decoding of such
377 an insn by the 4-byte machinery.
379 2020-03-20 Alan Modra <amodra@gmail.com>
381 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
382 partially filled buffer. Prevent lookup of 4-byte insns when
383 only VLE 2-byte insns are possible due to section size. Print
384 ".word" rather than ".long" for 2-byte leftovers.
386 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
389 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
391 2020-03-13 Jan Beulich <jbeulich@suse.com>
393 * i386-dis.c (X86_64_0D): Rename to ...
394 (X86_64_0E): ... this.
396 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
398 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
399 * Makefile.in: Regenerated.
401 2020-03-09 Jan Beulich <jbeulich@suse.com>
403 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
405 * i386-tbl.h: Re-generate.
407 2020-03-09 Jan Beulich <jbeulich@suse.com>
409 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
410 vprot*, vpsha*, and vpshl*.
411 * i386-tbl.h: Re-generate.
413 2020-03-09 Jan Beulich <jbeulich@suse.com>
415 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
416 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
417 * i386-tbl.h: Re-generate.
419 2020-03-09 Jan Beulich <jbeulich@suse.com>
421 * i386-gen.c (set_bitfield): Ignore zero-length field names.
422 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
423 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
424 * i386-tbl.h: Re-generate.
426 2020-03-09 Jan Beulich <jbeulich@suse.com>
428 * i386-gen.c (struct template_arg, struct template_instance,
429 struct template_param, struct template, templates,
430 parse_template, expand_templates): New.
431 (process_i386_opcodes): Various local variables moved to
432 expand_templates. Call parse_template and expand_templates.
433 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
434 * i386-tbl.h: Re-generate.
436 2020-03-06 Jan Beulich <jbeulich@suse.com>
438 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
439 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
440 register and memory source templates. Replace VexW= by VexW*
442 * i386-tbl.h: Re-generate.
444 2020-03-06 Jan Beulich <jbeulich@suse.com>
446 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
447 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
448 * i386-tbl.h: Re-generate.
450 2020-03-06 Jan Beulich <jbeulich@suse.com>
452 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
453 * i386-tbl.h: Re-generate.
455 2020-03-06 Jan Beulich <jbeulich@suse.com>
457 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
458 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
459 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
460 VexW0 on SSE2AVX variants.
461 (vmovq): Drop NoRex64 from XMM/XMM variants.
462 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
463 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
464 applicable use VexW0.
465 * i386-tbl.h: Re-generate.
467 2020-03-06 Jan Beulich <jbeulich@suse.com>
469 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
470 * i386-opc.h (Rex64): Delete.
471 (struct i386_opcode_modifier): Remove rex64 field.
472 * i386-opc.tbl (crc32): Drop Rex64.
473 Replace Rex64 with Size64 everywhere else.
474 * i386-tbl.h: Re-generate.
476 2020-03-06 Jan Beulich <jbeulich@suse.com>
478 * i386-dis.c (OP_E_memory): Exclude recording of used address
479 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
480 addressed memory operands for MPX insns.
482 2020-03-06 Jan Beulich <jbeulich@suse.com>
484 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
485 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
486 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
487 (ptwrite): Split into non-64-bit and 64-bit forms.
488 * i386-tbl.h: Re-generate.
490 2020-03-06 Jan Beulich <jbeulich@suse.com>
492 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
494 * i386-tbl.h: Re-generate.
496 2020-03-04 Jan Beulich <jbeulich@suse.com>
498 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
499 (prefix_table): Move vmmcall here. Add vmgexit.
500 (rm_table): Replace vmmcall entry by prefix_table[] escape.
501 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
502 (cpu_flags): Add CpuSEV_ES entry.
503 * i386-opc.h (CpuSEV_ES): New.
504 (union i386_cpu_flags): Add cpusev_es field.
505 * i386-opc.tbl (vmgexit): New.
506 * i386-init.h, i386-tbl.h: Re-generate.
508 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
510 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
512 * i386-opc.h (IGNORESIZE): New.
513 (DEFAULTSIZE): Likewise.
514 (IgnoreSize): Removed.
515 (DefaultSize): Likewise.
517 (i386_opcode_modifier): Replace ignoresize/defaultsize with
519 * i386-opc.tbl (IgnoreSize): New.
520 (DefaultSize): Likewise.
521 * i386-tbl.h: Regenerated.
523 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
526 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
529 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
532 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
533 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
534 * i386-tbl.h: Regenerated.
536 2020-02-26 Alan Modra <amodra@gmail.com>
538 * aarch64-asm.c: Indent labels correctly.
539 * aarch64-dis.c: Likewise.
540 * aarch64-gen.c: Likewise.
541 * aarch64-opc.c: Likewise.
542 * alpha-dis.c: Likewise.
543 * i386-dis.c: Likewise.
544 * nds32-asm.c: Likewise.
545 * nfp-dis.c: Likewise.
546 * visium-dis.c: Likewise.
548 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
550 * arc-regs.h (int_vector_base): Make it available for all ARC
553 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
555 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
558 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
560 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
561 c.mv/c.li if rs1 is zero.
563 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
565 * i386-gen.c (cpu_flag_init): Replace CpuABM with
566 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
568 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
569 * i386-opc.h (CpuABM): Removed.
571 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
572 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
573 popcnt. Remove CpuABM from lzcnt.
574 * i386-init.h: Regenerated.
575 * i386-tbl.h: Likewise.
577 2020-02-17 Jan Beulich <jbeulich@suse.com>
579 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
580 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
581 VexW1 instead of open-coding them.
582 * i386-tbl.h: Re-generate.
584 2020-02-17 Jan Beulich <jbeulich@suse.com>
586 * i386-opc.tbl (AddrPrefixOpReg): Define.
587 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
588 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
589 templates. Drop NoRex64.
590 * i386-tbl.h: Re-generate.
592 2020-02-17 Jan Beulich <jbeulich@suse.com>
595 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
596 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
597 into Intel syntax instance (with Unpsecified) and AT&T one
599 (vcvtneps2bf16): Likewise, along with folding the two so far
601 * i386-tbl.h: Re-generate.
603 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
605 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
608 2020-02-17 Alan Modra <amodra@gmail.com>
610 * i386-gen.c (cpu_flag_init): Correct last change.
612 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
614 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
617 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
619 * i386-opc.tbl (movsx): Remove Intel syntax comments.
622 2020-02-14 Jan Beulich <jbeulich@suse.com>
625 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
626 destination for Cpu64-only variant.
627 (movzx): Fold patterns.
628 * i386-tbl.h: Re-generate.
630 2020-02-13 Jan Beulich <jbeulich@suse.com>
632 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
633 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
634 CPU_ANY_SSE4_FLAGS entry.
635 * i386-init.h: Re-generate.
637 2020-02-12 Jan Beulich <jbeulich@suse.com>
639 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
640 with Unspecified, making the present one AT&T syntax only.
641 * i386-tbl.h: Re-generate.
643 2020-02-12 Jan Beulich <jbeulich@suse.com>
645 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
646 * i386-tbl.h: Re-generate.
648 2020-02-12 Jan Beulich <jbeulich@suse.com>
651 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
652 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
653 Amd64 and Intel64 templates.
654 (call, jmp): Likewise for far indirect variants. Dro
656 * i386-tbl.h: Re-generate.
658 2020-02-11 Jan Beulich <jbeulich@suse.com>
660 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
661 * i386-opc.h (ShortForm): Delete.
662 (struct i386_opcode_modifier): Remove shortform field.
663 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
664 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
665 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
666 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
668 * i386-tbl.h: Re-generate.
670 2020-02-11 Jan Beulich <jbeulich@suse.com>
672 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
673 fucompi): Drop ShortForm from operand-less templates.
674 * i386-tbl.h: Re-generate.
676 2020-02-11 Alan Modra <amodra@gmail.com>
678 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
679 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
680 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
681 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
682 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
684 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
686 * arm-dis.c (print_insn_cde): Define 'V' parse character.
687 (cde_opcodes): Add VCX* instructions.
689 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
690 Matthew Malcomson <matthew.malcomson@arm.com>
692 * arm-dis.c (struct cdeopcode32): New.
693 (CDE_OPCODE): New macro.
694 (cde_opcodes): New disassembly table.
695 (regnames): New option to table.
696 (cde_coprocs): New global variable.
697 (print_insn_cde): New
698 (print_insn_thumb32): Use print_insn_cde.
699 (parse_arm_disassembler_options): Parse coprocN args.
701 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
704 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
706 * i386-opc.h (AMD64): Removed.
710 (INTEL64ONLY): Likewise.
711 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
712 * i386-opc.tbl (Amd64): New.
714 (Intel64Only): Likewise.
715 Replace AMD64 with Amd64. Update sysenter/sysenter with
716 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
717 * i386-tbl.h: Regenerated.
719 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
722 * z80-dis.c: Add support for GBZ80 opcodes.
724 2020-02-04 Alan Modra <amodra@gmail.com>
726 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
728 2020-02-03 Alan Modra <amodra@gmail.com>
730 * m32c-ibld.c: Regenerate.
732 2020-02-01 Alan Modra <amodra@gmail.com>
734 * frv-ibld.c: Regenerate.
736 2020-01-31 Jan Beulich <jbeulich@suse.com>
738 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
739 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
740 (OP_E_memory): Replace xmm_mdq_mode case label by
741 vex_scalar_w_dq_mode one.
742 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
744 2020-01-31 Jan Beulich <jbeulich@suse.com>
746 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
747 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
748 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
749 (intel_operand_size): Drop vex_w_dq_mode case label.
751 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
753 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
754 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
756 2020-01-30 Alan Modra <amodra@gmail.com>
758 * m32c-ibld.c: Regenerate.
760 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
762 * bpf-opc.c: Regenerate.
764 2020-01-30 Jan Beulich <jbeulich@suse.com>
766 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
767 (dis386): Use them to replace C2/C3 table entries.
768 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
769 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
770 ones. Use Size64 instead of DefaultSize on Intel64 ones.
771 * i386-tbl.h: Re-generate.
773 2020-01-30 Jan Beulich <jbeulich@suse.com>
775 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
777 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
779 * i386-tbl.h: Re-generate.
781 2020-01-30 Alan Modra <amodra@gmail.com>
783 * tic4x-dis.c (tic4x_dp): Make unsigned.
785 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
786 Jan Beulich <jbeulich@suse.com>
789 * i386-dis.c (MOVSXD_Fixup): New function.
790 (movsxd_mode): New enum.
791 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
792 (intel_operand_size): Handle movsxd_mode.
793 (OP_E_register): Likewise.
795 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
796 register on movsxd. Add movsxd with 16-bit destination register
797 for AMD64 and Intel64 ISAs.
798 * i386-tbl.h: Regenerated.
800 2020-01-27 Tamar Christina <tamar.christina@arm.com>
803 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
804 * aarch64-asm-2.c: Regenerate
805 * aarch64-dis-2.c: Likewise.
806 * aarch64-opc-2.c: Likewise.
808 2020-01-21 Jan Beulich <jbeulich@suse.com>
810 * i386-opc.tbl (sysret): Drop DefaultSize.
811 * i386-tbl.h: Re-generate.
813 2020-01-21 Jan Beulich <jbeulich@suse.com>
815 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
817 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
818 * i386-tbl.h: Re-generate.
820 2020-01-20 Nick Clifton <nickc@redhat.com>
822 * po/de.po: Updated German translation.
823 * po/pt_BR.po: Updated Brazilian Portuguese translation.
824 * po/uk.po: Updated Ukranian translation.
826 2020-01-20 Alan Modra <amodra@gmail.com>
828 * hppa-dis.c (fput_const): Remove useless cast.
830 2020-01-20 Alan Modra <amodra@gmail.com>
832 * arm-dis.c (print_insn_arm): Wrap 'T' value.
834 2020-01-18 Nick Clifton <nickc@redhat.com>
836 * configure: Regenerate.
837 * po/opcodes.pot: Regenerate.
839 2020-01-18 Nick Clifton <nickc@redhat.com>
841 Binutils 2.34 branch created.
843 2020-01-17 Christian Biesinger <cbiesinger@google.com>
845 * opintl.h: Fix spelling error (seperate).
847 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
849 * i386-opc.tbl: Add {vex} pseudo prefix.
850 * i386-tbl.h: Regenerated.
852 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
855 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
856 (neon_opcodes): Likewise.
857 (select_arm_features): Make sure we enable MVE bits when selecting
858 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
861 2020-01-16 Jan Beulich <jbeulich@suse.com>
863 * i386-opc.tbl: Drop stale comment from XOP section.
865 2020-01-16 Jan Beulich <jbeulich@suse.com>
867 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
868 (extractps): Add VexWIG to SSE2AVX forms.
869 * i386-tbl.h: Re-generate.
871 2020-01-16 Jan Beulich <jbeulich@suse.com>
873 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
874 Size64 from and use VexW1 on SSE2AVX forms.
875 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
876 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
877 * i386-tbl.h: Re-generate.
879 2020-01-15 Alan Modra <amodra@gmail.com>
881 * tic4x-dis.c (tic4x_version): Make unsigned long.
882 (optab, optab_special, registernames): New file scope vars.
883 (tic4x_print_register): Set up registernames rather than
884 malloc'd registertable.
885 (tic4x_disassemble): Delete optable and optable_special. Use
886 optab and optab_special instead. Throw away old optab,
887 optab_special and registernames when info->mach changes.
889 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
892 * z80-dis.c (suffix): Use .db instruction to generate double
895 2020-01-14 Alan Modra <amodra@gmail.com>
897 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
898 values to unsigned before shifting.
900 2020-01-13 Thomas Troeger <tstroege@gmx.de>
902 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
904 (print_insn_thumb16, print_insn_thumb32): Likewise.
905 (print_insn): Initialize the insn info.
906 * i386-dis.c (print_insn): Initialize the insn info fields, and
909 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
911 * arc-opc.c (C_NE): Make it required.
913 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
915 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
916 reserved register name.
918 2020-01-13 Alan Modra <amodra@gmail.com>
920 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
921 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
923 2020-01-13 Alan Modra <amodra@gmail.com>
925 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
926 result of wasm_read_leb128 in a uint64_t and check that bits
927 are not lost when copying to other locals. Use uint32_t for
928 most locals. Use PRId64 when printing int64_t.
930 2020-01-13 Alan Modra <amodra@gmail.com>
932 * score-dis.c: Formatting.
933 * score7-dis.c: Formatting.
935 2020-01-13 Alan Modra <amodra@gmail.com>
937 * score-dis.c (print_insn_score48): Use unsigned variables for
938 unsigned values. Don't left shift negative values.
939 (print_insn_score32): Likewise.
940 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
942 2020-01-13 Alan Modra <amodra@gmail.com>
944 * tic4x-dis.c (tic4x_print_register): Remove dead code.
946 2020-01-13 Alan Modra <amodra@gmail.com>
948 * fr30-ibld.c: Regenerate.
950 2020-01-13 Alan Modra <amodra@gmail.com>
952 * xgate-dis.c (print_insn): Don't left shift signed value.
953 (ripBits): Formatting, use 1u.
955 2020-01-10 Alan Modra <amodra@gmail.com>
957 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
958 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
960 2020-01-10 Alan Modra <amodra@gmail.com>
962 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
963 and XRREG value earlier to avoid a shift with negative exponent.
964 * m10200-dis.c (disassemble): Similarly.
966 2020-01-09 Nick Clifton <nickc@redhat.com>
969 * z80-dis.c (ld_ii_ii): Use correct cast.
971 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
974 * z80-dis.c (ld_ii_ii): Use character constant when checking
977 2020-01-09 Jan Beulich <jbeulich@suse.com>
979 * i386-dis.c (SEP_Fixup): New.
981 (dis386_twobyte): Use it for sysenter/sysexit.
982 (enum x86_64_isa): Change amd64 enumerator to value 1.
983 (OP_J): Compare isa64 against intel64 instead of amd64.
984 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
986 * i386-tbl.h: Re-generate.
988 2020-01-08 Alan Modra <amodra@gmail.com>
990 * z8k-dis.c: Include libiberty.h
991 (instr_data_s): Make max_fetched unsigned.
992 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
993 Don't exceed byte_info bounds.
994 (output_instr): Make num_bytes unsigned.
995 (unpack_instr): Likewise for nibl_count and loop.
996 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
998 * z8k-opc.h: Regenerate.
1000 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1002 * arc-tbl.h (llock): Use 'LLOCK' as class.
1004 (scond): Use 'SCOND' as class.
1006 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1009 2020-01-06 Alan Modra <amodra@gmail.com>
1011 * m32c-ibld.c: Regenerate.
1013 2020-01-06 Alan Modra <amodra@gmail.com>
1016 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1017 Peek at next byte to prevent recursion on repeated prefix bytes.
1018 Ensure uninitialised "mybuf" is not accessed.
1019 (print_insn_z80): Don't zero n_fetch and n_used here,..
1020 (print_insn_z80_buf): ..do it here instead.
1022 2020-01-04 Alan Modra <amodra@gmail.com>
1024 * m32r-ibld.c: Regenerate.
1026 2020-01-04 Alan Modra <amodra@gmail.com>
1028 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1030 2020-01-04 Alan Modra <amodra@gmail.com>
1032 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1034 2020-01-04 Alan Modra <amodra@gmail.com>
1036 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1038 2020-01-03 Jan Beulich <jbeulich@suse.com>
1040 * aarch64-tbl.h (aarch64_opcode_table): Use
1041 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1043 2020-01-03 Jan Beulich <jbeulich@suse.com>
1045 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1046 forms of SUDOT and USDOT.
1048 2020-01-03 Jan Beulich <jbeulich@suse.com>
1050 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1052 * opcodes/aarch64-dis-2.c: Re-generate.
1054 2020-01-03 Jan Beulich <jbeulich@suse.com>
1056 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1058 * opcodes/aarch64-dis-2.c: Re-generate.
1060 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1062 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1064 2020-01-01 Alan Modra <amodra@gmail.com>
1066 Update year range in copyright notice of all files.
1068 For older changes see ChangeLog-2019
1070 Copyright (C) 2020 Free Software Foundation, Inc.
1072 Copying and distribution of this file, with or without modification,
1073 are permitted in any medium without royalty provided the copyright
1074 notice and this notice are preserved.
1080 version-control: never