opcodes/ChangeLog

   1 2019-10-29  Nick Clifton  <nickc@redhat.com>
   2
   3         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
   4         values.
   5         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
   6         (print_insn_s12z):  Check for illegal size values.
   7
   8 2019-10-28  Nick Clifton  <nickc@redhat.com>
   9
  10         * csky-dis.c (csky_chars_to_number): Check for a negative
  11         count. Use an unsigned integer to construct the return value.
  12
  13 2019-10-28  Nick Clifton  <nickc@redhat.com>
  14
  15         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
  16         operand buffer.  Set value to 15 not 13.
  17         (get_register_operand): Use OPERAND_BUFFER_LEN.
  18         (get_indirect_operand): Likewise.
  19         (print_two_operand): Likewise.
  20         (print_three_operand): Likewise.
  21         (print_oar_insn): Likewise.
  22
  23 2019-10-28  Nick Clifton  <nickc@redhat.com>
  24
  25         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
  26         (bit_extract_simple): Likewise.
  27         (bit_copy): Likewise.
  28         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
  29         index_offset array are not accessed.
  30
  31 2019-10-28  Nick Clifton  <nickc@redhat.com>
  32
  33         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
  34         operand.
  35
  36 2019-10-25  Nick Clifton  <nickc@redhat.com>
  37
  38         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
  39         access to opcodes.op array element.
  40
  41 2019-10-23  Nick Clifton  <nickc@redhat.com>
  42
  43         * rx-dis.c (get_register_name): Fix spelling typo in error
  44         message.
  45         (get_condition_name, get_flag_name, get_double_register_name)
  46         (get_double_register_high_name, get_double_register_low_name)
  47         (get_double_control_register_name, get_double_condition_name)
  48         (get_opsize_name, get_size_name): Likewise.
  49
  50 2019-10-22  Nick Clifton  <nickc@redhat.com>
  51
  52         * rx-dis.c (get_size_name): New function.  Provides safe
  53         access to name array.
  54         (get_opsize_name): Likewise.
  55         (print_insn_rx): Use the accessor functions.
  56
  57 2019-10-16  Nick Clifton  <nickc@redhat.com>
  58
  59         * rx-dis.c (get_register_name): New function.  Provides safe
  60         access to name array.
  61         (get_condition_name, get_flag_name, get_double_register_name)
  62         (get_double_register_high_name, get_double_register_low_name)
  63         (get_double_control_register_name, get_double_condition_name):
  64         Likewise.
  65         (print_insn_rx): Use the accessor functions.
  66
  67 2019-10-09  Nick Clifton  <nickc@redhat.com>
  68
  69         PR 25041
  70         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
  71         instructions.
  72
  73 2019-10-07  Jan Beulich  <jbeulich@suse.com>
  74
  75         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
  76         (cmpsd): Likewise. Move EsSeg to other operand.
  77         * opcodes/i386-tbl.h: Re-generate.
  78
  79 2019-09-23  Alan Modra  <amodra@gmail.com>
  80
  81         * m68k-dis.c: Include cpu-m68k.h
  82
  83 2019-09-23  Alan Modra  <amodra@gmail.com>
  84
  85         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
  86         "elf/mips.h" earlier.
  87
  88 2018-09-20  Jan Beulich  <jbeulich@suse.com>
  89
  90         PR gas/25012
  91         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
  92         with SReg operand.
  93         * i386-tbl.h: Re-generate.
  94
  95 2019-09-18  Alan Modra  <amodra@gmail.com>
  96
  97         * arc-ext.c: Update throughout for bfd section macro changes.
  98
  99 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 100
 101         * Makefile.in: Re-generate.
 102         * configure: Re-generate.
 103
 104 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 105
 106         * riscv-opc.c (riscv_opcodes): Change subset field
 107         to insn_class field for all instructions.
 108         (riscv_insn_types): Likewise.
 109
 110 2019-09-16  Phil Blundell  <pb@pbcl.net>
 111
 112         * configure: Regenerated.
 113
 114 2019-09-10  Miod Vallat  <miod@online.fr>
 115
 116         PR 24982
 117         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 118
 119 2019-09-09  Phil Blundell  <pb@pbcl.net>
 120
 121         binutils 2.33 branch created.
 122
 123 2019-09-03  Nick Clifton  <nickc@redhat.com>
 124
 125         PR 24961
 126         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 127         greater than zero before indexing via (bufcnt -1).
 128
 129 2019-09-03  Nick Clifton  <nickc@redhat.com>
 130
 131         PR 24958
 132         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 133         (MAX_SPEC_REG_NAME_LEN): Define.
 134         (struct mmix_dis_info): Use defined constants for array lengths.
 135         (get_reg_name): New function.
 136         (get_sprec_reg_name): New function.
 137         (print_insn_mmix): Use new functions.
 138
 139 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 140
 141         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 142         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 143         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 144
 145 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 146
 147         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 148         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 149         (aarch64_sys_reg_supported_p): Update checks for the above.
 150
 151 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 152
 153         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 154         cases MVE_SQRSHRL and MVE_UQRSHLL.
 155         (print_insn_mve): Add case for specifier 'k' to check
 156         specific bit of the instruction.
 157
 158 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 159
 160         PR 24854
 161         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 162         encountering an unknown machine type.
 163         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 164         cases return -1 rather than calling abort.
 165
 166 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 169         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 170         IgnoreSize.
 171         * i386-tbl.h: Re-generate.
 172
 173 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 174
 175         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 176         instructions.
 177
 178 2019-07-30  Mel Chen <mel.chen@sifive.com>
 179
 180         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 181         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 182
 183         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 184         fscsr.
 185
 186 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 187
 188         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 189         and MPY class instructions.
 190         (parse_option): Add nps400 option.
 191         (print_arc_disassembler_options): Add nps400 info.
 192
 193 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 194
 195         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 196         (bspop): Likewise.
 197         (modapp): Likewise.
 198         * arc-opc.c (RAD_CHK): Add.
 199         * arc-tbl.h: Regenerate.
 200
 201 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 202
 203         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 204         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 205
 206 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 207
 208         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 209         instructions as UNPREDICTABLE.
 210
 211 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 212
 213         * bpf-desc.c: Regenerated.
 214
 215 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 216
 217         * i386-gen.c (static_assert): Define.
 218         (main): Use it.
 219         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 220         (Opcode_Modifier_Num): ... this.
 221         (Mem): Delete.
 222
 223 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-gen.c (operand_types): Move RegMem ...
 226         (opcode_modifiers): ... here.
 227         * i386-opc.h (RegMem): Move to opcode modifer enum.
 228         (union i386_operand_type): Move regmem field ...
 229         (struct i386_opcode_modifier): ... here.
 230         * i386-opc.tbl (RegMem): Define.
 231         (mov, movq): Move RegMem on segment, control, debug, and test
 232         register flavors.
 233         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 234         to non-SSE2AVX flavor.
 235         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 236         Move RegMem on register only flavors. Drop IgnoreSize from
 237         legacy encoding flavors.
 238         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 239         flavors.
 240         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 241         register only flavors.
 242         (vmovd): Move RegMem and drop IgnoreSize on register only
 243         flavor. Change opcode and operand order to store form.
 244         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 245
 246 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 249         entries.
 250         * i386-opc.h (SReg2, SReg3): Replace by ...
 251         (SReg): ... this.
 252         (union i386_operand_type): Replace sreg fields.
 253         * i386-opc.tbl (mov, ): Use SReg.
 254         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 255         register flavors.
 256         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 257         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 258
 259 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 260
 261         * bpf-desc.c: Regenerate.
 262         * bpf-opc.c: Likewise.
 263         * bpf-opc.h: Likewise.
 264
 265 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 266
 267         * bpf-desc.c: Regenerate.
 268         * bpf-opc.c: Likewise.
 269
 270 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 271
 272         * arm-dis.c (print_insn_coprocessor): Rename index to
 273         index_operand.
 274
 275 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 276
 277         * riscv-opc.c (riscv_insn_types): Add r4 type.
 278
 279         * riscv-opc.c (riscv_insn_types): Add b and j type.
 280
 281         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 282         format for sb type and correct s type.
 283
 284 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 285
 286         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 287         SVE FMOV alias of FCPY.
 288
 289 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 290
 291         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 292         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 293
 294 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 295
 296         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 297         registers in an instruction prefixed by MOVPRFX.
 298
 299 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 300
 301         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 302         sve_size_13 icode to account for variant behaviour of
 303         pmull{t,b}.
 304         * aarch64-dis-2.c: Regenerate.
 305         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 306         sve_size_13 icode to account for variant behaviour of
 307         pmull{t,b}.
 308         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 309         (OP_SVE_VVV_Q_D): Add new qualifier.
 310         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 311         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 312         AES and those not.
 313
 314 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 315
 316         * opcodes/i386-gen.c (operand_type_init): Remove
 317         OPERAND_TYPE_VEC_IMM4 entry.
 318         (operand_types): Remove Vec_Imm4.
 319         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 320         (union i386_operand_type): Remove vec_imm4.
 321         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 322         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 323
 324 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 325
 326         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 327         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 328         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 329         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 330         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 331         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 332         * i386-tbl.h: Re-generate.
 333
 334 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 337         register operands.
 338         * i386-tbl.h: Re-generate.
 339
 340 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 341
 342         * i386-opc.tbl (C): New.
 343         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 344         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 345         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 346         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 347         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 348         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 349         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 350         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 351         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 352         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 353         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 354         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 355         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 356         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 357         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 358         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 359         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 360         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 361         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 362         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 363         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 364         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 365         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 366         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 367         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 368         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 369         flavors.
 370         * i386-tbl.h: Re-generate.
 371
 372 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 373
 374         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 375         register operands.
 376         * i386-tbl.h: Re-generate.
 377
 378 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 379
 380         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 381         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 382         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 383         * i386-tbl.h: Re-generate.
 384
 385 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 388         Disp8MemShift from register only templates.
 389         * i386-tbl.h: Re-generate.
 390
 391 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 392
 393         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 394         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 395         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 396         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 397         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 398         EVEX_W_0F11_P_3_M_1): Delete.
 399         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 400         EVEX_W_0F11_P_3): New.
 401         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 402         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 403         MOD_EVEX_0F11_PREFIX_3 table entries.
 404         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 405         PREFIX_EVEX_0F11 table entries.
 406         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 407         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 408         EVEX_W_0F11_P_3_M_{0,1} table entries.
 409
 410 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 411
 412         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 413         Delete.
 414
 415 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 416
 417         PR binutils/24719
 418         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 419         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 420         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 421         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 422         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 423         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 424         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 425         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 426         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 427         PREFIX_EVEX_0F38C6_REG_6 entries.
 428         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 429         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 430         EVEX_W_0F38C7_R_6_P_2 entries.
 431         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 432         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 433         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 434         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 435         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 436         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 437         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 438
 439 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 440
 441         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 442         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 443         VEX_LEN_0F2D_P_3): Delete.
 444         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 445         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 446         (prefix_table): ... here.
 447
 448 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 449
 450         * i386-dis.c (Iq): Delete.
 451         (Id): New.
 452         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 453         TBM insns.
 454         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 455         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 456         (OP_E_memory): Also honor needindex when deciding whether an
 457         address size prefix needs printing.
 458         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 459
 460 2019-06-26  Jim Wilson  <jimw@sifive.com>
 461
 462         PR binutils/24739
 463         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 464         Set info->display_endian to info->endian_code.
 465
 466 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 467
 468         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 469         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 470         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 471         OPERAND_TYPE_ACC64 entries.
 472         * i386-init.h: Re-generate.
 473
 474 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 477         Delete.
 478         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 479         of dqa_mode.
 480         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 481         entries here.
 482         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 483         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 484
 485 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 488         variables.
 489
 490 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 491
 492         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 493         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 494         movnti.
 495         * i386-opc.tbl (movnti): Add IgnoreSize.
 496         * i386-tbl.h: Re-generate.
 497
 498 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 501         * i386-tbl.h: Re-generate.
 502
 503 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 504
 505         * i386-dis-evex.h: Break into ...
 506         * i386-dis-evex-len.h: New file.
 507         * i386-dis-evex-mod.h: Likewise.
 508         * i386-dis-evex-prefix.h: Likewise.
 509         * i386-dis-evex-reg.h: Likewise.
 510         * i386-dis-evex-w.h: Likewise.
 511         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 512         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 513         i386-dis-evex-mod.h.
 514
 515 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 516
 517         PR binutils/24700
 518         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 519         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 520         EVEX_W_0F385B_P_2.
 521         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 522         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 523         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 524         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 525         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 526         EVEX_LEN_0F385B_P_2_W_1.
 527         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 528         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 529         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 530         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 531         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 532         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 533         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 534         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 535         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 536         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 537
 538 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 539
 540         PR binutils/24691
 541         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 542         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 543         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 544         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 545         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 546         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 547         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 548         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 549         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 550         EVEX_LEN_0F3A43_P_2_W_1.
 551         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 552         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 553         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 554         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 555         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 556         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 557         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 558         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 559         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 560         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 561         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 562         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 563
 564 2019-06-14  Nick Clifton  <nickc@redhat.com>
 565
 566         * po/fr.po; Updated French translation.
 567
 568 2019-06-13  Stafford Horne  <shorne@gmail.com>
 569
 570         * or1k-asm.c: Regenerated.
 571         * or1k-desc.c: Regenerated.
 572         * or1k-desc.h: Regenerated.
 573         * or1k-dis.c: Regenerated.
 574         * or1k-ibld.c: Regenerated.
 575         * or1k-opc.c: Regenerated.
 576         * or1k-opc.h: Regenerated.
 577         * or1k-opinst.c: Regenerated.
 578
 579 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 580
 581         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 582
 583 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 584
 585         PR binutils/24633
 586         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 587         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 588         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 589         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 590         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 591         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 592         EVEX_LEN_0F3A1B_P_2_W_1.
 593         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 594         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 595         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 596         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 597         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 598         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 599         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 600         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 601
 602 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 603
 604         PR binutils/24626
 605         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 606         EVEX.vvvv when disassembling VEX and EVEX instructions.
 607         (OP_VEX): Set vex.register_specifier to 0 after readding
 608         vex.register_specifier.
 609         (OP_Vex_2src_1): Likewise.
 610         (OP_Vex_2src_2): Likewise.
 611         (OP_LWP_E): Likewise.
 612         (OP_EX_Vex): Don't check vex.register_specifier.
 613         (OP_XMM_Vex): Likewise.
 614
 615 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 616             Lili Cui  <lili.cui@intel.com>
 617
 618         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 619         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 620         instructions.
 621         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 622         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 623         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 624         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 625         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 626         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 627         * i386-init.h: Regenerated.
 628         * i386-tbl.h: Likewise.
 629
 630 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 631             Lili Cui  <lili.cui@intel.com>
 632
 633         * doc/c-i386.texi: Document enqcmd.
 634         * testsuite/gas/i386/enqcmd-intel.d: New file.
 635         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 636         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 637         * testsuite/gas/i386/enqcmd.d: Likewise.
 638         * testsuite/gas/i386/enqcmd.s: Likewise.
 639         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 640         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 641         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 642         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 643         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 644         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 645         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 646         and x86-64-enqcmd.
 647
 648 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 649
 650         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 651
 652 2019-06-03  Alan Modra  <amodra@gmail.com>
 653
 654         * ppc-dis.c (prefix_opcd_indices): Correct size.
 655
 656 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 657
 658         PR gas/24625
 659         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 660         Disp8ShiftVL.
 661         * i386-tbl.h: Regenerated.
 662
 663 2019-05-24  Alan Modra  <amodra@gmail.com>
 664
 665         * po/POTFILES.in: Regenerate.
 666
 667 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 668             Alan Modra  <amodra@gmail.com>
 669
 670         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 671         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 672         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 673         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 674         XTOP>): Define and add entries.
 675         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 676         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 677         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 678         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 679
 680 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 681             Alan Modra  <amodra@gmail.com>
 682
 683         * ppc-dis.c (ppc_opts): Add "future" entry.
 684         (PREFIX_OPCD_SEGS): Define.
 685         (prefix_opcd_indices): New array.
 686         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 687         (lookup_prefix): New function.
 688         (print_insn_powerpc): Handle 64-bit prefix instructions.
 689         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 690         (PMRR, POWERXX): Define.
 691         (prefix_opcodes): New instruction table.
 692         (prefix_num_opcodes): New constant.
 693
 694 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 695
 696         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 697         * configure: Regenerated.
 698         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 699         and cpu/bpf.opc.
 700         (HFILES): Add bpf-desc.h and bpf-opc.h.
 701         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 702         bpf-ibld.c and bpf-opc.c.
 703         (BPF_DEPS): Define.
 704         * Makefile.in: Regenerated.
 705         * disassemble.c (ARCH_bpf): Define.
 706         (disassembler): Add case for bfd_arch_bpf.
 707         (disassemble_init_for_target): Likewise.
 708         (enum epbf_isa_attr): Define.
 709         * disassemble.h: extern print_insn_bpf.
 710         * bpf-asm.c: Generated.
 711         * bpf-opc.h: Likewise.
 712         * bpf-opc.c: Likewise.
 713         * bpf-ibld.c: Likewise.
 714         * bpf-dis.c: Likewise.
 715         * bpf-desc.h: Likewise.
 716         * bpf-desc.c: Likewise.
 717
 718 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 719
 720         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 721         and VMSR with the new operands.
 722
 723 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 724
 725         * arm-dis.c (enum mve_instructions): New enum
 726         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 727         and cneg.
 728         (mve_opcodes): New instructions as above.
 729         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 730         csneg and csel.
 731         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 732
 733 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 734
 735         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 736         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 737         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 738         uqshl, urshrl and urshr.
 739         (is_mve_okay_in_it): Add new instructions to TRUE list.
 740         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 741         (print_insn_mve): Updated to accept new %j,
 742         %<bitfield>m and %<bitfield>n patterns.
 743
 744 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 745
 746         * mips-opc.c (mips_builtin_opcodes): Change source register
 747         constraint for DAUI.
 748
 749 2019-05-20  Nick Clifton  <nickc@redhat.com>
 750
 751         * po/fr.po: Updated French translation.
 752
 753 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 754             Michael Collison <michael.collison@arm.com>
 755
 756         * arm-dis.c (thumb32_opcodes): Add new instructions.
 757         (enum mve_instructions): Likewise.
 758         (enum mve_undefined): Add new reasons.
 759         (is_mve_encoding_conflict): Handle new instructions.
 760         (is_mve_undefined): Likewise.
 761         (is_mve_unpredictable): Likewise.
 762         (print_mve_undefined): Likewise.
 763         (print_mve_size): Likewise.
 764
 765 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 766             Michael Collison <michael.collison@arm.com>
 767
 768         * arm-dis.c (thumb32_opcodes): Add new instructions.
 769         (enum mve_instructions): Likewise.
 770         (is_mve_encoding_conflict): Handle new instructions.
 771         (is_mve_undefined): Likewise.
 772         (is_mve_unpredictable): Likewise.
 773         (print_mve_size): Likewise.
 774
 775 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 776             Michael Collison <michael.collison@arm.com>
 777
 778         * arm-dis.c (thumb32_opcodes): Add new instructions.
 779         (enum mve_instructions): Likewise.
 780         (is_mve_encoding_conflict): Likewise.
 781         (is_mve_unpredictable): Likewise.
 782         (print_mve_size): Likewise.
 783
 784 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 785             Michael Collison <michael.collison@arm.com>
 786
 787         * arm-dis.c (thumb32_opcodes): Add new instructions.
 788         (enum mve_instructions): Likewise.
 789         (is_mve_encoding_conflict): Handle new instructions.
 790         (is_mve_undefined): Likewise.
 791         (is_mve_unpredictable): Likewise.
 792         (print_mve_size): Likewise.
 793
 794 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 795             Michael Collison <michael.collison@arm.com>
 796
 797         * arm-dis.c (thumb32_opcodes): Add new instructions.
 798         (enum mve_instructions): Likewise.
 799         (is_mve_encoding_conflict): Handle new instructions.
 800         (is_mve_undefined): Likewise.
 801         (is_mve_unpredictable): Likewise.
 802         (print_mve_size): Likewise.
 803         (print_insn_mve): Likewise.
 804
 805 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 806             Michael Collison <michael.collison@arm.com>
 807
 808         * arm-dis.c (thumb32_opcodes): Add new instructions.
 809         (print_insn_thumb32): Handle new instructions.
 810
 811 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 812             Michael Collison <michael.collison@arm.com>
 813
 814         * arm-dis.c (enum mve_instructions): Add new instructions.
 815         (enum mve_undefined): Add new reasons.
 816         (is_mve_encoding_conflict): Handle new instructions.
 817         (is_mve_undefined): Likewise.
 818         (is_mve_unpredictable): Likewise.
 819         (print_mve_undefined): Likewise.
 820         (print_mve_size): Likewise.
 821         (print_mve_shift_n): Likewise.
 822         (print_insn_mve): Likewise.
 823
 824 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 825             Michael Collison <michael.collison@arm.com>
 826
 827         * arm-dis.c (enum mve_instructions): Add new instructions.
 828         (is_mve_encoding_conflict): Handle new instructions.
 829         (is_mve_unpredictable): Likewise.
 830         (print_mve_rotate): Likewise.
 831         (print_mve_size): Likewise.
 832         (print_insn_mve): Likewise.
 833
 834 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 835             Michael Collison <michael.collison@arm.com>
 836
 837         * arm-dis.c (enum mve_instructions): Add new instructions.
 838         (is_mve_encoding_conflict): Handle new instructions.
 839         (is_mve_unpredictable): Likewise.
 840         (print_mve_size): Likewise.
 841         (print_insn_mve): Likewise.
 842
 843 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 844             Michael Collison <michael.collison@arm.com>
 845
 846         * arm-dis.c (enum mve_instructions): Add new instructions.
 847         (enum mve_undefined): Add new reasons.
 848         (is_mve_encoding_conflict): Handle new instructions.
 849         (is_mve_undefined): Likewise.
 850         (is_mve_unpredictable): Likewise.
 851         (print_mve_undefined): Likewise.
 852         (print_mve_size): Likewise.
 853         (print_insn_mve): Likewise.
 854
 855 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 856             Michael Collison <michael.collison@arm.com>
 857
 858         * arm-dis.c (enum mve_instructions): Add new instructions.
 859         (is_mve_encoding_conflict): Handle new instructions.
 860         (is_mve_undefined): Likewise.
 861         (is_mve_unpredictable): Likewise.
 862         (print_mve_size): Likewise.
 863         (print_insn_mve): Likewise.
 864
 865 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 866             Michael Collison <michael.collison@arm.com>
 867
 868         * arm-dis.c (enum mve_instructions): Add new instructions.
 869         (enum mve_unpredictable): Add new reasons.
 870         (enum mve_undefined): Likewise.
 871         (is_mve_okay_in_it): Handle new isntructions.
 872         (is_mve_encoding_conflict): Likewise.
 873         (is_mve_undefined): Likewise.
 874         (is_mve_unpredictable): Likewise.
 875         (print_mve_vmov_index): Likewise.
 876         (print_simd_imm8): Likewise.
 877         (print_mve_undefined): Likewise.
 878         (print_mve_unpredictable): Likewise.
 879         (print_mve_size): Likewise.
 880         (print_insn_mve): Likewise.
 881
 882 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 883             Michael Collison <michael.collison@arm.com>
 884
 885         * arm-dis.c (enum mve_instructions): Add new instructions.
 886         (enum mve_unpredictable): Add new reasons.
 887         (enum mve_undefined): Likewise.
 888         (is_mve_encoding_conflict): Handle new instructions.
 889         (is_mve_undefined): Likewise.
 890         (is_mve_unpredictable): Likewise.
 891         (print_mve_undefined): Likewise.
 892         (print_mve_unpredictable): Likewise.
 893         (print_mve_rounding_mode): Likewise.
 894         (print_mve_vcvt_size): Likewise.
 895         (print_mve_size): Likewise.
 896         (print_insn_mve): Likewise.
 897
 898 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 899             Michael Collison <michael.collison@arm.com>
 900
 901         * arm-dis.c (enum mve_instructions): Add new instructions.
 902         (enum mve_unpredictable): Add new reasons.
 903         (enum mve_undefined): Likewise.
 904         (is_mve_undefined): Handle new instructions.
 905         (is_mve_unpredictable): Likewise.
 906         (print_mve_undefined): Likewise.
 907         (print_mve_unpredictable): Likewise.
 908         (print_mve_size): Likewise.
 909         (print_insn_mve): Likewise.
 910
 911 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 912             Michael Collison <michael.collison@arm.com>
 913
 914         * arm-dis.c (enum mve_instructions): Add new instructions.
 915         (enum mve_undefined): Add new reasons.
 916         (insns): Add new instructions.
 917         (is_mve_encoding_conflict):
 918         (print_mve_vld_str_addr): New print function.
 919         (is_mve_undefined): Handle new instructions.
 920         (is_mve_unpredictable): Likewise.
 921         (print_mve_undefined): Likewise.
 922         (print_mve_size): Likewise.
 923         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 924         (print_insn_mve):  Handle new operands.
 925
 926 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 927             Michael Collison <michael.collison@arm.com>
 928
 929         * arm-dis.c (enum mve_instructions): Add new instructions.
 930         (enum mve_unpredictable): Add new reasons.
 931         (is_mve_encoding_conflict): Handle new instructions.
 932         (is_mve_unpredictable): Likewise.
 933         (mve_opcodes): Add new instructions.
 934         (print_mve_unpredictable): Handle new reasons.
 935         (print_mve_register_blocks): New print function.
 936         (print_mve_size): Handle new instructions.
 937         (print_insn_mve): Likewise.
 938
 939 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 940             Michael Collison <michael.collison@arm.com>
 941
 942         * arm-dis.c (enum mve_instructions): Add new instructions.
 943         (enum mve_unpredictable): Add new reasons.
 944         (enum mve_undefined): Likewise.
 945         (is_mve_encoding_conflict): Handle new instructions.
 946         (is_mve_undefined): Likewise.
 947         (is_mve_unpredictable): Likewise.
 948         (coprocessor_opcodes): Move NEON VDUP from here...
 949         (neon_opcodes): ... to here.
 950         (mve_opcodes): Add new instructions.
 951         (print_mve_undefined):  Handle new reasons.
 952         (print_mve_unpredictable): Likewise.
 953         (print_mve_size): Handle new instructions.
 954         (print_insn_neon): Handle vdup.
 955         (print_insn_mve): Handle new operands.
 956
 957 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 958             Michael Collison <michael.collison@arm.com>
 959
 960         * arm-dis.c (enum mve_instructions): Add new instructions.
 961         (enum mve_unpredictable): Add new values.
 962         (mve_opcodes): Add new instructions.
 963         (vec_condnames): New array with vector conditions.
 964         (mve_predicatenames): New array with predicate suffixes.
 965         (mve_vec_sizename): New array with vector sizes.
 966         (enum vpt_pred_state): New enum with vector predication states.
 967         (struct vpt_block): New struct type for vpt blocks.
 968         (vpt_block_state): Global struct to keep track of state.
 969         (mve_extract_pred_mask): New helper function.
 970         (num_instructions_vpt_block): Likewise.
 971         (mark_outside_vpt_block): Likewise.
 972         (mark_inside_vpt_block): Likewise.
 973         (invert_next_predicate_state): Likewise.
 974         (update_next_predicate_state): Likewise.
 975         (update_vpt_block_state): Likewise.
 976         (is_vpt_instruction): Likewise.
 977         (is_mve_encoding_conflict): Add entries for new instructions.
 978         (is_mve_unpredictable): Likewise.
 979         (print_mve_unpredictable): Handle new cases.
 980         (print_instruction_predicate): Likewise.
 981         (print_mve_size): New function.
 982         (print_vec_condition): New function.
 983         (print_insn_mve): Handle vpt blocks and new print operands.
 984
 985 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 986
 987         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 988         8, 14 and 15 for Armv8.1-M Mainline.
 989
 990 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 991             Michael Collison <michael.collison@arm.com>
 992
 993         * arm-dis.c (enum mve_instructions): New enum.
 994         (enum mve_unpredictable): Likewise.
 995         (enum mve_undefined): Likewise.
 996         (struct mopcode32): New struct.
 997         (is_mve_okay_in_it): New function.
 998         (is_mve_architecture): Likewise.
 999         (arm_decode_field): Likewise.
1000         (arm_decode_field_multiple): Likewise.
1001         (is_mve_encoding_conflict): Likewise.
1002         (is_mve_undefined): Likewise.
1003         (is_mve_unpredictable): Likewise.
1004         (print_mve_undefined): Likewise.
1005         (print_mve_unpredictable): Likewise.
1006         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1007         (print_insn_mve): New function.
1008         (print_insn_thumb32): Handle MVE architecture.
1009         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1010
1011 2019-05-10  Nick Clifton  <nickc@redhat.com>
1012
1013         PR 24538
1014         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1015         end of the table prematurely.
1016
1017 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1018
1019         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1020         macros for R6.
1021
1022 2019-05-11  Alan Modra  <amodra@gmail.com>
1023
1024         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1025         when -Mraw is in effect.
1026
1027 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1028
1029         * aarch64-dis-2.c: Regenerate.
1030         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1031         (OP_SVE_BBB): New variant set.
1032         (OP_SVE_DDDD): New variant set.
1033         (OP_SVE_HHH): New variant set.
1034         (OP_SVE_HHHU): New variant set.
1035         (OP_SVE_SSS): New variant set.
1036         (OP_SVE_SSSU): New variant set.
1037         (OP_SVE_SHH): New variant set.
1038         (OP_SVE_SBBU): New variant set.
1039         (OP_SVE_DSS): New variant set.
1040         (OP_SVE_DHHU): New variant set.
1041         (OP_SVE_VMV_HSD_BHS): New variant set.
1042         (OP_SVE_VVU_HSD_BHS): New variant set.
1043         (OP_SVE_VVVU_SD_BH): New variant set.
1044         (OP_SVE_VVVU_BHSD): New variant set.
1045         (OP_SVE_VVV_QHD_DBS): New variant set.
1046         (OP_SVE_VVV_HSD_BHS): New variant set.
1047         (OP_SVE_VVV_HSD_BHS2): New variant set.
1048         (OP_SVE_VVV_BHS_HSD): New variant set.
1049         (OP_SVE_VV_BHS_HSD): New variant set.
1050         (OP_SVE_VVV_SD): New variant set.
1051         (OP_SVE_VVU_BHS_HSD): New variant set.
1052         (OP_SVE_VZVV_SD): New variant set.
1053         (OP_SVE_VZVV_BH): New variant set.
1054         (OP_SVE_VZV_SD): New variant set.
1055         (aarch64_opcode_table): Add sve2 instructions.
1056
1057 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1058
1059         * aarch64-asm-2.c: Regenerated.
1060         * aarch64-dis-2.c: Regenerated.
1061         * aarch64-opc-2.c: Regenerated.
1062         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1063         for SVE_SHLIMM_UNPRED_22.
1064         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1065         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1066         operand.
1067
1068 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1069
1070         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1071         sve_size_tsz_bhs iclass encode.
1072         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1073         sve_size_tsz_bhs iclass decode.
1074
1075 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1076
1077         * aarch64-asm-2.c: Regenerated.
1078         * aarch64-dis-2.c: Regenerated.
1079         * aarch64-opc-2.c: Regenerated.
1080         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1081         for SVE_Zm4_11_INDEX.
1082         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1083         (fields): Handle SVE_i2h field.
1084         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1085         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1086
1087 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1088
1089         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1090         sve_shift_tsz_bhsd iclass encode.
1091         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1092         sve_shift_tsz_bhsd iclass decode.
1093
1094 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1095
1096         * aarch64-asm-2.c: Regenerated.
1097         * aarch64-dis-2.c: Regenerated.
1098         * aarch64-opc-2.c: Regenerated.
1099         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1100         (aarch64_encode_variant_using_iclass): Handle
1101         sve_shift_tsz_hsd iclass encode.
1102         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1103         sve_shift_tsz_hsd iclass decode.
1104         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1105         for SVE_SHRIMM_UNPRED_22.
1106         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1107         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1108         operand.
1109
1110 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1111
1112         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1113         sve_size_013 iclass encode.
1114         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1115         sve_size_013 iclass decode.
1116
1117 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1118
1119         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1120         sve_size_bh iclass encode.
1121         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1122         sve_size_bh iclass decode.
1123
1124 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1125
1126         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1127         sve_size_sd2 iclass encode.
1128         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1129         sve_size_sd2 iclass decode.
1130         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1131         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1132
1133 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1134
1135         * aarch64-asm-2.c: Regenerated.
1136         * aarch64-dis-2.c: Regenerated.
1137         * aarch64-opc-2.c: Regenerated.
1138         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1139         for SVE_ADDR_ZX.
1140         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1141         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1142
1143 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1144
1145         * aarch64-asm-2.c: Regenerated.
1146         * aarch64-dis-2.c: Regenerated.
1147         * aarch64-opc-2.c: Regenerated.
1148         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1149         for SVE_Zm3_11_INDEX.
1150         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1151         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1152         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1153         fields.
1154         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1155
1156 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1157
1158         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1159         sve_size_hsd2 iclass encode.
1160         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1161         sve_size_hsd2 iclass decode.
1162         * aarch64-opc.c (fields): Handle SVE_size field.
1163         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1164
1165 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1166
1167         * aarch64-asm-2.c: Regenerated.
1168         * aarch64-dis-2.c: Regenerated.
1169         * aarch64-opc-2.c: Regenerated.
1170         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1171         for SVE_IMM_ROT3.
1172         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1173         (fields): Handle SVE_rot3 field.
1174         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1175         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1176
1177 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1178
1179         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1180         instructions.
1181
1182 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1183
1184         * aarch64-tbl.h
1185         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1186         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1187         aarch64_feature_sve2bitperm): New feature sets.
1188         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1189         for feature set addresses.
1190         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1191         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1192
1193 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1194             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1195
1196         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1197         argument and set ASE_EVA_R6 appropriately.
1198         (set_default_mips_dis_options): Pass ISA to above.
1199         (parse_mips_dis_option): Likewise.
1200         * mips-opc.c (EVAR6): New macro.
1201         (mips_builtin_opcodes): Add llwpe, scwpe.
1202
1203 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1204
1205         * aarch64-asm-2.c: Regenerated.
1206         * aarch64-dis-2.c: Regenerated.
1207         * aarch64-opc-2.c: Regenerated.
1208         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1209         AARCH64_OPND_TME_UIMM16.
1210         (aarch64_print_operand): Likewise.
1211         * aarch64-tbl.h (QL_IMM_NIL): New.
1212         (TME): New.
1213         (_TME_INSN): New.
1214         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1215
1216 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1217
1218         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1219
1220 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1221             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1222
1223         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1224
1225 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1226
1227         * s12z-opc.h: Add extern "C" bracketing to help
1228         users who wish to use this interface in c++ code.
1229
1230 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1231
1232         * s12z-opc.c (bm_decode): Handle bit map operations with the
1233         "reserved0" mode.
1234
1235 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1236
1237         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1238         specifier.  Add entries for VLDR and VSTR of system registers.
1239         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1240         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1241         of %J and %K format specifier.
1242
1243 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1244
1245         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1246         Add new entries for VSCCLRM instruction.
1247         (print_insn_coprocessor): Handle new %C format control code.
1248
1249 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1250
1251         * arm-dis.c (enum isa): New enum.
1252         (struct sopcode32): New structure.
1253         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1254         set isa field of all current entries to ANY.
1255         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1256         Only match an entry if its isa field allows the current mode.
1257
1258 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1259
1260         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1261         CLRM.
1262         (print_insn_thumb32): Add logic to print %n CLRM register list.
1263
1264 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1265
1266         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1267         and %Q patterns.
1268
1269 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1270
1271         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1272         (print_insn_thumb32): Edit the switch case for %Z.
1273
1274 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1275
1276         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1277
1278 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1279
1280         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1281
1282 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1283
1284         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1285
1286 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1287
1288         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1289         Arm register with r13 and r15 unpredictable.
1290         (thumb32_opcodes): New instructions for bfx and bflx.
1291
1292 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1293
1294         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1295
1296 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1297
1298         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1299
1300 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1301
1302         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1303
1304 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1305
1306         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1307
1308 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1309
1310         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1311         "optr". ("operator" is a reserved word in c++).
1312
1313 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1314
1315         * aarch64-opc.c (aarch64_print_operand): Add case for
1316         AARCH64_OPND_Rt_SP.
1317         (verify_constraints): Likewise.
1318         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1319         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1320         to accept Rt|SP as first operand.
1321         (AARCH64_OPERANDS): Add new Rt_SP.
1322         * aarch64-asm-2.c: Regenerated.
1323         * aarch64-dis-2.c: Regenerated.
1324         * aarch64-opc-2.c: Regenerated.
1325
1326 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1327
1328         * aarch64-asm-2.c: Regenerated.
1329         * aarch64-dis-2.c: Likewise.
1330         * aarch64-opc-2.c: Likewise.
1331         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1332
1333 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1334
1335         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1336
1337 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1338
1339         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1340         * i386-init.h: Regenerated.
1341
1342 2019-04-07  Alan Modra  <amodra@gmail.com>
1343
1344         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1345         op_separator to control printing of spaces, comma and parens
1346         rather than need_comma, need_paren and spaces vars.
1347
1348 2019-04-07  Alan Modra  <amodra@gmail.com>
1349
1350         PR 24421
1351         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1352         (print_insn_neon, print_insn_arm): Likewise.
1353
1354 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1355
1356         * i386-dis-evex.h (evex_table): Updated to support BF16
1357         instructions.
1358         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1359         and EVEX_W_0F3872_P_3.
1360         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1361         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1362         * i386-opc.h (enum): Add CpuAVX512_BF16.
1363         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1364         * i386-opc.tbl: Add AVX512 BF16 instructions.
1365         * i386-init.h: Regenerated.
1366         * i386-tbl.h: Likewise.
1367
1368 2019-04-05  Alan Modra  <amodra@gmail.com>
1369
1370         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1371         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1372         to favour printing of "-" branch hint when using the "y" bit.
1373         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1374
1375 2019-04-05  Alan Modra  <amodra@gmail.com>
1376
1377         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1378         opcode until first operand is output.
1379
1380 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1381
1382         PR gas/24349
1383         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1384         (valid_bo_post_v2): Add support for 'at' branch hints.
1385         (insert_bo): Only error on branch on ctr.
1386         (get_bo_hint_mask): New function.
1387         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1388         for inserting 'at' branch hints.
1389         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1390         for extracting 'at' branch hints.
1391         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1392         (BOE): Delete operand.
1393         (BOM, BOP): New operands.
1394         (RM): Update value.
1395         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1396         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1397         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1398         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1399         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1400         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1401         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1402         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1403         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1404         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1405         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1406         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1407         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1408         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1409         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1410         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1411         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1412         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1413         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1414         bttarl+>: New extended mnemonics.
1415
1416 2019-03-28  Alan Modra  <amodra@gmail.com>
1417
1418         PR 24390
1419         * ppc-opc.c (BTF): Define.
1420         (powerpc_opcodes): Use for mtfsb*.
1421         * ppc-dis.c (print_insn_powerpc): Print fields with both
1422         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1423
1424 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1425
1426         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1427         (mapping_symbol_for_insn): Implement new algorithm.
1428         (print_insn): Remove duplicate code.
1429
1430 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1431
1432         * aarch64-dis.c (print_insn_aarch64):
1433         Implement override.
1434
1435 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1436
1437         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1438         order.
1439
1440 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1441
1442         * aarch64-dis.c (last_stop_offset): New.
1443         (print_insn_aarch64): Use stop_offset.
1444
1445 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1446
1447         PR gas/24359
1448         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1449         CPU_ANY_AVX2_FLAGS.
1450         * i386-init.h: Regenerated.
1451
1452 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1453
1454         PR gas/24348
1455         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1456         vmovdqu16, vmovdqu32 and vmovdqu64.
1457         * i386-tbl.h: Regenerated.
1458
1459 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1460
1461         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1462         from vstrszb, vstrszh, and vstrszf.
1463
1464 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1465
1466         * s390-opc.txt: Add instruction descriptions.
1467
1468 2019-02-08  Jim Wilson  <jimw@sifive.com>
1469
1470         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1471         <bne>: Likewise.
1472
1473 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1474
1475         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1476
1477 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1478
1479         PR binutils/23212
1480         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1481         * aarch64-opc.c (verify_elem_sd): New.
1482         (fields): Add FLD_sz entr.
1483         * aarch64-tbl.h (_SIMD_INSN): New.
1484         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1485         fmulx scalar and vector by element isns.
1486
1487 2019-02-07  Nick Clifton  <nickc@redhat.com>
1488
1489         * po/sv.po: Updated Swedish translation.
1490
1491 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1492
1493         * s390-mkopc.c (main): Accept arch13 as cpu string.
1494         * s390-opc.c: Add new instruction formats and instruction opcode
1495         masks.
1496         * s390-opc.txt: Add new arch13 instructions.
1497
1498 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1499
1500         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1501         (aarch64_opcode): Change encoding for stg, stzg
1502         st2g and st2zg.
1503         * aarch64-asm-2.c: Regenerated.
1504         * aarch64-dis-2.c: Regenerated.
1505         * aarch64-opc-2.c: Regenerated.
1506
1507 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1508
1509         * aarch64-asm-2.c: Regenerated.
1510         * aarch64-dis-2.c: Likewise.
1511         * aarch64-opc-2.c: Likewise.
1512         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1513
1514 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1515             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1516
1517         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1518         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1519         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1520         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1521         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1522         case for ldstgv_indexed.
1523         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1524         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1525         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1526         * aarch64-asm-2.c: Regenerated.
1527         * aarch64-dis-2.c: Regenerated.
1528         * aarch64-opc-2.c: Regenerated.
1529
1530 2019-01-23  Nick Clifton  <nickc@redhat.com>
1531
1532         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1533
1534 2019-01-21  Nick Clifton  <nickc@redhat.com>
1535
1536         * po/de.po: Updated German translation.
1537         * po/uk.po: Updated Ukranian translation.
1538
1539 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1540         * mips-dis.c (mips_arch_choices): Fix typo in
1541         gs464, gs464e and gs264e descriptors.
1542
1543 2019-01-19  Nick Clifton  <nickc@redhat.com>
1544
1545         * configure: Regenerate.
1546         * po/opcodes.pot: Regenerate.
1547
1548 2018-06-24  Nick Clifton  <nickc@redhat.com>
1549
1550         2.32 branch created.
1551
1552 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1553
1554         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1555         if it is null.
1556         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1557         zero.
1558
1559 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1560
1561         * configure: Regenerate.
1562
1563 2019-01-07  Alan Modra  <amodra@gmail.com>
1564
1565         * configure: Regenerate.
1566         * po/POTFILES.in: Regenerate.
1567
1568 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1569
1570         * s12z-opc.c: New file.
1571         * s12z-opc.h: New file.
1572         * s12z-dis.c: Removed all code not directly related to display
1573         of instructions.  Used the interface provided by the new files
1574         instead.
1575         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1576         * Makefile.in: Regenerate.
1577         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1578         * configure: Regenerate.
1579
1580 2019-01-01  Alan Modra  <amodra@gmail.com>
1581
1582         Update year range in copyright notice of all files.
1583
1584 For older changes see ChangeLog-2018
1585 \f
1586 Copyright (C) 2019 Free Software Foundation, Inc.
1587
1588 Copying and distribution of this file, with or without modification,
1589 are permitted in any medium without royalty provided the copyright
1590 notice and this notice are preserved.
1591
1592 Local Variables:
1593 mode: change-log
1594 left-margin: 8
1595 fill-column: 74
1596 version-control: never
1597 End: