1 2020-02-12 Jan Beulich <jbeulich@suse.com>
4 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
5 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
6 Amd64 and Intel64 templates.
7 (call, jmp): Likewise for far indirect variants. Dro
9 * i386-tbl.h: Re-generate.
11 2020-02-11 Jan Beulich <jbeulich@suse.com>
13 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
14 * i386-opc.h (ShortForm): Delete.
15 (struct i386_opcode_modifier): Remove shortform field.
16 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
17 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
18 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
19 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
21 * i386-tbl.h: Re-generate.
23 2020-02-11 Jan Beulich <jbeulich@suse.com>
25 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
26 fucompi): Drop ShortForm from operand-less templates.
27 * i386-tbl.h: Re-generate.
29 2020-02-11 Alan Modra <amodra@gmail.com>
31 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
32 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
33 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
34 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
35 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
37 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
39 * arm-dis.c (print_insn_cde): Define 'V' parse character.
40 (cde_opcodes): Add VCX* instructions.
42 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
43 Matthew Malcomson <matthew.malcomson@arm.com>
45 * arm-dis.c (struct cdeopcode32): New.
46 (CDE_OPCODE): New macro.
47 (cde_opcodes): New disassembly table.
48 (regnames): New option to table.
49 (cde_coprocs): New global variable.
51 (print_insn_thumb32): Use print_insn_cde.
52 (parse_arm_disassembler_options): Parse coprocN args.
54 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
57 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
59 * i386-opc.h (AMD64): Removed.
63 (INTEL64ONLY): Likewise.
64 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
65 * i386-opc.tbl (Amd64): New.
67 (Intel64Only): Likewise.
68 Replace AMD64 with Amd64. Update sysenter/sysenter with
69 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
70 * i386-tbl.h: Regenerated.
72 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
75 * z80-dis.c: Add support for GBZ80 opcodes.
77 2020-02-04 Alan Modra <amodra@gmail.com>
79 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
81 2020-02-03 Alan Modra <amodra@gmail.com>
83 * m32c-ibld.c: Regenerate.
85 2020-02-01 Alan Modra <amodra@gmail.com>
87 * frv-ibld.c: Regenerate.
89 2020-01-31 Jan Beulich <jbeulich@suse.com>
91 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
92 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
93 (OP_E_memory): Replace xmm_mdq_mode case label by
94 vex_scalar_w_dq_mode one.
95 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
97 2020-01-31 Jan Beulich <jbeulich@suse.com>
99 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
100 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
101 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
102 (intel_operand_size): Drop vex_w_dq_mode case label.
104 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
106 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
107 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
109 2020-01-30 Alan Modra <amodra@gmail.com>
111 * m32c-ibld.c: Regenerate.
113 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
115 * bpf-opc.c: Regenerate.
117 2020-01-30 Jan Beulich <jbeulich@suse.com>
119 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
120 (dis386): Use them to replace C2/C3 table entries.
121 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
122 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
123 ones. Use Size64 instead of DefaultSize on Intel64 ones.
124 * i386-tbl.h: Re-generate.
126 2020-01-30 Jan Beulich <jbeulich@suse.com>
128 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
130 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
132 * i386-tbl.h: Re-generate.
134 2020-01-30 Alan Modra <amodra@gmail.com>
136 * tic4x-dis.c (tic4x_dp): Make unsigned.
138 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
139 Jan Beulich <jbeulich@suse.com>
142 * i386-dis.c (MOVSXD_Fixup): New function.
143 (movsxd_mode): New enum.
144 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
145 (intel_operand_size): Handle movsxd_mode.
146 (OP_E_register): Likewise.
148 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
149 register on movsxd. Add movsxd with 16-bit destination register
150 for AMD64 and Intel64 ISAs.
151 * i386-tbl.h: Regenerated.
153 2020-01-27 Tamar Christina <tamar.christina@arm.com>
156 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
157 * aarch64-asm-2.c: Regenerate
158 * aarch64-dis-2.c: Likewise.
159 * aarch64-opc-2.c: Likewise.
161 2020-01-21 Jan Beulich <jbeulich@suse.com>
163 * i386-opc.tbl (sysret): Drop DefaultSize.
164 * i386-tbl.h: Re-generate.
166 2020-01-21 Jan Beulich <jbeulich@suse.com>
168 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
170 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
171 * i386-tbl.h: Re-generate.
173 2020-01-20 Nick Clifton <nickc@redhat.com>
175 * po/de.po: Updated German translation.
176 * po/pt_BR.po: Updated Brazilian Portuguese translation.
177 * po/uk.po: Updated Ukranian translation.
179 2020-01-20 Alan Modra <amodra@gmail.com>
181 * hppa-dis.c (fput_const): Remove useless cast.
183 2020-01-20 Alan Modra <amodra@gmail.com>
185 * arm-dis.c (print_insn_arm): Wrap 'T' value.
187 2020-01-18 Nick Clifton <nickc@redhat.com>
189 * configure: Regenerate.
190 * po/opcodes.pot: Regenerate.
192 2020-01-18 Nick Clifton <nickc@redhat.com>
194 Binutils 2.34 branch created.
196 2020-01-17 Christian Biesinger <cbiesinger@google.com>
198 * opintl.h: Fix spelling error (seperate).
200 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
202 * i386-opc.tbl: Add {vex} pseudo prefix.
203 * i386-tbl.h: Regenerated.
205 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
208 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
209 (neon_opcodes): Likewise.
210 (select_arm_features): Make sure we enable MVE bits when selecting
211 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
214 2020-01-16 Jan Beulich <jbeulich@suse.com>
216 * i386-opc.tbl: Drop stale comment from XOP section.
218 2020-01-16 Jan Beulich <jbeulich@suse.com>
220 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
221 (extractps): Add VexWIG to SSE2AVX forms.
222 * i386-tbl.h: Re-generate.
224 2020-01-16 Jan Beulich <jbeulich@suse.com>
226 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
227 Size64 from and use VexW1 on SSE2AVX forms.
228 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
229 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
230 * i386-tbl.h: Re-generate.
232 2020-01-15 Alan Modra <amodra@gmail.com>
234 * tic4x-dis.c (tic4x_version): Make unsigned long.
235 (optab, optab_special, registernames): New file scope vars.
236 (tic4x_print_register): Set up registernames rather than
237 malloc'd registertable.
238 (tic4x_disassemble): Delete optable and optable_special. Use
239 optab and optab_special instead. Throw away old optab,
240 optab_special and registernames when info->mach changes.
242 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
245 * z80-dis.c (suffix): Use .db instruction to generate double
248 2020-01-14 Alan Modra <amodra@gmail.com>
250 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
251 values to unsigned before shifting.
253 2020-01-13 Thomas Troeger <tstroege@gmx.de>
255 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
257 (print_insn_thumb16, print_insn_thumb32): Likewise.
258 (print_insn): Initialize the insn info.
259 * i386-dis.c (print_insn): Initialize the insn info fields, and
262 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
264 * arc-opc.c (C_NE): Make it required.
266 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
268 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
269 reserved register name.
271 2020-01-13 Alan Modra <amodra@gmail.com>
273 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
274 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
276 2020-01-13 Alan Modra <amodra@gmail.com>
278 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
279 result of wasm_read_leb128 in a uint64_t and check that bits
280 are not lost when copying to other locals. Use uint32_t for
281 most locals. Use PRId64 when printing int64_t.
283 2020-01-13 Alan Modra <amodra@gmail.com>
285 * score-dis.c: Formatting.
286 * score7-dis.c: Formatting.
288 2020-01-13 Alan Modra <amodra@gmail.com>
290 * score-dis.c (print_insn_score48): Use unsigned variables for
291 unsigned values. Don't left shift negative values.
292 (print_insn_score32): Likewise.
293 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
295 2020-01-13 Alan Modra <amodra@gmail.com>
297 * tic4x-dis.c (tic4x_print_register): Remove dead code.
299 2020-01-13 Alan Modra <amodra@gmail.com>
301 * fr30-ibld.c: Regenerate.
303 2020-01-13 Alan Modra <amodra@gmail.com>
305 * xgate-dis.c (print_insn): Don't left shift signed value.
306 (ripBits): Formatting, use 1u.
308 2020-01-10 Alan Modra <amodra@gmail.com>
310 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
311 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
313 2020-01-10 Alan Modra <amodra@gmail.com>
315 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
316 and XRREG value earlier to avoid a shift with negative exponent.
317 * m10200-dis.c (disassemble): Similarly.
319 2020-01-09 Nick Clifton <nickc@redhat.com>
322 * z80-dis.c (ld_ii_ii): Use correct cast.
324 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
327 * z80-dis.c (ld_ii_ii): Use character constant when checking
330 2020-01-09 Jan Beulich <jbeulich@suse.com>
332 * i386-dis.c (SEP_Fixup): New.
334 (dis386_twobyte): Use it for sysenter/sysexit.
335 (enum x86_64_isa): Change amd64 enumerator to value 1.
336 (OP_J): Compare isa64 against intel64 instead of amd64.
337 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
339 * i386-tbl.h: Re-generate.
341 2020-01-08 Alan Modra <amodra@gmail.com>
343 * z8k-dis.c: Include libiberty.h
344 (instr_data_s): Make max_fetched unsigned.
345 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
346 Don't exceed byte_info bounds.
347 (output_instr): Make num_bytes unsigned.
348 (unpack_instr): Likewise for nibl_count and loop.
349 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
351 * z8k-opc.h: Regenerate.
353 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
355 * arc-tbl.h (llock): Use 'LLOCK' as class.
357 (scond): Use 'SCOND' as class.
359 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
362 2020-01-06 Alan Modra <amodra@gmail.com>
364 * m32c-ibld.c: Regenerate.
366 2020-01-06 Alan Modra <amodra@gmail.com>
369 * z80-dis.c (suffix): Don't use a local struct buffer copy.
370 Peek at next byte to prevent recursion on repeated prefix bytes.
371 Ensure uninitialised "mybuf" is not accessed.
372 (print_insn_z80): Don't zero n_fetch and n_used here,..
373 (print_insn_z80_buf): ..do it here instead.
375 2020-01-04 Alan Modra <amodra@gmail.com>
377 * m32r-ibld.c: Regenerate.
379 2020-01-04 Alan Modra <amodra@gmail.com>
381 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
383 2020-01-04 Alan Modra <amodra@gmail.com>
385 * crx-dis.c (match_opcode): Avoid shift left of signed value.
387 2020-01-04 Alan Modra <amodra@gmail.com>
389 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
391 2020-01-03 Jan Beulich <jbeulich@suse.com>
393 * aarch64-tbl.h (aarch64_opcode_table): Use
394 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
396 2020-01-03 Jan Beulich <jbeulich@suse.com>
398 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
399 forms of SUDOT and USDOT.
401 2020-01-03 Jan Beulich <jbeulich@suse.com>
403 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
405 * opcodes/aarch64-dis-2.c: Re-generate.
407 2020-01-03 Jan Beulich <jbeulich@suse.com>
409 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
411 * opcodes/aarch64-dis-2.c: Re-generate.
413 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
415 * z80-dis.c: Add support for eZ80 and Z80 instructions.
417 2020-01-01 Alan Modra <amodra@gmail.com>
419 Update year range in copyright notice of all files.
421 For older changes see ChangeLog-2019
423 Copyright (C) 2020 Free Software Foundation, Inc.
425 Copying and distribution of this file, with or without modification,
426 are permitted in any medium without royalty provided the copyright
427 notice and this notice are preserved.
433 version-control: never