opcodes/ChangeLog

   1 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis-evex.h: Break into ...
   4         * i386-dis-evex-len.h: New file.
   5         * i386-dis-evex-mod.h: Likewise.
   6         * i386-dis-evex-prefix.h: Likewise.
   7         * i386-dis-evex-reg.h: Likewise.
   8         * i386-dis-evex-w.h: Likewise.
   9         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
  10         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
  11         i386-dis-evex-mod.h.
  12
  13 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
  14
  15         PR binutils/24700
  16         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
  17         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
  18         EVEX_W_0F385B_P_2.
  19         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
  20         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
  21         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
  22         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
  23         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
  24         EVEX_LEN_0F385B_P_2_W_1.
  25         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
  26         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
  27         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
  28         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
  29         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
  30         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
  31         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
  32         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
  33         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
  34         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
  35
  36 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
  37
  38         PR binutils/24691
  39         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
  40         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
  41         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
  42         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
  43         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
  44         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
  45         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
  46         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
  47         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
  48         EVEX_LEN_0F3A43_P_2_W_1.
  49         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
  50         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
  51         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
  52         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
  53         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
  54         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
  55         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
  56         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
  57         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
  58         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
  59         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
  60         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
  61
  62 2019-06-14  Nick Clifton  <nickc@redhat.com>
  63
  64         * po/fr.po; Updated French translation.
  65
  66 2019-06-13  Stafford Horne  <shorne@gmail.com>
  67
  68         * or1k-asm.c: Regenerated.
  69         * or1k-desc.c: Regenerated.
  70         * or1k-desc.h: Regenerated.
  71         * or1k-dis.c: Regenerated.
  72         * or1k-ibld.c: Regenerated.
  73         * or1k-opc.c: Regenerated.
  74         * or1k-opc.h: Regenerated.
  75         * or1k-opinst.c: Regenerated.
  76
  77 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
  78
  79         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
  80
  81 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         PR binutils/24633
  84         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
  85         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
  86         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
  87         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
  88         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
  89         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
  90         EVEX_LEN_0F3A1B_P_2_W_1.
  91         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
  92         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
  93         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
  94         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
  95         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
  96         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
  97         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
  98         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
  99
 100 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 101
 102         PR binutils/24626
 103         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 104         EVEX.vvvv when disassembling VEX and EVEX instructions.
 105         (OP_VEX): Set vex.register_specifier to 0 after readding
 106         vex.register_specifier.
 107         (OP_Vex_2src_1): Likewise.
 108         (OP_Vex_2src_2): Likewise.
 109         (OP_LWP_E): Likewise.
 110         (OP_EX_Vex): Don't check vex.register_specifier.
 111         (OP_XMM_Vex): Likewise.
 112
 113 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 114             Lili Cui  <lili.cui@intel.com>
 115
 116         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 117         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 118         instructions.
 119         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 120         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 121         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 122         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 123         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 124         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 125         * i386-init.h: Regenerated.
 126         * i386-tbl.h: Likewise.
 127
 128 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 129             Lili Cui  <lili.cui@intel.com>
 130
 131         * doc/c-i386.texi: Document enqcmd.
 132         * testsuite/gas/i386/enqcmd-intel.d: New file.
 133         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 134         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 135         * testsuite/gas/i386/enqcmd.d: Likewise.
 136         * testsuite/gas/i386/enqcmd.s: Likewise.
 137         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 138         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 139         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 140         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 141         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 142         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 143         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 144         and x86-64-enqcmd.
 145
 146 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 147
 148         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 149
 150 2019-06-03  Alan Modra  <amodra@gmail.com>
 151
 152         * ppc-dis.c (prefix_opcd_indices): Correct size.
 153
 154 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         PR gas/24625
 157         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 158         Disp8ShiftVL.
 159         * i386-tbl.h: Regenerated.
 160
 161 2019-05-24  Alan Modra  <amodra@gmail.com>
 162
 163         * po/POTFILES.in: Regenerate.
 164
 165 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 166             Alan Modra  <amodra@gmail.com>
 167
 168         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 169         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 170         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 171         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 172         XTOP>): Define and add entries.
 173         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 174         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 175         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 176         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 177
 178 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 179             Alan Modra  <amodra@gmail.com>
 180
 181         * ppc-dis.c (ppc_opts): Add "future" entry.
 182         (PREFIX_OPCD_SEGS): Define.
 183         (prefix_opcd_indices): New array.
 184         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 185         (lookup_prefix): New function.
 186         (print_insn_powerpc): Handle 64-bit prefix instructions.
 187         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 188         (PMRR, POWERXX): Define.
 189         (prefix_opcodes): New instruction table.
 190         (prefix_num_opcodes): New constant.
 191
 192 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 193
 194         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 195         * configure: Regenerated.
 196         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 197         and cpu/bpf.opc.
 198         (HFILES): Add bpf-desc.h and bpf-opc.h.
 199         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 200         bpf-ibld.c and bpf-opc.c.
 201         (BPF_DEPS): Define.
 202         * Makefile.in: Regenerated.
 203         * disassemble.c (ARCH_bpf): Define.
 204         (disassembler): Add case for bfd_arch_bpf.
 205         (disassemble_init_for_target): Likewise.
 206         (enum epbf_isa_attr): Define.
 207         * disassemble.h: extern print_insn_bpf.
 208         * bpf-asm.c: Generated.
 209         * bpf-opc.h: Likewise.
 210         * bpf-opc.c: Likewise.
 211         * bpf-ibld.c: Likewise.
 212         * bpf-dis.c: Likewise.
 213         * bpf-desc.h: Likewise.
 214         * bpf-desc.c: Likewise.
 215
 216 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 217
 218         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 219         and VMSR with the new operands.
 220
 221 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 222
 223         * arm-dis.c (enum mve_instructions): New enum
 224         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 225         and cneg.
 226         (mve_opcodes): New instructions as above.
 227         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 228         csneg and csel.
 229         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 230
 231 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 232
 233         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 234         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 235         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 236         uqshl, urshrl and urshr.
 237         (is_mve_okay_in_it): Add new instructions to TRUE list.
 238         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 239         (print_insn_mve): Updated to accept new %j,
 240         %<bitfield>m and %<bitfield>n patterns.
 241
 242 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 243
 244         * mips-opc.c (mips_builtin_opcodes): Change source register
 245         constraint for DAUI.
 246
 247 2019-05-20  Nick Clifton  <nickc@redhat.com>
 248
 249         * po/fr.po: Updated French translation.
 250
 251 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 252             Michael Collison <michael.collison@arm.com>
 253
 254         * arm-dis.c (thumb32_opcodes): Add new instructions.
 255         (enum mve_instructions): Likewise.
 256         (enum mve_undefined): Add new reasons.
 257         (is_mve_encoding_conflict): Handle new instructions.
 258         (is_mve_undefined): Likewise.
 259         (is_mve_unpredictable): Likewise.
 260         (print_mve_undefined): Likewise.
 261         (print_mve_size): Likewise.
 262
 263 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 264             Michael Collison <michael.collison@arm.com>
 265
 266         * arm-dis.c (thumb32_opcodes): Add new instructions.
 267         (enum mve_instructions): Likewise.
 268         (is_mve_encoding_conflict): Handle new instructions.
 269         (is_mve_undefined): Likewise.
 270         (is_mve_unpredictable): Likewise.
 271         (print_mve_size): Likewise.
 272
 273 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 274             Michael Collison <michael.collison@arm.com>
 275
 276         * arm-dis.c (thumb32_opcodes): Add new instructions.
 277         (enum mve_instructions): Likewise.
 278         (is_mve_encoding_conflict): Likewise.
 279         (is_mve_unpredictable): Likewise.
 280         (print_mve_size): Likewise.
 281
 282 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 283             Michael Collison <michael.collison@arm.com>
 284
 285         * arm-dis.c (thumb32_opcodes): Add new instructions.
 286         (enum mve_instructions): Likewise.
 287         (is_mve_encoding_conflict): Handle new instructions.
 288         (is_mve_undefined): Likewise.
 289         (is_mve_unpredictable): Likewise.
 290         (print_mve_size): Likewise.
 291
 292 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 293             Michael Collison <michael.collison@arm.com>
 294
 295         * arm-dis.c (thumb32_opcodes): Add new instructions.
 296         (enum mve_instructions): Likewise.
 297         (is_mve_encoding_conflict): Handle new instructions.
 298         (is_mve_undefined): Likewise.
 299         (is_mve_unpredictable): Likewise.
 300         (print_mve_size): Likewise.
 301         (print_insn_mve): Likewise.
 302
 303 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 304             Michael Collison <michael.collison@arm.com>
 305
 306         * arm-dis.c (thumb32_opcodes): Add new instructions.
 307         (print_insn_thumb32): Handle new instructions.
 308
 309 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 310             Michael Collison <michael.collison@arm.com>
 311
 312         * arm-dis.c (enum mve_instructions): Add new instructions.
 313         (enum mve_undefined): Add new reasons.
 314         (is_mve_encoding_conflict): Handle new instructions.
 315         (is_mve_undefined): Likewise.
 316         (is_mve_unpredictable): Likewise.
 317         (print_mve_undefined): Likewise.
 318         (print_mve_size): Likewise.
 319         (print_mve_shift_n): Likewise.
 320         (print_insn_mve): Likewise.
 321
 322 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 323             Michael Collison <michael.collison@arm.com>
 324
 325         * arm-dis.c (enum mve_instructions): Add new instructions.
 326         (is_mve_encoding_conflict): Handle new instructions.
 327         (is_mve_unpredictable): Likewise.
 328         (print_mve_rotate): Likewise.
 329         (print_mve_size): Likewise.
 330         (print_insn_mve): Likewise.
 331
 332 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 333             Michael Collison <michael.collison@arm.com>
 334
 335         * arm-dis.c (enum mve_instructions): Add new instructions.
 336         (is_mve_encoding_conflict): Handle new instructions.
 337         (is_mve_unpredictable): Likewise.
 338         (print_mve_size): Likewise.
 339         (print_insn_mve): Likewise.
 340
 341 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 342             Michael Collison <michael.collison@arm.com>
 343
 344         * arm-dis.c (enum mve_instructions): Add new instructions.
 345         (enum mve_undefined): Add new reasons.
 346         (is_mve_encoding_conflict): Handle new instructions.
 347         (is_mve_undefined): Likewise.
 348         (is_mve_unpredictable): Likewise.
 349         (print_mve_undefined): Likewise.
 350         (print_mve_size): Likewise.
 351         (print_insn_mve): Likewise.
 352
 353 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 354             Michael Collison <michael.collison@arm.com>
 355
 356         * arm-dis.c (enum mve_instructions): Add new instructions.
 357         (is_mve_encoding_conflict): Handle new instructions.
 358         (is_mve_undefined): Likewise.
 359         (is_mve_unpredictable): Likewise.
 360         (print_mve_size): Likewise.
 361         (print_insn_mve): Likewise.
 362
 363 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 364             Michael Collison <michael.collison@arm.com>
 365
 366         * arm-dis.c (enum mve_instructions): Add new instructions.
 367         (enum mve_unpredictable): Add new reasons.
 368         (enum mve_undefined): Likewise.
 369         (is_mve_okay_in_it): Handle new isntructions.
 370         (is_mve_encoding_conflict): Likewise.
 371         (is_mve_undefined): Likewise.
 372         (is_mve_unpredictable): Likewise.
 373         (print_mve_vmov_index): Likewise.
 374         (print_simd_imm8): Likewise.
 375         (print_mve_undefined): Likewise.
 376         (print_mve_unpredictable): Likewise.
 377         (print_mve_size): Likewise.
 378         (print_insn_mve): Likewise.
 379
 380 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 381             Michael Collison <michael.collison@arm.com>
 382
 383         * arm-dis.c (enum mve_instructions): Add new instructions.
 384         (enum mve_unpredictable): Add new reasons.
 385         (enum mve_undefined): Likewise.
 386         (is_mve_encoding_conflict): Handle new instructions.
 387         (is_mve_undefined): Likewise.
 388         (is_mve_unpredictable): Likewise.
 389         (print_mve_undefined): Likewise.
 390         (print_mve_unpredictable): Likewise.
 391         (print_mve_rounding_mode): Likewise.
 392         (print_mve_vcvt_size): Likewise.
 393         (print_mve_size): Likewise.
 394         (print_insn_mve): Likewise.
 395
 396 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 397             Michael Collison <michael.collison@arm.com>
 398
 399         * arm-dis.c (enum mve_instructions): Add new instructions.
 400         (enum mve_unpredictable): Add new reasons.
 401         (enum mve_undefined): Likewise.
 402         (is_mve_undefined): Handle new instructions.
 403         (is_mve_unpredictable): Likewise.
 404         (print_mve_undefined): Likewise.
 405         (print_mve_unpredictable): Likewise.
 406         (print_mve_size): Likewise.
 407         (print_insn_mve): Likewise.
 408
 409 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 410             Michael Collison <michael.collison@arm.com>
 411
 412         * arm-dis.c (enum mve_instructions): Add new instructions.
 413         (enum mve_undefined): Add new reasons.
 414         (insns): Add new instructions.
 415         (is_mve_encoding_conflict):
 416         (print_mve_vld_str_addr): New print function.
 417         (is_mve_undefined): Handle new instructions.
 418         (is_mve_unpredictable): Likewise.
 419         (print_mve_undefined): Likewise.
 420         (print_mve_size): Likewise.
 421         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 422         (print_insn_mve):  Handle new operands.
 423
 424 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 425             Michael Collison <michael.collison@arm.com>
 426
 427         * arm-dis.c (enum mve_instructions): Add new instructions.
 428         (enum mve_unpredictable): Add new reasons.
 429         (is_mve_encoding_conflict): Handle new instructions.
 430         (is_mve_unpredictable): Likewise.
 431         (mve_opcodes): Add new instructions.
 432         (print_mve_unpredictable): Handle new reasons.
 433         (print_mve_register_blocks): New print function.
 434         (print_mve_size): Handle new instructions.
 435         (print_insn_mve): Likewise.
 436
 437 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 438             Michael Collison <michael.collison@arm.com>
 439
 440         * arm-dis.c (enum mve_instructions): Add new instructions.
 441         (enum mve_unpredictable): Add new reasons.
 442         (enum mve_undefined): Likewise.
 443         (is_mve_encoding_conflict): Handle new instructions.
 444         (is_mve_undefined): Likewise.
 445         (is_mve_unpredictable): Likewise.
 446         (coprocessor_opcodes): Move NEON VDUP from here...
 447         (neon_opcodes): ... to here.
 448         (mve_opcodes): Add new instructions.
 449         (print_mve_undefined):  Handle new reasons.
 450         (print_mve_unpredictable): Likewise.
 451         (print_mve_size): Handle new instructions.
 452         (print_insn_neon): Handle vdup.
 453         (print_insn_mve): Handle new operands.
 454
 455 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 456             Michael Collison <michael.collison@arm.com>
 457
 458         * arm-dis.c (enum mve_instructions): Add new instructions.
 459         (enum mve_unpredictable): Add new values.
 460         (mve_opcodes): Add new instructions.
 461         (vec_condnames): New array with vector conditions.
 462         (mve_predicatenames): New array with predicate suffixes.
 463         (mve_vec_sizename): New array with vector sizes.
 464         (enum vpt_pred_state): New enum with vector predication states.
 465         (struct vpt_block): New struct type for vpt blocks.
 466         (vpt_block_state): Global struct to keep track of state.
 467         (mve_extract_pred_mask): New helper function.
 468         (num_instructions_vpt_block): Likewise.
 469         (mark_outside_vpt_block): Likewise.
 470         (mark_inside_vpt_block): Likewise.
 471         (invert_next_predicate_state): Likewise.
 472         (update_next_predicate_state): Likewise.
 473         (update_vpt_block_state): Likewise.
 474         (is_vpt_instruction): Likewise.
 475         (is_mve_encoding_conflict): Add entries for new instructions.
 476         (is_mve_unpredictable): Likewise.
 477         (print_mve_unpredictable): Handle new cases.
 478         (print_instruction_predicate): Likewise.
 479         (print_mve_size): New function.
 480         (print_vec_condition): New function.
 481         (print_insn_mve): Handle vpt blocks and new print operands.
 482
 483 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 484
 485         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 486         8, 14 and 15 for Armv8.1-M Mainline.
 487
 488 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 489             Michael Collison <michael.collison@arm.com>
 490
 491         * arm-dis.c (enum mve_instructions): New enum.
 492         (enum mve_unpredictable): Likewise.
 493         (enum mve_undefined): Likewise.
 494         (struct mopcode32): New struct.
 495         (is_mve_okay_in_it): New function.
 496         (is_mve_architecture): Likewise.
 497         (arm_decode_field): Likewise.
 498         (arm_decode_field_multiple): Likewise.
 499         (is_mve_encoding_conflict): Likewise.
 500         (is_mve_undefined): Likewise.
 501         (is_mve_unpredictable): Likewise.
 502         (print_mve_undefined): Likewise.
 503         (print_mve_unpredictable): Likewise.
 504         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 505         (print_insn_mve): New function.
 506         (print_insn_thumb32): Handle MVE architecture.
 507         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 508
 509 2019-05-10  Nick Clifton  <nickc@redhat.com>
 510
 511         PR 24538
 512         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 513         end of the table prematurely.
 514
 515 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 516
 517         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 518         macros for R6.
 519
 520 2019-05-11  Alan Modra  <amodra@gmail.com>
 521
 522         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 523         when -Mraw is in effect.
 524
 525 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 526
 527         * aarch64-dis-2.c: Regenerate.
 528         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 529         (OP_SVE_BBB): New variant set.
 530         (OP_SVE_DDDD): New variant set.
 531         (OP_SVE_HHH): New variant set.
 532         (OP_SVE_HHHU): New variant set.
 533         (OP_SVE_SSS): New variant set.
 534         (OP_SVE_SSSU): New variant set.
 535         (OP_SVE_SHH): New variant set.
 536         (OP_SVE_SBBU): New variant set.
 537         (OP_SVE_DSS): New variant set.
 538         (OP_SVE_DHHU): New variant set.
 539         (OP_SVE_VMV_HSD_BHS): New variant set.
 540         (OP_SVE_VVU_HSD_BHS): New variant set.
 541         (OP_SVE_VVVU_SD_BH): New variant set.
 542         (OP_SVE_VVVU_BHSD): New variant set.
 543         (OP_SVE_VVV_QHD_DBS): New variant set.
 544         (OP_SVE_VVV_HSD_BHS): New variant set.
 545         (OP_SVE_VVV_HSD_BHS2): New variant set.
 546         (OP_SVE_VVV_BHS_HSD): New variant set.
 547         (OP_SVE_VV_BHS_HSD): New variant set.
 548         (OP_SVE_VVV_SD): New variant set.
 549         (OP_SVE_VVU_BHS_HSD): New variant set.
 550         (OP_SVE_VZVV_SD): New variant set.
 551         (OP_SVE_VZVV_BH): New variant set.
 552         (OP_SVE_VZV_SD): New variant set.
 553         (aarch64_opcode_table): Add sve2 instructions.
 554
 555 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 556
 557         * aarch64-asm-2.c: Regenerated.
 558         * aarch64-dis-2.c: Regenerated.
 559         * aarch64-opc-2.c: Regenerated.
 560         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 561         for SVE_SHLIMM_UNPRED_22.
 562         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 563         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 564         operand.
 565
 566 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 567
 568         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 569         sve_size_tsz_bhs iclass encode.
 570         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 571         sve_size_tsz_bhs iclass decode.
 572
 573 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 574
 575         * aarch64-asm-2.c: Regenerated.
 576         * aarch64-dis-2.c: Regenerated.
 577         * aarch64-opc-2.c: Regenerated.
 578         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 579         for SVE_Zm4_11_INDEX.
 580         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 581         (fields): Handle SVE_i2h field.
 582         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 583         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 584
 585 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 586
 587         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 588         sve_shift_tsz_bhsd iclass encode.
 589         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 590         sve_shift_tsz_bhsd iclass decode.
 591
 592 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 593
 594         * aarch64-asm-2.c: Regenerated.
 595         * aarch64-dis-2.c: Regenerated.
 596         * aarch64-opc-2.c: Regenerated.
 597         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 598         (aarch64_encode_variant_using_iclass): Handle
 599         sve_shift_tsz_hsd iclass encode.
 600         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 601         sve_shift_tsz_hsd iclass decode.
 602         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 603         for SVE_SHRIMM_UNPRED_22.
 604         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 605         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 606         operand.
 607
 608 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 609
 610         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 611         sve_size_013 iclass encode.
 612         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 613         sve_size_013 iclass decode.
 614
 615 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 616
 617         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 618         sve_size_bh iclass encode.
 619         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 620         sve_size_bh iclass decode.
 621
 622 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 623
 624         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 625         sve_size_sd2 iclass encode.
 626         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 627         sve_size_sd2 iclass decode.
 628         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 629         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 630
 631 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 632
 633         * aarch64-asm-2.c: Regenerated.
 634         * aarch64-dis-2.c: Regenerated.
 635         * aarch64-opc-2.c: Regenerated.
 636         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 637         for SVE_ADDR_ZX.
 638         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 639         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 640
 641 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 642
 643         * aarch64-asm-2.c: Regenerated.
 644         * aarch64-dis-2.c: Regenerated.
 645         * aarch64-opc-2.c: Regenerated.
 646         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 647         for SVE_Zm3_11_INDEX.
 648         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 649         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 650         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 651         fields.
 652         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 653
 654 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 655
 656         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 657         sve_size_hsd2 iclass encode.
 658         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 659         sve_size_hsd2 iclass decode.
 660         * aarch64-opc.c (fields): Handle SVE_size field.
 661         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 662
 663 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 664
 665         * aarch64-asm-2.c: Regenerated.
 666         * aarch64-dis-2.c: Regenerated.
 667         * aarch64-opc-2.c: Regenerated.
 668         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 669         for SVE_IMM_ROT3.
 670         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 671         (fields): Handle SVE_rot3 field.
 672         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 673         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 674
 675 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 676
 677         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 678         instructions.
 679
 680 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 681
 682         * aarch64-tbl.h
 683         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 684         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 685         aarch64_feature_sve2bitperm): New feature sets.
 686         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 687         for feature set addresses.
 688         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 689         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 690
 691 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 692             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 693
 694         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 695         argument and set ASE_EVA_R6 appropriately.
 696         (set_default_mips_dis_options): Pass ISA to above.
 697         (parse_mips_dis_option): Likewise.
 698         * mips-opc.c (EVAR6): New macro.
 699         (mips_builtin_opcodes): Add llwpe, scwpe.
 700
 701 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 702
 703         * aarch64-asm-2.c: Regenerated.
 704         * aarch64-dis-2.c: Regenerated.
 705         * aarch64-opc-2.c: Regenerated.
 706         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 707         AARCH64_OPND_TME_UIMM16.
 708         (aarch64_print_operand): Likewise.
 709         * aarch64-tbl.h (QL_IMM_NIL): New.
 710         (TME): New.
 711         (_TME_INSN): New.
 712         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 713
 714 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 715
 716         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 717
 718 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 719             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 720
 721         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 722
 723 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 724
 725         * s12z-opc.h: Add extern "C" bracketing to help
 726         users who wish to use this interface in c++ code.
 727
 728 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 729
 730         * s12z-opc.c (bm_decode): Handle bit map operations with the
 731         "reserved0" mode.
 732
 733 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 734
 735         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 736         specifier.  Add entries for VLDR and VSTR of system registers.
 737         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 738         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 739         of %J and %K format specifier.
 740
 741 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 742
 743         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 744         Add new entries for VSCCLRM instruction.
 745         (print_insn_coprocessor): Handle new %C format control code.
 746
 747 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 748
 749         * arm-dis.c (enum isa): New enum.
 750         (struct sopcode32): New structure.
 751         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 752         set isa field of all current entries to ANY.
 753         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 754         Only match an entry if its isa field allows the current mode.
 755
 756 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 757
 758         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 759         CLRM.
 760         (print_insn_thumb32): Add logic to print %n CLRM register list.
 761
 762 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 763
 764         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 765         and %Q patterns.
 766
 767 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 768
 769         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 770         (print_insn_thumb32): Edit the switch case for %Z.
 771
 772 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 773
 774         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 775
 776 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 777
 778         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 779
 780 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 781
 782         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 783
 784 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 785
 786         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 787         Arm register with r13 and r15 unpredictable.
 788         (thumb32_opcodes): New instructions for bfx and bflx.
 789
 790 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 791
 792         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 793
 794 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 795
 796         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 797
 798 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 799
 800         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 801
 802 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 803
 804         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 805
 806 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 807
 808         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 809         "optr". ("operator" is a reserved word in c++).
 810
 811 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 812
 813         * aarch64-opc.c (aarch64_print_operand): Add case for
 814         AARCH64_OPND_Rt_SP.
 815         (verify_constraints): Likewise.
 816         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 817         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 818         to accept Rt|SP as first operand.
 819         (AARCH64_OPERANDS): Add new Rt_SP.
 820         * aarch64-asm-2.c: Regenerated.
 821         * aarch64-dis-2.c: Regenerated.
 822         * aarch64-opc-2.c: Regenerated.
 823
 824 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 825
 826         * aarch64-asm-2.c: Regenerated.
 827         * aarch64-dis-2.c: Likewise.
 828         * aarch64-opc-2.c: Likewise.
 829         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 830
 831 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 832
 833         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 834
 835 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 836
 837         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 838         * i386-init.h: Regenerated.
 839
 840 2019-04-07  Alan Modra  <amodra@gmail.com>
 841
 842         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 843         op_separator to control printing of spaces, comma and parens
 844         rather than need_comma, need_paren and spaces vars.
 845
 846 2019-04-07  Alan Modra  <amodra@gmail.com>
 847
 848         PR 24421
 849         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 850         (print_insn_neon, print_insn_arm): Likewise.
 851
 852 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 853
 854         * i386-dis-evex.h (evex_table): Updated to support BF16
 855         instructions.
 856         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 857         and EVEX_W_0F3872_P_3.
 858         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 859         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 860         * i386-opc.h (enum): Add CpuAVX512_BF16.
 861         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 862         * i386-opc.tbl: Add AVX512 BF16 instructions.
 863         * i386-init.h: Regenerated.
 864         * i386-tbl.h: Likewise.
 865
 866 2019-04-05  Alan Modra  <amodra@gmail.com>
 867
 868         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 869         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 870         to favour printing of "-" branch hint when using the "y" bit.
 871         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 872
 873 2019-04-05  Alan Modra  <amodra@gmail.com>
 874
 875         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 876         opcode until first operand is output.
 877
 878 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 879
 880         PR gas/24349
 881         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 882         (valid_bo_post_v2): Add support for 'at' branch hints.
 883         (insert_bo): Only error on branch on ctr.
 884         (get_bo_hint_mask): New function.
 885         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 886         for inserting 'at' branch hints.
 887         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 888         for extracting 'at' branch hints.
 889         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 890         (BOE): Delete operand.
 891         (BOM, BOP): New operands.
 892         (RM): Update value.
 893         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 894         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 895         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 896         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 897         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 898         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 899         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 900         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 901         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 902         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 903         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 904         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 905         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 906         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 907         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 908         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 909         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 910         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 911         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 912         bttarl+>: New extended mnemonics.
 913
 914 2019-03-28  Alan Modra  <amodra@gmail.com>
 915
 916         PR 24390
 917         * ppc-opc.c (BTF): Define.
 918         (powerpc_opcodes): Use for mtfsb*.
 919         * ppc-dis.c (print_insn_powerpc): Print fields with both
 920         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 921
 922 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 923
 924         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 925         (mapping_symbol_for_insn): Implement new algorithm.
 926         (print_insn): Remove duplicate code.
 927
 928 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 929
 930         * aarch64-dis.c (print_insn_aarch64):
 931         Implement override.
 932
 933 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 934
 935         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 936         order.
 937
 938 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 939
 940         * aarch64-dis.c (last_stop_offset): New.
 941         (print_insn_aarch64): Use stop_offset.
 942
 943 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 944
 945         PR gas/24359
 946         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 947         CPU_ANY_AVX2_FLAGS.
 948         * i386-init.h: Regenerated.
 949
 950 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 951
 952         PR gas/24348
 953         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 954         vmovdqu16, vmovdqu32 and vmovdqu64.
 955         * i386-tbl.h: Regenerated.
 956
 957 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 958
 959         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 960         from vstrszb, vstrszh, and vstrszf.
 961
 962 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 963
 964         * s390-opc.txt: Add instruction descriptions.
 965
 966 2019-02-08  Jim Wilson  <jimw@sifive.com>
 967
 968         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 969         <bne>: Likewise.
 970
 971 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 972
 973         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 974
 975 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 976
 977         PR binutils/23212
 978         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 979         * aarch64-opc.c (verify_elem_sd): New.
 980         (fields): Add FLD_sz entr.
 981         * aarch64-tbl.h (_SIMD_INSN): New.
 982         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 983         fmulx scalar and vector by element isns.
 984
 985 2019-02-07  Nick Clifton  <nickc@redhat.com>
 986
 987         * po/sv.po: Updated Swedish translation.
 988
 989 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 990
 991         * s390-mkopc.c (main): Accept arch13 as cpu string.
 992         * s390-opc.c: Add new instruction formats and instruction opcode
 993         masks.
 994         * s390-opc.txt: Add new arch13 instructions.
 995
 996 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 997
 998         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 999         (aarch64_opcode): Change encoding for stg, stzg
1000         st2g and st2zg.
1001         * aarch64-asm-2.c: Regenerated.
1002         * aarch64-dis-2.c: Regenerated.
1003         * aarch64-opc-2.c: Regenerated.
1004
1005 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1006
1007         * aarch64-asm-2.c: Regenerated.
1008         * aarch64-dis-2.c: Likewise.
1009         * aarch64-opc-2.c: Likewise.
1010         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1011
1012 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1013             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1014
1015         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1016         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1017         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1018         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1019         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1020         case for ldstgv_indexed.
1021         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1022         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1023         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1024         * aarch64-asm-2.c: Regenerated.
1025         * aarch64-dis-2.c: Regenerated.
1026         * aarch64-opc-2.c: Regenerated.
1027
1028 2019-01-23  Nick Clifton  <nickc@redhat.com>
1029
1030         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1031
1032 2019-01-21  Nick Clifton  <nickc@redhat.com>
1033
1034         * po/de.po: Updated German translation.
1035         * po/uk.po: Updated Ukranian translation.
1036
1037 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1038         * mips-dis.c (mips_arch_choices): Fix typo in
1039         gs464, gs464e and gs264e descriptors.
1040
1041 2019-01-19  Nick Clifton  <nickc@redhat.com>
1042
1043         * configure: Regenerate.
1044         * po/opcodes.pot: Regenerate.
1045
1046 2018-06-24  Nick Clifton  <nickc@redhat.com>
1047
1048         2.32 branch created.
1049
1050 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1051
1052         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1053         if it is null.
1054         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1055         zero.
1056
1057 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1058
1059         * configure: Regenerate.
1060
1061 2019-01-07  Alan Modra  <amodra@gmail.com>
1062
1063         * configure: Regenerate.
1064         * po/POTFILES.in: Regenerate.
1065
1066 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1067
1068         * s12z-opc.c: New file.
1069         * s12z-opc.h: New file.
1070         * s12z-dis.c: Removed all code not directly related to display
1071         of instructions.  Used the interface provided by the new files
1072         instead.
1073         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1074         * Makefile.in: Regenerate.
1075         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1076         * configure: Regenerate.
1077
1078 2019-01-01  Alan Modra  <amodra@gmail.com>
1079
1080         Update year range in copyright notice of all files.
1081
1082 For older changes see ChangeLog-2018
1083 \f
1084 Copyright (C) 2019 Free Software Foundation, Inc.
1085
1086 Copying and distribution of this file, with or without modification,
1087 are permitted in any medium without royalty provided the copyright
1088 notice and this notice are preserved.
1089
1090 Local Variables:
1091 mode: change-log
1092 left-margin: 8
1093 fill-column: 74
1094 version-control: never
1095 End: