opcodes/ChangeLog

   1 2019-10-30  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_type_shorthands): Delete.
   4         (operand_type_init): Expand previous shorthands.
   5         (set_bitfield_from_shorthand): Rename back to ...
   6         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
   7         of operand_type_init[].
   8         (set_bitfield): Adjust call to the above function.
   9         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
  10         RegXMM, RegYMM, RegZMM): Define.
  11         * i386-reg.tbl: Expand prior shorthands.
  12
  13 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-gen.c (output_i386_opcode): Change order of fields
  16         emitted to output.
  17         * i386-opc.h (struct insn_template): Move operands field.
  18         Convert extension_opcode field to unsigned short.
  19         * i386-tbl.h: Re-generate.
  20
  21 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  22
  23         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
  24         of W.
  25         * i386-opc.h (W): Extend comment.
  26         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
  27         general purpose variants not allowing for byte operands.
  28         * i386-tbl.h: Re-generate.
  29
  30 2019-10-29  Nick Clifton  <nickc@redhat.com>
  31
  32         * tic30-dis.c (print_branch): Correct size of operand array.
  33
  34 2019-10-29  Nick Clifton  <nickc@redhat.com>
  35
  36         * d30v-dis.c (print_insn): Check that operand index is valid
  37         before attempting to access the operands array.
  38
  39 2019-10-29  Nick Clifton  <nickc@redhat.com>
  40
  41         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
  42         locating the bit to be tested.
  43
  44 2019-10-29  Nick Clifton  <nickc@redhat.com>
  45
  46         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
  47         values.
  48         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
  49         (print_insn_s12z):  Check for illegal size values.
  50
  51 2019-10-28  Nick Clifton  <nickc@redhat.com>
  52
  53         * csky-dis.c (csky_chars_to_number): Check for a negative
  54         count. Use an unsigned integer to construct the return value.
  55
  56 2019-10-28  Nick Clifton  <nickc@redhat.com>
  57
  58         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
  59         operand buffer.  Set value to 15 not 13.
  60         (get_register_operand): Use OPERAND_BUFFER_LEN.
  61         (get_indirect_operand): Likewise.
  62         (print_two_operand): Likewise.
  63         (print_three_operand): Likewise.
  64         (print_oar_insn): Likewise.
  65
  66 2019-10-28  Nick Clifton  <nickc@redhat.com>
  67
  68         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
  69         (bit_extract_simple): Likewise.
  70         (bit_copy): Likewise.
  71         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
  72         index_offset array are not accessed.
  73
  74 2019-10-28  Nick Clifton  <nickc@redhat.com>
  75
  76         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
  77         operand.
  78
  79 2019-10-25  Nick Clifton  <nickc@redhat.com>
  80
  81         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
  82         access to opcodes.op array element.
  83
  84 2019-10-23  Nick Clifton  <nickc@redhat.com>
  85
  86         * rx-dis.c (get_register_name): Fix spelling typo in error
  87         message.
  88         (get_condition_name, get_flag_name, get_double_register_name)
  89         (get_double_register_high_name, get_double_register_low_name)
  90         (get_double_control_register_name, get_double_condition_name)
  91         (get_opsize_name, get_size_name): Likewise.
  92
  93 2019-10-22  Nick Clifton  <nickc@redhat.com>
  94
  95         * rx-dis.c (get_size_name): New function.  Provides safe
  96         access to name array.
  97         (get_opsize_name): Likewise.
  98         (print_insn_rx): Use the accessor functions.
  99
 100 2019-10-16  Nick Clifton  <nickc@redhat.com>
 101
 102         * rx-dis.c (get_register_name): New function.  Provides safe
 103         access to name array.
 104         (get_condition_name, get_flag_name, get_double_register_name)
 105         (get_double_register_high_name, get_double_register_low_name)
 106         (get_double_control_register_name, get_double_condition_name):
 107         Likewise.
 108         (print_insn_rx): Use the accessor functions.
 109
 110 2019-10-09  Nick Clifton  <nickc@redhat.com>
 111
 112         PR 25041
 113         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 114         instructions.
 115
 116 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 117
 118         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 119         (cmpsd): Likewise. Move EsSeg to other operand.
 120         * opcodes/i386-tbl.h: Re-generate.
 121
 122 2019-09-23  Alan Modra  <amodra@gmail.com>
 123
 124         * m68k-dis.c: Include cpu-m68k.h
 125
 126 2019-09-23  Alan Modra  <amodra@gmail.com>
 127
 128         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 129         "elf/mips.h" earlier.
 130
 131 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 132
 133         PR gas/25012
 134         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 135         with SReg operand.
 136         * i386-tbl.h: Re-generate.
 137
 138 2019-09-18  Alan Modra  <amodra@gmail.com>
 139
 140         * arc-ext.c: Update throughout for bfd section macro changes.
 141
 142 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 143
 144         * Makefile.in: Re-generate.
 145         * configure: Re-generate.
 146
 147 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 148
 149         * riscv-opc.c (riscv_opcodes): Change subset field
 150         to insn_class field for all instructions.
 151         (riscv_insn_types): Likewise.
 152
 153 2019-09-16  Phil Blundell  <pb@pbcl.net>
 154
 155         * configure: Regenerated.
 156
 157 2019-09-10  Miod Vallat  <miod@online.fr>
 158
 159         PR 24982
 160         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 161
 162 2019-09-09  Phil Blundell  <pb@pbcl.net>
 163
 164         binutils 2.33 branch created.
 165
 166 2019-09-03  Nick Clifton  <nickc@redhat.com>
 167
 168         PR 24961
 169         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 170         greater than zero before indexing via (bufcnt -1).
 171
 172 2019-09-03  Nick Clifton  <nickc@redhat.com>
 173
 174         PR 24958
 175         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 176         (MAX_SPEC_REG_NAME_LEN): Define.
 177         (struct mmix_dis_info): Use defined constants for array lengths.
 178         (get_reg_name): New function.
 179         (get_sprec_reg_name): New function.
 180         (print_insn_mmix): Use new functions.
 181
 182 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 183
 184         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 185         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 186         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 187
 188 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 189
 190         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 191         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 192         (aarch64_sys_reg_supported_p): Update checks for the above.
 193
 194 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 195
 196         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 197         cases MVE_SQRSHRL and MVE_UQRSHLL.
 198         (print_insn_mve): Add case for specifier 'k' to check
 199         specific bit of the instruction.
 200
 201 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 202
 203         PR 24854
 204         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 205         encountering an unknown machine type.
 206         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 207         cases return -1 rather than calling abort.
 208
 209 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 210
 211         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 212         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 213         IgnoreSize.
 214         * i386-tbl.h: Re-generate.
 215
 216 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 217
 218         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 219         instructions.
 220
 221 2019-07-30  Mel Chen <mel.chen@sifive.com>
 222
 223         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 224         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 225
 226         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 227         fscsr.
 228
 229 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 230
 231         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 232         and MPY class instructions.
 233         (parse_option): Add nps400 option.
 234         (print_arc_disassembler_options): Add nps400 info.
 235
 236 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 237
 238         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 239         (bspop): Likewise.
 240         (modapp): Likewise.
 241         * arc-opc.c (RAD_CHK): Add.
 242         * arc-tbl.h: Regenerate.
 243
 244 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 245
 246         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 247         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 248
 249 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 250
 251         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 252         instructions as UNPREDICTABLE.
 253
 254 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 255
 256         * bpf-desc.c: Regenerated.
 257
 258 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-gen.c (static_assert): Define.
 261         (main): Use it.
 262         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 263         (Opcode_Modifier_Num): ... this.
 264         (Mem): Delete.
 265
 266 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-gen.c (operand_types): Move RegMem ...
 269         (opcode_modifiers): ... here.
 270         * i386-opc.h (RegMem): Move to opcode modifer enum.
 271         (union i386_operand_type): Move regmem field ...
 272         (struct i386_opcode_modifier): ... here.
 273         * i386-opc.tbl (RegMem): Define.
 274         (mov, movq): Move RegMem on segment, control, debug, and test
 275         register flavors.
 276         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 277         to non-SSE2AVX flavor.
 278         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 279         Move RegMem on register only flavors. Drop IgnoreSize from
 280         legacy encoding flavors.
 281         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 282         flavors.
 283         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 284         register only flavors.
 285         (vmovd): Move RegMem and drop IgnoreSize on register only
 286         flavor. Change opcode and operand order to store form.
 287         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 288
 289 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 292         entries.
 293         * i386-opc.h (SReg2, SReg3): Replace by ...
 294         (SReg): ... this.
 295         (union i386_operand_type): Replace sreg fields.
 296         * i386-opc.tbl (mov, ): Use SReg.
 297         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 298         register flavors.
 299         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 300         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 301
 302 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 303
 304         * bpf-desc.c: Regenerate.
 305         * bpf-opc.c: Likewise.
 306         * bpf-opc.h: Likewise.
 307
 308 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 309
 310         * bpf-desc.c: Regenerate.
 311         * bpf-opc.c: Likewise.
 312
 313 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 314
 315         * arm-dis.c (print_insn_coprocessor): Rename index to
 316         index_operand.
 317
 318 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 319
 320         * riscv-opc.c (riscv_insn_types): Add r4 type.
 321
 322         * riscv-opc.c (riscv_insn_types): Add b and j type.
 323
 324         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 325         format for sb type and correct s type.
 326
 327 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 328
 329         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 330         SVE FMOV alias of FCPY.
 331
 332 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 333
 334         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 335         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 336
 337 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 338
 339         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 340         registers in an instruction prefixed by MOVPRFX.
 341
 342 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 343
 344         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 345         sve_size_13 icode to account for variant behaviour of
 346         pmull{t,b}.
 347         * aarch64-dis-2.c: Regenerate.
 348         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 349         sve_size_13 icode to account for variant behaviour of
 350         pmull{t,b}.
 351         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 352         (OP_SVE_VVV_Q_D): Add new qualifier.
 353         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 354         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 355         AES and those not.
 356
 357 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 358
 359         * opcodes/i386-gen.c (operand_type_init): Remove
 360         OPERAND_TYPE_VEC_IMM4 entry.
 361         (operand_types): Remove Vec_Imm4.
 362         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 363         (union i386_operand_type): Remove vec_imm4.
 364         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 365         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 366
 367 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 370         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 371         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 372         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 373         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 374         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 375         * i386-tbl.h: Re-generate.
 376
 377 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 378
 379         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 380         register operands.
 381         * i386-tbl.h: Re-generate.
 382
 383 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 384
 385         * i386-opc.tbl (C): New.
 386         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 387         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 388         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 389         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 390         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 391         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 392         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 393         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 394         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 395         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 396         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 397         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 398         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 399         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 400         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 401         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 402         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 403         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 404         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 405         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 406         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 407         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 408         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 409         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 410         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 411         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 412         flavors.
 413         * i386-tbl.h: Re-generate.
 414
 415 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 418         register operands.
 419         * i386-tbl.h: Re-generate.
 420
 421 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 422
 423         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 424         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 425         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 426         * i386-tbl.h: Re-generate.
 427
 428 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 431         Disp8MemShift from register only templates.
 432         * i386-tbl.h: Re-generate.
 433
 434 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 435
 436         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 437         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 438         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 439         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 440         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 441         EVEX_W_0F11_P_3_M_1): Delete.
 442         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 443         EVEX_W_0F11_P_3): New.
 444         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 445         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 446         MOD_EVEX_0F11_PREFIX_3 table entries.
 447         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 448         PREFIX_EVEX_0F11 table entries.
 449         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 450         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 451         EVEX_W_0F11_P_3_M_{0,1} table entries.
 452
 453 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 456         Delete.
 457
 458 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         PR binutils/24719
 461         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 462         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 463         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 464         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 465         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 466         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 467         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 468         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 469         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 470         PREFIX_EVEX_0F38C6_REG_6 entries.
 471         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 472         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 473         EVEX_W_0F38C7_R_6_P_2 entries.
 474         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 475         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 476         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 477         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 478         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 479         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 480         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 481
 482 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 483
 484         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 485         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 486         VEX_LEN_0F2D_P_3): Delete.
 487         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 488         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 489         (prefix_table): ... here.
 490
 491 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-dis.c (Iq): Delete.
 494         (Id): New.
 495         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 496         TBM insns.
 497         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 498         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 499         (OP_E_memory): Also honor needindex when deciding whether an
 500         address size prefix needs printing.
 501         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 502
 503 2019-06-26  Jim Wilson  <jimw@sifive.com>
 504
 505         PR binutils/24739
 506         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 507         Set info->display_endian to info->endian_code.
 508
 509 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 510
 511         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 512         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 513         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 514         OPERAND_TYPE_ACC64 entries.
 515         * i386-init.h: Re-generate.
 516
 517 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 520         Delete.
 521         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 522         of dqa_mode.
 523         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 524         entries here.
 525         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 526         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 527
 528 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 529
 530         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 531         variables.
 532
 533 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 536         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 537         movnti.
 538         * i386-opc.tbl (movnti): Add IgnoreSize.
 539         * i386-tbl.h: Re-generate.
 540
 541 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 544         * i386-tbl.h: Re-generate.
 545
 546 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 547
 548         * i386-dis-evex.h: Break into ...
 549         * i386-dis-evex-len.h: New file.
 550         * i386-dis-evex-mod.h: Likewise.
 551         * i386-dis-evex-prefix.h: Likewise.
 552         * i386-dis-evex-reg.h: Likewise.
 553         * i386-dis-evex-w.h: Likewise.
 554         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 555         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 556         i386-dis-evex-mod.h.
 557
 558 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 559
 560         PR binutils/24700
 561         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 562         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 563         EVEX_W_0F385B_P_2.
 564         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 565         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 566         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 567         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 568         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 569         EVEX_LEN_0F385B_P_2_W_1.
 570         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 571         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 572         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 573         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 574         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 575         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 576         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 577         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 578         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 579         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 580
 581 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 582
 583         PR binutils/24691
 584         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 585         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 586         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 587         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 588         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 589         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 590         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 591         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 592         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 593         EVEX_LEN_0F3A43_P_2_W_1.
 594         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 595         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 596         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 597         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 598         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 599         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 600         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 601         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 602         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 603         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 604         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 605         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 606
 607 2019-06-14  Nick Clifton  <nickc@redhat.com>
 608
 609         * po/fr.po; Updated French translation.
 610
 611 2019-06-13  Stafford Horne  <shorne@gmail.com>
 612
 613         * or1k-asm.c: Regenerated.
 614         * or1k-desc.c: Regenerated.
 615         * or1k-desc.h: Regenerated.
 616         * or1k-dis.c: Regenerated.
 617         * or1k-ibld.c: Regenerated.
 618         * or1k-opc.c: Regenerated.
 619         * or1k-opc.h: Regenerated.
 620         * or1k-opinst.c: Regenerated.
 621
 622 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 623
 624         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 625
 626 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 627
 628         PR binutils/24633
 629         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 630         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 631         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 632         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 633         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 634         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 635         EVEX_LEN_0F3A1B_P_2_W_1.
 636         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 637         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 638         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 639         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 640         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 641         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 642         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 643         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 644
 645 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 646
 647         PR binutils/24626
 648         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 649         EVEX.vvvv when disassembling VEX and EVEX instructions.
 650         (OP_VEX): Set vex.register_specifier to 0 after readding
 651         vex.register_specifier.
 652         (OP_Vex_2src_1): Likewise.
 653         (OP_Vex_2src_2): Likewise.
 654         (OP_LWP_E): Likewise.
 655         (OP_EX_Vex): Don't check vex.register_specifier.
 656         (OP_XMM_Vex): Likewise.
 657
 658 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 659             Lili Cui  <lili.cui@intel.com>
 660
 661         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 662         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 663         instructions.
 664         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 665         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 666         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 667         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 668         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 669         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 670         * i386-init.h: Regenerated.
 671         * i386-tbl.h: Likewise.
 672
 673 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 674             Lili Cui  <lili.cui@intel.com>
 675
 676         * doc/c-i386.texi: Document enqcmd.
 677         * testsuite/gas/i386/enqcmd-intel.d: New file.
 678         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 679         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 680         * testsuite/gas/i386/enqcmd.d: Likewise.
 681         * testsuite/gas/i386/enqcmd.s: Likewise.
 682         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 683         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 684         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 685         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 686         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 687         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 688         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 689         and x86-64-enqcmd.
 690
 691 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 692
 693         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 694
 695 2019-06-03  Alan Modra  <amodra@gmail.com>
 696
 697         * ppc-dis.c (prefix_opcd_indices): Correct size.
 698
 699 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 700
 701         PR gas/24625
 702         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 703         Disp8ShiftVL.
 704         * i386-tbl.h: Regenerated.
 705
 706 2019-05-24  Alan Modra  <amodra@gmail.com>
 707
 708         * po/POTFILES.in: Regenerate.
 709
 710 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 711             Alan Modra  <amodra@gmail.com>
 712
 713         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 714         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 715         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 716         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 717         XTOP>): Define and add entries.
 718         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 719         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 720         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 721         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 722
 723 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 724             Alan Modra  <amodra@gmail.com>
 725
 726         * ppc-dis.c (ppc_opts): Add "future" entry.
 727         (PREFIX_OPCD_SEGS): Define.
 728         (prefix_opcd_indices): New array.
 729         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 730         (lookup_prefix): New function.
 731         (print_insn_powerpc): Handle 64-bit prefix instructions.
 732         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 733         (PMRR, POWERXX): Define.
 734         (prefix_opcodes): New instruction table.
 735         (prefix_num_opcodes): New constant.
 736
 737 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 738
 739         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 740         * configure: Regenerated.
 741         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 742         and cpu/bpf.opc.
 743         (HFILES): Add bpf-desc.h and bpf-opc.h.
 744         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 745         bpf-ibld.c and bpf-opc.c.
 746         (BPF_DEPS): Define.
 747         * Makefile.in: Regenerated.
 748         * disassemble.c (ARCH_bpf): Define.
 749         (disassembler): Add case for bfd_arch_bpf.
 750         (disassemble_init_for_target): Likewise.
 751         (enum epbf_isa_attr): Define.
 752         * disassemble.h: extern print_insn_bpf.
 753         * bpf-asm.c: Generated.
 754         * bpf-opc.h: Likewise.
 755         * bpf-opc.c: Likewise.
 756         * bpf-ibld.c: Likewise.
 757         * bpf-dis.c: Likewise.
 758         * bpf-desc.h: Likewise.
 759         * bpf-desc.c: Likewise.
 760
 761 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 762
 763         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 764         and VMSR with the new operands.
 765
 766 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 767
 768         * arm-dis.c (enum mve_instructions): New enum
 769         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 770         and cneg.
 771         (mve_opcodes): New instructions as above.
 772         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 773         csneg and csel.
 774         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 775
 776 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 777
 778         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 779         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 780         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 781         uqshl, urshrl and urshr.
 782         (is_mve_okay_in_it): Add new instructions to TRUE list.
 783         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 784         (print_insn_mve): Updated to accept new %j,
 785         %<bitfield>m and %<bitfield>n patterns.
 786
 787 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 788
 789         * mips-opc.c (mips_builtin_opcodes): Change source register
 790         constraint for DAUI.
 791
 792 2019-05-20  Nick Clifton  <nickc@redhat.com>
 793
 794         * po/fr.po: Updated French translation.
 795
 796 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 797             Michael Collison <michael.collison@arm.com>
 798
 799         * arm-dis.c (thumb32_opcodes): Add new instructions.
 800         (enum mve_instructions): Likewise.
 801         (enum mve_undefined): Add new reasons.
 802         (is_mve_encoding_conflict): Handle new instructions.
 803         (is_mve_undefined): Likewise.
 804         (is_mve_unpredictable): Likewise.
 805         (print_mve_undefined): Likewise.
 806         (print_mve_size): Likewise.
 807
 808 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 809             Michael Collison <michael.collison@arm.com>
 810
 811         * arm-dis.c (thumb32_opcodes): Add new instructions.
 812         (enum mve_instructions): Likewise.
 813         (is_mve_encoding_conflict): Handle new instructions.
 814         (is_mve_undefined): Likewise.
 815         (is_mve_unpredictable): Likewise.
 816         (print_mve_size): Likewise.
 817
 818 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 819             Michael Collison <michael.collison@arm.com>
 820
 821         * arm-dis.c (thumb32_opcodes): Add new instructions.
 822         (enum mve_instructions): Likewise.
 823         (is_mve_encoding_conflict): Likewise.
 824         (is_mve_unpredictable): Likewise.
 825         (print_mve_size): Likewise.
 826
 827 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 828             Michael Collison <michael.collison@arm.com>
 829
 830         * arm-dis.c (thumb32_opcodes): Add new instructions.
 831         (enum mve_instructions): Likewise.
 832         (is_mve_encoding_conflict): Handle new instructions.
 833         (is_mve_undefined): Likewise.
 834         (is_mve_unpredictable): Likewise.
 835         (print_mve_size): Likewise.
 836
 837 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 838             Michael Collison <michael.collison@arm.com>
 839
 840         * arm-dis.c (thumb32_opcodes): Add new instructions.
 841         (enum mve_instructions): Likewise.
 842         (is_mve_encoding_conflict): Handle new instructions.
 843         (is_mve_undefined): Likewise.
 844         (is_mve_unpredictable): Likewise.
 845         (print_mve_size): Likewise.
 846         (print_insn_mve): Likewise.
 847
 848 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 849             Michael Collison <michael.collison@arm.com>
 850
 851         * arm-dis.c (thumb32_opcodes): Add new instructions.
 852         (print_insn_thumb32): Handle new instructions.
 853
 854 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 855             Michael Collison <michael.collison@arm.com>
 856
 857         * arm-dis.c (enum mve_instructions): Add new instructions.
 858         (enum mve_undefined): Add new reasons.
 859         (is_mve_encoding_conflict): Handle new instructions.
 860         (is_mve_undefined): Likewise.
 861         (is_mve_unpredictable): Likewise.
 862         (print_mve_undefined): Likewise.
 863         (print_mve_size): Likewise.
 864         (print_mve_shift_n): Likewise.
 865         (print_insn_mve): Likewise.
 866
 867 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 868             Michael Collison <michael.collison@arm.com>
 869
 870         * arm-dis.c (enum mve_instructions): Add new instructions.
 871         (is_mve_encoding_conflict): Handle new instructions.
 872         (is_mve_unpredictable): Likewise.
 873         (print_mve_rotate): Likewise.
 874         (print_mve_size): Likewise.
 875         (print_insn_mve): Likewise.
 876
 877 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 878             Michael Collison <michael.collison@arm.com>
 879
 880         * arm-dis.c (enum mve_instructions): Add new instructions.
 881         (is_mve_encoding_conflict): Handle new instructions.
 882         (is_mve_unpredictable): Likewise.
 883         (print_mve_size): Likewise.
 884         (print_insn_mve): Likewise.
 885
 886 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 887             Michael Collison <michael.collison@arm.com>
 888
 889         * arm-dis.c (enum mve_instructions): Add new instructions.
 890         (enum mve_undefined): Add new reasons.
 891         (is_mve_encoding_conflict): Handle new instructions.
 892         (is_mve_undefined): Likewise.
 893         (is_mve_unpredictable): Likewise.
 894         (print_mve_undefined): Likewise.
 895         (print_mve_size): Likewise.
 896         (print_insn_mve): Likewise.
 897
 898 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 899             Michael Collison <michael.collison@arm.com>
 900
 901         * arm-dis.c (enum mve_instructions): Add new instructions.
 902         (is_mve_encoding_conflict): Handle new instructions.
 903         (is_mve_undefined): Likewise.
 904         (is_mve_unpredictable): Likewise.
 905         (print_mve_size): Likewise.
 906         (print_insn_mve): Likewise.
 907
 908 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 909             Michael Collison <michael.collison@arm.com>
 910
 911         * arm-dis.c (enum mve_instructions): Add new instructions.
 912         (enum mve_unpredictable): Add new reasons.
 913         (enum mve_undefined): Likewise.
 914         (is_mve_okay_in_it): Handle new isntructions.
 915         (is_mve_encoding_conflict): Likewise.
 916         (is_mve_undefined): Likewise.
 917         (is_mve_unpredictable): Likewise.
 918         (print_mve_vmov_index): Likewise.
 919         (print_simd_imm8): Likewise.
 920         (print_mve_undefined): Likewise.
 921         (print_mve_unpredictable): Likewise.
 922         (print_mve_size): Likewise.
 923         (print_insn_mve): Likewise.
 924
 925 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 926             Michael Collison <michael.collison@arm.com>
 927
 928         * arm-dis.c (enum mve_instructions): Add new instructions.
 929         (enum mve_unpredictable): Add new reasons.
 930         (enum mve_undefined): Likewise.
 931         (is_mve_encoding_conflict): Handle new instructions.
 932         (is_mve_undefined): Likewise.
 933         (is_mve_unpredictable): Likewise.
 934         (print_mve_undefined): Likewise.
 935         (print_mve_unpredictable): Likewise.
 936         (print_mve_rounding_mode): Likewise.
 937         (print_mve_vcvt_size): Likewise.
 938         (print_mve_size): Likewise.
 939         (print_insn_mve): Likewise.
 940
 941 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 942             Michael Collison <michael.collison@arm.com>
 943
 944         * arm-dis.c (enum mve_instructions): Add new instructions.
 945         (enum mve_unpredictable): Add new reasons.
 946         (enum mve_undefined): Likewise.
 947         (is_mve_undefined): Handle new instructions.
 948         (is_mve_unpredictable): Likewise.
 949         (print_mve_undefined): Likewise.
 950         (print_mve_unpredictable): Likewise.
 951         (print_mve_size): Likewise.
 952         (print_insn_mve): Likewise.
 953
 954 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 955             Michael Collison <michael.collison@arm.com>
 956
 957         * arm-dis.c (enum mve_instructions): Add new instructions.
 958         (enum mve_undefined): Add new reasons.
 959         (insns): Add new instructions.
 960         (is_mve_encoding_conflict):
 961         (print_mve_vld_str_addr): New print function.
 962         (is_mve_undefined): Handle new instructions.
 963         (is_mve_unpredictable): Likewise.
 964         (print_mve_undefined): Likewise.
 965         (print_mve_size): Likewise.
 966         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 967         (print_insn_mve):  Handle new operands.
 968
 969 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 970             Michael Collison <michael.collison@arm.com>
 971
 972         * arm-dis.c (enum mve_instructions): Add new instructions.
 973         (enum mve_unpredictable): Add new reasons.
 974         (is_mve_encoding_conflict): Handle new instructions.
 975         (is_mve_unpredictable): Likewise.
 976         (mve_opcodes): Add new instructions.
 977         (print_mve_unpredictable): Handle new reasons.
 978         (print_mve_register_blocks): New print function.
 979         (print_mve_size): Handle new instructions.
 980         (print_insn_mve): Likewise.
 981
 982 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 983             Michael Collison <michael.collison@arm.com>
 984
 985         * arm-dis.c (enum mve_instructions): Add new instructions.
 986         (enum mve_unpredictable): Add new reasons.
 987         (enum mve_undefined): Likewise.
 988         (is_mve_encoding_conflict): Handle new instructions.
 989         (is_mve_undefined): Likewise.
 990         (is_mve_unpredictable): Likewise.
 991         (coprocessor_opcodes): Move NEON VDUP from here...
 992         (neon_opcodes): ... to here.
 993         (mve_opcodes): Add new instructions.
 994         (print_mve_undefined):  Handle new reasons.
 995         (print_mve_unpredictable): Likewise.
 996         (print_mve_size): Handle new instructions.
 997         (print_insn_neon): Handle vdup.
 998         (print_insn_mve): Handle new operands.
 999
1000 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1001             Michael Collison <michael.collison@arm.com>
1002
1003         * arm-dis.c (enum mve_instructions): Add new instructions.
1004         (enum mve_unpredictable): Add new values.
1005         (mve_opcodes): Add new instructions.
1006         (vec_condnames): New array with vector conditions.
1007         (mve_predicatenames): New array with predicate suffixes.
1008         (mve_vec_sizename): New array with vector sizes.
1009         (enum vpt_pred_state): New enum with vector predication states.
1010         (struct vpt_block): New struct type for vpt blocks.
1011         (vpt_block_state): Global struct to keep track of state.
1012         (mve_extract_pred_mask): New helper function.
1013         (num_instructions_vpt_block): Likewise.
1014         (mark_outside_vpt_block): Likewise.
1015         (mark_inside_vpt_block): Likewise.
1016         (invert_next_predicate_state): Likewise.
1017         (update_next_predicate_state): Likewise.
1018         (update_vpt_block_state): Likewise.
1019         (is_vpt_instruction): Likewise.
1020         (is_mve_encoding_conflict): Add entries for new instructions.
1021         (is_mve_unpredictable): Likewise.
1022         (print_mve_unpredictable): Handle new cases.
1023         (print_instruction_predicate): Likewise.
1024         (print_mve_size): New function.
1025         (print_vec_condition): New function.
1026         (print_insn_mve): Handle vpt blocks and new print operands.
1027
1028 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1029
1030         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1031         8, 14 and 15 for Armv8.1-M Mainline.
1032
1033 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1034             Michael Collison <michael.collison@arm.com>
1035
1036         * arm-dis.c (enum mve_instructions): New enum.
1037         (enum mve_unpredictable): Likewise.
1038         (enum mve_undefined): Likewise.
1039         (struct mopcode32): New struct.
1040         (is_mve_okay_in_it): New function.
1041         (is_mve_architecture): Likewise.
1042         (arm_decode_field): Likewise.
1043         (arm_decode_field_multiple): Likewise.
1044         (is_mve_encoding_conflict): Likewise.
1045         (is_mve_undefined): Likewise.
1046         (is_mve_unpredictable): Likewise.
1047         (print_mve_undefined): Likewise.
1048         (print_mve_unpredictable): Likewise.
1049         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1050         (print_insn_mve): New function.
1051         (print_insn_thumb32): Handle MVE architecture.
1052         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1053
1054 2019-05-10  Nick Clifton  <nickc@redhat.com>
1055
1056         PR 24538
1057         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1058         end of the table prematurely.
1059
1060 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1061
1062         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1063         macros for R6.
1064
1065 2019-05-11  Alan Modra  <amodra@gmail.com>
1066
1067         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1068         when -Mraw is in effect.
1069
1070 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1071
1072         * aarch64-dis-2.c: Regenerate.
1073         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1074         (OP_SVE_BBB): New variant set.
1075         (OP_SVE_DDDD): New variant set.
1076         (OP_SVE_HHH): New variant set.
1077         (OP_SVE_HHHU): New variant set.
1078         (OP_SVE_SSS): New variant set.
1079         (OP_SVE_SSSU): New variant set.
1080         (OP_SVE_SHH): New variant set.
1081         (OP_SVE_SBBU): New variant set.
1082         (OP_SVE_DSS): New variant set.
1083         (OP_SVE_DHHU): New variant set.
1084         (OP_SVE_VMV_HSD_BHS): New variant set.
1085         (OP_SVE_VVU_HSD_BHS): New variant set.
1086         (OP_SVE_VVVU_SD_BH): New variant set.
1087         (OP_SVE_VVVU_BHSD): New variant set.
1088         (OP_SVE_VVV_QHD_DBS): New variant set.
1089         (OP_SVE_VVV_HSD_BHS): New variant set.
1090         (OP_SVE_VVV_HSD_BHS2): New variant set.
1091         (OP_SVE_VVV_BHS_HSD): New variant set.
1092         (OP_SVE_VV_BHS_HSD): New variant set.
1093         (OP_SVE_VVV_SD): New variant set.
1094         (OP_SVE_VVU_BHS_HSD): New variant set.
1095         (OP_SVE_VZVV_SD): New variant set.
1096         (OP_SVE_VZVV_BH): New variant set.
1097         (OP_SVE_VZV_SD): New variant set.
1098         (aarch64_opcode_table): Add sve2 instructions.
1099
1100 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1101
1102         * aarch64-asm-2.c: Regenerated.
1103         * aarch64-dis-2.c: Regenerated.
1104         * aarch64-opc-2.c: Regenerated.
1105         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1106         for SVE_SHLIMM_UNPRED_22.
1107         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1108         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1109         operand.
1110
1111 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1112
1113         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1114         sve_size_tsz_bhs iclass encode.
1115         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1116         sve_size_tsz_bhs iclass decode.
1117
1118 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1119
1120         * aarch64-asm-2.c: Regenerated.
1121         * aarch64-dis-2.c: Regenerated.
1122         * aarch64-opc-2.c: Regenerated.
1123         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1124         for SVE_Zm4_11_INDEX.
1125         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1126         (fields): Handle SVE_i2h field.
1127         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1128         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1129
1130 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1131
1132         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1133         sve_shift_tsz_bhsd iclass encode.
1134         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1135         sve_shift_tsz_bhsd iclass decode.
1136
1137 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1138
1139         * aarch64-asm-2.c: Regenerated.
1140         * aarch64-dis-2.c: Regenerated.
1141         * aarch64-opc-2.c: Regenerated.
1142         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1143         (aarch64_encode_variant_using_iclass): Handle
1144         sve_shift_tsz_hsd iclass encode.
1145         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1146         sve_shift_tsz_hsd iclass decode.
1147         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1148         for SVE_SHRIMM_UNPRED_22.
1149         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1150         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1151         operand.
1152
1153 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1154
1155         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1156         sve_size_013 iclass encode.
1157         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1158         sve_size_013 iclass decode.
1159
1160 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1161
1162         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1163         sve_size_bh iclass encode.
1164         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1165         sve_size_bh iclass decode.
1166
1167 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1168
1169         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1170         sve_size_sd2 iclass encode.
1171         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1172         sve_size_sd2 iclass decode.
1173         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1174         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1175
1176 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1177
1178         * aarch64-asm-2.c: Regenerated.
1179         * aarch64-dis-2.c: Regenerated.
1180         * aarch64-opc-2.c: Regenerated.
1181         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1182         for SVE_ADDR_ZX.
1183         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1184         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1185
1186 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1187
1188         * aarch64-asm-2.c: Regenerated.
1189         * aarch64-dis-2.c: Regenerated.
1190         * aarch64-opc-2.c: Regenerated.
1191         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1192         for SVE_Zm3_11_INDEX.
1193         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1194         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1195         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1196         fields.
1197         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1198
1199 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1200
1201         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1202         sve_size_hsd2 iclass encode.
1203         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1204         sve_size_hsd2 iclass decode.
1205         * aarch64-opc.c (fields): Handle SVE_size field.
1206         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1207
1208 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1209
1210         * aarch64-asm-2.c: Regenerated.
1211         * aarch64-dis-2.c: Regenerated.
1212         * aarch64-opc-2.c: Regenerated.
1213         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1214         for SVE_IMM_ROT3.
1215         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1216         (fields): Handle SVE_rot3 field.
1217         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1218         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1219
1220 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1221
1222         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1223         instructions.
1224
1225 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1226
1227         * aarch64-tbl.h
1228         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1229         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1230         aarch64_feature_sve2bitperm): New feature sets.
1231         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1232         for feature set addresses.
1233         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1234         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1235
1236 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1237             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1238
1239         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1240         argument and set ASE_EVA_R6 appropriately.
1241         (set_default_mips_dis_options): Pass ISA to above.
1242         (parse_mips_dis_option): Likewise.
1243         * mips-opc.c (EVAR6): New macro.
1244         (mips_builtin_opcodes): Add llwpe, scwpe.
1245
1246 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1247
1248         * aarch64-asm-2.c: Regenerated.
1249         * aarch64-dis-2.c: Regenerated.
1250         * aarch64-opc-2.c: Regenerated.
1251         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1252         AARCH64_OPND_TME_UIMM16.
1253         (aarch64_print_operand): Likewise.
1254         * aarch64-tbl.h (QL_IMM_NIL): New.
1255         (TME): New.
1256         (_TME_INSN): New.
1257         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1258
1259 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1260
1261         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1262
1263 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1264             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1265
1266         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1267
1268 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1269
1270         * s12z-opc.h: Add extern "C" bracketing to help
1271         users who wish to use this interface in c++ code.
1272
1273 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1274
1275         * s12z-opc.c (bm_decode): Handle bit map operations with the
1276         "reserved0" mode.
1277
1278 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1279
1280         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1281         specifier.  Add entries for VLDR and VSTR of system registers.
1282         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1283         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1284         of %J and %K format specifier.
1285
1286 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1287
1288         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1289         Add new entries for VSCCLRM instruction.
1290         (print_insn_coprocessor): Handle new %C format control code.
1291
1292 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1293
1294         * arm-dis.c (enum isa): New enum.
1295         (struct sopcode32): New structure.
1296         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1297         set isa field of all current entries to ANY.
1298         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1299         Only match an entry if its isa field allows the current mode.
1300
1301 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1302
1303         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1304         CLRM.
1305         (print_insn_thumb32): Add logic to print %n CLRM register list.
1306
1307 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1308
1309         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1310         and %Q patterns.
1311
1312 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1313
1314         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1315         (print_insn_thumb32): Edit the switch case for %Z.
1316
1317 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1318
1319         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1320
1321 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1322
1323         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1324
1325 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1326
1327         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1328
1329 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1330
1331         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1332         Arm register with r13 and r15 unpredictable.
1333         (thumb32_opcodes): New instructions for bfx and bflx.
1334
1335 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1336
1337         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1338
1339 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1340
1341         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1342
1343 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1344
1345         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1346
1347 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1348
1349         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1350
1351 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1352
1353         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1354         "optr". ("operator" is a reserved word in c++).
1355
1356 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1357
1358         * aarch64-opc.c (aarch64_print_operand): Add case for
1359         AARCH64_OPND_Rt_SP.
1360         (verify_constraints): Likewise.
1361         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1362         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1363         to accept Rt|SP as first operand.
1364         (AARCH64_OPERANDS): Add new Rt_SP.
1365         * aarch64-asm-2.c: Regenerated.
1366         * aarch64-dis-2.c: Regenerated.
1367         * aarch64-opc-2.c: Regenerated.
1368
1369 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1370
1371         * aarch64-asm-2.c: Regenerated.
1372         * aarch64-dis-2.c: Likewise.
1373         * aarch64-opc-2.c: Likewise.
1374         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1375
1376 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1377
1378         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1379
1380 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1381
1382         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1383         * i386-init.h: Regenerated.
1384
1385 2019-04-07  Alan Modra  <amodra@gmail.com>
1386
1387         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1388         op_separator to control printing of spaces, comma and parens
1389         rather than need_comma, need_paren and spaces vars.
1390
1391 2019-04-07  Alan Modra  <amodra@gmail.com>
1392
1393         PR 24421
1394         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1395         (print_insn_neon, print_insn_arm): Likewise.
1396
1397 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1398
1399         * i386-dis-evex.h (evex_table): Updated to support BF16
1400         instructions.
1401         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1402         and EVEX_W_0F3872_P_3.
1403         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1404         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1405         * i386-opc.h (enum): Add CpuAVX512_BF16.
1406         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1407         * i386-opc.tbl: Add AVX512 BF16 instructions.
1408         * i386-init.h: Regenerated.
1409         * i386-tbl.h: Likewise.
1410
1411 2019-04-05  Alan Modra  <amodra@gmail.com>
1412
1413         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1414         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1415         to favour printing of "-" branch hint when using the "y" bit.
1416         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1417
1418 2019-04-05  Alan Modra  <amodra@gmail.com>
1419
1420         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1421         opcode until first operand is output.
1422
1423 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1424
1425         PR gas/24349
1426         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1427         (valid_bo_post_v2): Add support for 'at' branch hints.
1428         (insert_bo): Only error on branch on ctr.
1429         (get_bo_hint_mask): New function.
1430         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1431         for inserting 'at' branch hints.
1432         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1433         for extracting 'at' branch hints.
1434         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1435         (BOE): Delete operand.
1436         (BOM, BOP): New operands.
1437         (RM): Update value.
1438         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1439         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1440         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1441         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1442         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1443         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1444         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1445         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1446         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1447         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1448         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1449         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1450         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1451         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1452         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1453         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1454         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1455         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1456         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1457         bttarl+>: New extended mnemonics.
1458
1459 2019-03-28  Alan Modra  <amodra@gmail.com>
1460
1461         PR 24390
1462         * ppc-opc.c (BTF): Define.
1463         (powerpc_opcodes): Use for mtfsb*.
1464         * ppc-dis.c (print_insn_powerpc): Print fields with both
1465         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1466
1467 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1468
1469         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1470         (mapping_symbol_for_insn): Implement new algorithm.
1471         (print_insn): Remove duplicate code.
1472
1473 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1474
1475         * aarch64-dis.c (print_insn_aarch64):
1476         Implement override.
1477
1478 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1479
1480         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1481         order.
1482
1483 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1484
1485         * aarch64-dis.c (last_stop_offset): New.
1486         (print_insn_aarch64): Use stop_offset.
1487
1488 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1489
1490         PR gas/24359
1491         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1492         CPU_ANY_AVX2_FLAGS.
1493         * i386-init.h: Regenerated.
1494
1495 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1496
1497         PR gas/24348
1498         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1499         vmovdqu16, vmovdqu32 and vmovdqu64.
1500         * i386-tbl.h: Regenerated.
1501
1502 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1503
1504         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1505         from vstrszb, vstrszh, and vstrszf.
1506
1507 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1508
1509         * s390-opc.txt: Add instruction descriptions.
1510
1511 2019-02-08  Jim Wilson  <jimw@sifive.com>
1512
1513         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1514         <bne>: Likewise.
1515
1516 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1517
1518         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1519
1520 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1521
1522         PR binutils/23212
1523         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1524         * aarch64-opc.c (verify_elem_sd): New.
1525         (fields): Add FLD_sz entr.
1526         * aarch64-tbl.h (_SIMD_INSN): New.
1527         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1528         fmulx scalar and vector by element isns.
1529
1530 2019-02-07  Nick Clifton  <nickc@redhat.com>
1531
1532         * po/sv.po: Updated Swedish translation.
1533
1534 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1535
1536         * s390-mkopc.c (main): Accept arch13 as cpu string.
1537         * s390-opc.c: Add new instruction formats and instruction opcode
1538         masks.
1539         * s390-opc.txt: Add new arch13 instructions.
1540
1541 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1542
1543         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1544         (aarch64_opcode): Change encoding for stg, stzg
1545         st2g and st2zg.
1546         * aarch64-asm-2.c: Regenerated.
1547         * aarch64-dis-2.c: Regenerated.
1548         * aarch64-opc-2.c: Regenerated.
1549
1550 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1551
1552         * aarch64-asm-2.c: Regenerated.
1553         * aarch64-dis-2.c: Likewise.
1554         * aarch64-opc-2.c: Likewise.
1555         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1556
1557 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1558             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1559
1560         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1561         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1562         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1563         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1564         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1565         case for ldstgv_indexed.
1566         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1567         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1568         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1569         * aarch64-asm-2.c: Regenerated.
1570         * aarch64-dis-2.c: Regenerated.
1571         * aarch64-opc-2.c: Regenerated.
1572
1573 2019-01-23  Nick Clifton  <nickc@redhat.com>
1574
1575         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1576
1577 2019-01-21  Nick Clifton  <nickc@redhat.com>
1578
1579         * po/de.po: Updated German translation.
1580         * po/uk.po: Updated Ukranian translation.
1581
1582 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1583         * mips-dis.c (mips_arch_choices): Fix typo in
1584         gs464, gs464e and gs264e descriptors.
1585
1586 2019-01-19  Nick Clifton  <nickc@redhat.com>
1587
1588         * configure: Regenerate.
1589         * po/opcodes.pot: Regenerate.
1590
1591 2018-06-24  Nick Clifton  <nickc@redhat.com>
1592
1593         2.32 branch created.
1594
1595 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1596
1597         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1598         if it is null.
1599         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1600         zero.
1601
1602 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1603
1604         * configure: Regenerate.
1605
1606 2019-01-07  Alan Modra  <amodra@gmail.com>
1607
1608         * configure: Regenerate.
1609         * po/POTFILES.in: Regenerate.
1610
1611 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1612
1613         * s12z-opc.c: New file.
1614         * s12z-opc.h: New file.
1615         * s12z-dis.c: Removed all code not directly related to display
1616         of instructions.  Used the interface provided by the new files
1617         instead.
1618         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1619         * Makefile.in: Regenerate.
1620         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1621         * configure: Regenerate.
1622
1623 2019-01-01  Alan Modra  <amodra@gmail.com>
1624
1625         Update year range in copyright notice of all files.
1626
1627 For older changes see ChangeLog-2018
1628 \f
1629 Copyright (C) 2019 Free Software Foundation, Inc.
1630
1631 Copying and distribution of this file, with or without modification,
1632 are permitted in any medium without royalty provided the copyright
1633 notice and this notice are preserved.
1634
1635 Local Variables:
1636 mode: change-log
1637 left-margin: 8
1638 fill-column: 74
1639 version-control: never
1640 End: