opcodes/ChangeLog

   1 2021-03-11  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (putop): Drop need_vex check when also checking
   4         vex.evex.
   5         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
   6         checking vex.b.
   7
   8 2021-03-11  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
  11         checks. Move case label past broadcast check.
  12
  13 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  14
  15         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
  16         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
  17         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
  18         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
  19         EVEX_W_0F38C7_M_0_L_2): Delete.
  20         (REG_EVEX_0F38C7_M_0_L_2): New.
  21         (intel_operand_size): Handle VEX and EVEX the same for
  22         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
  23         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
  24         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
  25         vex_vsib_q_w_d_mode uses.
  26         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
  27         0F38A1, and 0F38A3 entries.
  28         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
  29         entry.
  30         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
  31         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
  32         0F38A3 entries.
  33
  34 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  35
  36         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
  37         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
  38         MOD_VEX_0FXOP_09_12): Rename to ...
  39         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
  40         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
  41         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
  42         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
  43         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
  44         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
  45         (reg_table): Adjust comments.
  46         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
  47         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
  48         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
  49         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
  50         (vex_len_table): Adjust opcode 0A_12 entry.
  51         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
  52         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
  53         (rm_table): Move hreset entry.
  54
  55 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  56
  57         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
  58         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
  59         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
  60         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
  61         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
  62         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
  63         (get_valid_dis386): Also handle 512-bit vector length when
  64         vectoring into vex_len_table[].
  65         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
  66         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
  67         entries.
  68         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
  69         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
  70         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
  71         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
  72         entries.
  73
  74 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  75
  76         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
  77         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
  78         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
  79         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
  80         entries.
  81         * i386-dis-evex-len.h (evex_len_table): Likewise.
  82         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
  83
  84 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  85
  86         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
  87         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
  88         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
  89         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
  90         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
  91         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
  92         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
  93         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
  94         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
  95         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
  96         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
  97         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
  98         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
  99         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 100         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 101         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 102         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 103         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 104         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 105         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 106         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 107         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 108         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 109         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 110         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 111         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 112         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 113         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 114         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 115         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 116         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 117         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 118         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 119         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 120         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 121         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 122         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 123         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 124         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 125         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 126         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 127         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 128         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 129         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 130         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 131         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 132         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 133         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 134         EVEX_W_0F3A43_L_n): New.
 135         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 136         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 137         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 138         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 139         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 140         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 141         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 142         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 143         0F385B, 0F38C6, and 0F38C7 entries.
 144         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 145         0F38C6 and 0F38C7.
 146         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 147         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 148         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 149         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 150
 151 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 152
 153         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 154         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 155         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 156         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 157         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 158         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 159         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 160         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 161         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 162         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 163         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 164         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 165         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 166         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 167         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 168         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 169         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 170         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 171         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 172         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 173         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 174         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 175         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 176         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 177         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 178         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 179         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 180         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 181         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 182         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 183         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 184         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 185         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 186         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 187         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 188         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 189         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 190         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 191         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 192         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 193         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 194         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 195         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 196         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 197         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 198         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 199         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 200         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 201         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 202         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 203         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 204         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 205         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 206         VEX_W_0F99_P_2_LEN_0): Delete.
 207         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 208         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 209         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 210         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 211         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 212         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 213         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 214         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 215         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 216         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 217         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 218         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 219         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 220         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 221         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 222         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 223         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 224         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 225         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 226         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 227         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 228         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 229         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 230         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 231         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 232         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 233         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 234         (prefix_table): No longer link to vex_len_table[] for opcodes
 235         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 236         0F92, 0F93, 0F98, and 0F99.
 237         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 238         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 239         0F98, and 0F99.
 240         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 241         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 242         0F98, and 0F99.
 243         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 244         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 245         0F98, and 0F99.
 246         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 247         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 248         0F98, and 0F99.
 249
 250 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 251
 252         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 253         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 254         REG_VEX_0F73_M_0 respectively.
 255         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 256         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 257         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 258         MOD_VEX_0F73_REG_7): Delete.
 259         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 260         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 261         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 262         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 263         PREFIX_VEX_0F3AF0_L_0 respectively.
 264         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 265         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 266         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 267         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 268         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 269         VEX_LEN_0F38F7): New.
 270         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 271         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 272         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 273         0F38F3.
 274         (prefix_table): No longer link to vex_len_table[] for opcodes
 275         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 276         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 277         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 278         0F38F6, 0F38F7, and 0F3AF0.
 279         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 280         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 281         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 282         0F73.
 283
 284 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 285
 286         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 287         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 288         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 289         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 290         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 291         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 292         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 293         73.
 294         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 295         0F72, and 0F73.
 296         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 297         0F73.
 298
 299 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 300
 301         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 302         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 303         (reg_table): Don't link to mod_table[] where not needed. Add
 304         PREFIX_IGNORED to nop entries.
 305         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 306         (mod_table): Add nop entries next to prefetch ones. Drop
 307         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 308         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 309         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 310         PREFIX_OPCODE from endbr* entries.
 311         (get_valid_dis386): Also consider entry's name when zapping
 312         vindex.
 313         (print_insn): Handle PREFIX_IGNORED.
 314
 315 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 316
 317         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 318         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 319         element.
 320         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 321         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 322         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 323         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 324         (struct i386_opcode_modifier): Delete notrackprefixok,
 325         islockable, hleprefixok, and repprefixok fields. Add prefixok
 326         field.
 327         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 328         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 329         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 330         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 331         Replace HLEPrefixOk.
 332         * opcodes/i386-tbl.h: Re-generate.
 333
 334 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 335
 336         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 337         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 338         64-bit form.
 339         * opcodes/i386-tbl.h: Re-generate.
 340
 341 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 344         for {} instead of {0}. Don't look for '0'.
 345         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 346         size specifiers.
 347
 348 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 349
 350         PR 27158
 351         * riscv-dis.c (print_insn_args): Updated encoding macros.
 352         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 353         (match_c_addi16sp): Updated encoding macros.
 354         (match_c_lui): Likewise.
 355         (match_c_lui_with_hint): Likewise.
 356         (match_c_addi4spn): Likewise.
 357         (match_c_slli): Likewise.
 358         (match_slli_as_c_slli): Likewise.
 359         (match_c_slli64): Likewise.
 360         (match_srxi_as_c_srxi): Likewise.
 361         (riscv_insn_types): Added .insn css/cl/cs.
 362
 363 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 364
 365         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 366         (default_priv_spec): Updated type to riscv_spec_class.
 367         (parse_riscv_dis_option): Updated.
 368         * riscv-opc.c: Moved stuff and make the file tidy.
 369
 370 2021-02-17  Alan Modra  <amodra@gmail.com>
 371
 372         * wasm32-dis.c: Include limits.h.
 373         (CHAR_BIT): Provide backup define.
 374         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 375         Correct signed overflow checking.
 376
 377 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 378
 379         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 380         * i386-tbl.h: Re-generate.
 381
 382 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 383
 384         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 385         Oword.
 386         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 387
 388 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 389
 390         * s390-mkopc.c (main): Accept arch14 as cpu string.
 391         * s390-opc.txt: Add new arch14 instructions.
 392
 393 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 394
 395         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 396         favour of LIBINTL.
 397         * configure: Regenerated.
 398
 399 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 400
 401         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 402         * tic54x-opc.c (regs): Rename to ...
 403         (tic54x_regs): ... this.
 404         (mmregs): Rename to ...
 405         (tic54x_mmregs): ... this.
 406         (condition_codes): Rename to ...
 407         (tic54x_condition_codes): ... this.
 408         (cc2_codes): Rename to ...
 409         (tic54x_cc2_codes): ... this.
 410         (cc3_codes): Rename to ...
 411         (tic54x_cc3_codes): ... this.
 412         (status_bits): Rename to ...
 413         (tic54x_status_bits): ... this.
 414         (misc_symbols): Rename to ...
 415         (tic54x_misc_symbols): ... this.
 416
 417 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 418
 419         * riscv-opc.c (MASK_RVB_IMM): Removed.
 420         (riscv_opcodes): Removed zb* instructions.
 421         (riscv_ext_version_table): Removed versions for zb*.
 422
 423 2021-01-26  Alan Modra  <amodra@gmail.com>
 424
 425         * i386-gen.c (parse_template): Ensure entire template_instance
 426         is initialised.
 427
 428 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 429
 430         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 431         (riscv_fpr_names_abi): Likewise.
 432         (riscv_opcodes): Likewise.
 433         (riscv_insn_types): Likewise.
 434
 435 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 436
 437         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 438
 439 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 440
 441         * riscv-dis.c: Comments tidy and improvement.
 442         * riscv-opc.c: Likewise.
 443
 444 2021-01-13  Alan Modra  <amodra@gmail.com>
 445
 446         * Makefile.in: Regenerate.
 447
 448 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 449
 450         PR binutils/26792
 451         * configure.ac: Use GNU_MAKE_JOBSERVER.
 452         * aclocal.m4: Regenerated.
 453         * configure: Likewise.
 454
 455 2021-01-12  Nick Clifton  <nickc@redhat.com>
 456
 457         * po/sr.po: Updated Serbian translation.
 458
 459 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 460
 461         PR ld/27173
 462         * configure: Regenerated.
 463
 464 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 465
 466         * aarch64-asm-2.c: Regenerate.
 467         * aarch64-dis-2.c: Likewise.
 468         * aarch64-opc-2.c: Likewise.
 469         * aarch64-opc.c (aarch64_print_operand):
 470         Delete handling of AARCH64_OPND_CSRE_CSR.
 471         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 472         (CSRE): Likewise.
 473         (_CSRE_INSN): Likewise.
 474         (aarch64_opcode_table): Delete csr.
 475
 476 2021-01-11  Nick Clifton  <nickc@redhat.com>
 477
 478         * po/de.po: Updated German translation.
 479         * po/fr.po: Updated French translation.
 480         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 481         * po/sv.po: Updated Swedish translation.
 482         * po/uk.po: Updated Ukranian translation.
 483
 484 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 485
 486         * configure: Regenerated.
 487
 488 2021-01-09  Nick Clifton  <nickc@redhat.com>
 489
 490         * configure: Regenerate.
 491         * po/opcodes.pot: Regenerate.
 492
 493 2021-01-09  Nick Clifton  <nickc@redhat.com>
 494
 495         * 2.36 release branch crated.
 496
 497 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 498
 499         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 500         (DW, (XRC_MASK): Define.
 501         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 502
 503 2021-01-09  Alan Modra  <amodra@gmail.com>
 504
 505         * configure: Regenerate.
 506
 507 2021-01-08  Nick Clifton  <nickc@redhat.com>
 508
 509         * po/sv.po: Updated Swedish translation.
 510
 511 2021-01-08  Nick Clifton  <nickc@redhat.com>
 512
 513         PR 27129
 514         * aarch64-dis.c (determine_disassembling_preference): Move call to
 515         aarch64_match_operands_constraint outside of the assertion.
 516         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 517         Replace with a return of FALSE.
 518
 519         PR 27139
 520         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 521         core system register.
 522
 523 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 524
 525         * configure: Regenerate.
 526
 527 2021-01-07  Nick Clifton  <nickc@redhat.com>
 528
 529         * po/fr.po: Updated French translation.
 530
 531 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 532
 533         * m68k-opc.c (chkl): Change minimum architecture requirement to
 534         m68020.
 535
 536 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 537
 538         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 539
 540 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 541             Jim Wilson  <jimw@sifive.com>
 542             Andrew Waterman  <andrew@sifive.com>
 543             Maxim Blinov  <maxim.blinov@embecosm.com>
 544             Kito Cheng  <kito.cheng@sifive.com>
 545             Nelson Chu  <nelson.chu@sifive.com>
 546
 547         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 548         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 549
 550 2021-01-01  Alan Modra  <amodra@gmail.com>
 551
 552         Update year range in copyright notice of all files.
 553
 554 For older changes see ChangeLog-2020
 555 \f
 556 Copyright (C) 2021 Free Software Foundation, Inc.
 557
 558 Copying and distribution of this file, with or without modification,
 559 are permitted in any medium without royalty provided the copyright
 560 notice and this notice are preserved.
 561
 562 Local Variables:
 563 mode: change-log
 564 left-margin: 8
 565 fill-column: 74
 566 version-control: never
 567 End: