opcodes/ChangeLog

   1 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
   2             Alan Modra  <amodra@gmail.com>
   3
   4         * ppc-dis.c (ppc_opts): Add "future" entry.
   5         (PREFIX_OPCD_SEGS): Define.
   6         (prefix_opcd_indices): New array.
   7         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
   8         (lookup_prefix): New function.
   9         (print_insn_powerpc): Handle 64-bit prefix instructions.
  10         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
  11         (PMRR, POWERXX): Define.
  12         (prefix_opcodes): New instruction table.
  13         (prefix_num_opcodes): New constant.
  14
  15 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  16
  17         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
  18         * configure: Regenerated.
  19         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
  20         and cpu/bpf.opc.
  21         (HFILES): Add bpf-desc.h and bpf-opc.h.
  22         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
  23         bpf-ibld.c and bpf-opc.c.
  24         (BPF_DEPS): Define.
  25         * Makefile.in: Regenerated.
  26         * disassemble.c (ARCH_bpf): Define.
  27         (disassembler): Add case for bfd_arch_bpf.
  28         (disassemble_init_for_target): Likewise.
  29         (enum epbf_isa_attr): Define.
  30         * disassemble.h: extern print_insn_bpf.
  31         * bpf-asm.c: Generated.
  32         * bpf-opc.h: Likewise.
  33         * bpf-opc.c: Likewise.
  34         * bpf-ibld.c: Likewise.
  35         * bpf-dis.c: Likewise.
  36         * bpf-desc.h: Likewise.
  37         * bpf-desc.c: Likewise.
  38
  39 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  40
  41         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
  42         and VMSR with the new operands.
  43
  44 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  45
  46         * arm-dis.c (enum mve_instructions): New enum
  47         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
  48         and cneg.
  49         (mve_opcodes): New instructions as above.
  50         (is_mve_encoding_conflict): Add cases for csinc, csinv,
  51         csneg and csel.
  52         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
  53
  54 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  55
  56         * arm-dis.c (emun mve_instructions): Updated for new instructions.
  57         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
  58         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
  59         uqshl, urshrl and urshr.
  60         (is_mve_okay_in_it): Add new instructions to TRUE list.
  61         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
  62         (print_insn_mve): Updated to accept new %j,
  63         %<bitfield>m and %<bitfield>n patterns.
  64
  65 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
  66
  67         * mips-opc.c (mips_builtin_opcodes): Change source register
  68         constraint for DAUI.
  69
  70 2019-05-20  Nick Clifton  <nickc@redhat.com>
  71
  72         * po/fr.po: Updated French translation.
  73
  74 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  75             Michael Collison <michael.collison@arm.com>
  76
  77         * arm-dis.c (thumb32_opcodes): Add new instructions.
  78         (enum mve_instructions): Likewise.
  79         (enum mve_undefined): Add new reasons.
  80         (is_mve_encoding_conflict): Handle new instructions.
  81         (is_mve_undefined): Likewise.
  82         (is_mve_unpredictable): Likewise.
  83         (print_mve_undefined): Likewise.
  84         (print_mve_size): Likewise.
  85
  86 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  87             Michael Collison <michael.collison@arm.com>
  88
  89         * arm-dis.c (thumb32_opcodes): Add new instructions.
  90         (enum mve_instructions): Likewise.
  91         (is_mve_encoding_conflict): Handle new instructions.
  92         (is_mve_undefined): Likewise.
  93         (is_mve_unpredictable): Likewise.
  94         (print_mve_size): Likewise.
  95
  96 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  97             Michael Collison <michael.collison@arm.com>
  98
  99         * arm-dis.c (thumb32_opcodes): Add new instructions.
 100         (enum mve_instructions): Likewise.
 101         (is_mve_encoding_conflict): Likewise.
 102         (is_mve_unpredictable): Likewise.
 103         (print_mve_size): Likewise.
 104
 105 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 106             Michael Collison <michael.collison@arm.com>
 107
 108         * arm-dis.c (thumb32_opcodes): Add new instructions.
 109         (enum mve_instructions): Likewise.
 110         (is_mve_encoding_conflict): Handle new instructions.
 111         (is_mve_undefined): Likewise.
 112         (is_mve_unpredictable): Likewise.
 113         (print_mve_size): Likewise.
 114
 115 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 116             Michael Collison <michael.collison@arm.com>
 117
 118         * arm-dis.c (thumb32_opcodes): Add new instructions.
 119         (enum mve_instructions): Likewise.
 120         (is_mve_encoding_conflict): Handle new instructions.
 121         (is_mve_undefined): Likewise.
 122         (is_mve_unpredictable): Likewise.
 123         (print_mve_size): Likewise.
 124         (print_insn_mve): Likewise.
 125
 126 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 127             Michael Collison <michael.collison@arm.com>
 128
 129         * arm-dis.c (thumb32_opcodes): Add new instructions.
 130         (print_insn_thumb32): Handle new instructions.
 131
 132 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 133             Michael Collison <michael.collison@arm.com>
 134
 135         * arm-dis.c (enum mve_instructions): Add new instructions.
 136         (enum mve_undefined): Add new reasons.
 137         (is_mve_encoding_conflict): Handle new instructions.
 138         (is_mve_undefined): Likewise.
 139         (is_mve_unpredictable): Likewise.
 140         (print_mve_undefined): Likewise.
 141         (print_mve_size): Likewise.
 142         (print_mve_shift_n): Likewise.
 143         (print_insn_mve): Likewise.
 144
 145 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 146             Michael Collison <michael.collison@arm.com>
 147
 148         * arm-dis.c (enum mve_instructions): Add new instructions.
 149         (is_mve_encoding_conflict): Handle new instructions.
 150         (is_mve_unpredictable): Likewise.
 151         (print_mve_rotate): Likewise.
 152         (print_mve_size): Likewise.
 153         (print_insn_mve): Likewise.
 154
 155 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 156             Michael Collison <michael.collison@arm.com>
 157
 158         * arm-dis.c (enum mve_instructions): Add new instructions.
 159         (is_mve_encoding_conflict): Handle new instructions.
 160         (is_mve_unpredictable): Likewise.
 161         (print_mve_size): Likewise.
 162         (print_insn_mve): Likewise.
 163
 164 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 165             Michael Collison <michael.collison@arm.com>
 166
 167         * arm-dis.c (enum mve_instructions): Add new instructions.
 168         (enum mve_undefined): Add new reasons.
 169         (is_mve_encoding_conflict): Handle new instructions.
 170         (is_mve_undefined): Likewise.
 171         (is_mve_unpredictable): Likewise.
 172         (print_mve_undefined): Likewise.
 173         (print_mve_size): Likewise.
 174         (print_insn_mve): Likewise.
 175
 176 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 177             Michael Collison <michael.collison@arm.com>
 178
 179         * arm-dis.c (enum mve_instructions): Add new instructions.
 180         (is_mve_encoding_conflict): Handle new instructions.
 181         (is_mve_undefined): Likewise.
 182         (is_mve_unpredictable): Likewise.
 183         (print_mve_size): Likewise.
 184         (print_insn_mve): Likewise.
 185
 186 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 187             Michael Collison <michael.collison@arm.com>
 188
 189         * arm-dis.c (enum mve_instructions): Add new instructions.
 190         (enum mve_unpredictable): Add new reasons.
 191         (enum mve_undefined): Likewise.
 192         (is_mve_okay_in_it): Handle new isntructions.
 193         (is_mve_encoding_conflict): Likewise.
 194         (is_mve_undefined): Likewise.
 195         (is_mve_unpredictable): Likewise.
 196         (print_mve_vmov_index): Likewise.
 197         (print_simd_imm8): Likewise.
 198         (print_mve_undefined): Likewise.
 199         (print_mve_unpredictable): Likewise.
 200         (print_mve_size): Likewise.
 201         (print_insn_mve): Likewise.
 202
 203 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 204             Michael Collison <michael.collison@arm.com>
 205
 206         * arm-dis.c (enum mve_instructions): Add new instructions.
 207         (enum mve_unpredictable): Add new reasons.
 208         (enum mve_undefined): Likewise.
 209         (is_mve_encoding_conflict): Handle new instructions.
 210         (is_mve_undefined): Likewise.
 211         (is_mve_unpredictable): Likewise.
 212         (print_mve_undefined): Likewise.
 213         (print_mve_unpredictable): Likewise.
 214         (print_mve_rounding_mode): Likewise.
 215         (print_mve_vcvt_size): Likewise.
 216         (print_mve_size): Likewise.
 217         (print_insn_mve): Likewise.
 218
 219 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 220             Michael Collison <michael.collison@arm.com>
 221
 222         * arm-dis.c (enum mve_instructions): Add new instructions.
 223         (enum mve_unpredictable): Add new reasons.
 224         (enum mve_undefined): Likewise.
 225         (is_mve_undefined): Handle new instructions.
 226         (is_mve_unpredictable): Likewise.
 227         (print_mve_undefined): Likewise.
 228         (print_mve_unpredictable): Likewise.
 229         (print_mve_size): Likewise.
 230         (print_insn_mve): Likewise.
 231
 232 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 233             Michael Collison <michael.collison@arm.com>
 234
 235         * arm-dis.c (enum mve_instructions): Add new instructions.
 236         (enum mve_undefined): Add new reasons.
 237         (insns): Add new instructions.
 238         (is_mve_encoding_conflict):
 239         (print_mve_vld_str_addr): New print function.
 240         (is_mve_undefined): Handle new instructions.
 241         (is_mve_unpredictable): Likewise.
 242         (print_mve_undefined): Likewise.
 243         (print_mve_size): Likewise.
 244         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 245         (print_insn_mve):  Handle new operands.
 246
 247 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 248             Michael Collison <michael.collison@arm.com>
 249
 250         * arm-dis.c (enum mve_instructions): Add new instructions.
 251         (enum mve_unpredictable): Add new reasons.
 252         (is_mve_encoding_conflict): Handle new instructions.
 253         (is_mve_unpredictable): Likewise.
 254         (mve_opcodes): Add new instructions.
 255         (print_mve_unpredictable): Handle new reasons.
 256         (print_mve_register_blocks): New print function.
 257         (print_mve_size): Handle new instructions.
 258         (print_insn_mve): Likewise.
 259
 260 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 261             Michael Collison <michael.collison@arm.com>
 262
 263         * arm-dis.c (enum mve_instructions): Add new instructions.
 264         (enum mve_unpredictable): Add new reasons.
 265         (enum mve_undefined): Likewise.
 266         (is_mve_encoding_conflict): Handle new instructions.
 267         (is_mve_undefined): Likewise.
 268         (is_mve_unpredictable): Likewise.
 269         (coprocessor_opcodes): Move NEON VDUP from here...
 270         (neon_opcodes): ... to here.
 271         (mve_opcodes): Add new instructions.
 272         (print_mve_undefined):  Handle new reasons.
 273         (print_mve_unpredictable): Likewise.
 274         (print_mve_size): Handle new instructions.
 275         (print_insn_neon): Handle vdup.
 276         (print_insn_mve): Handle new operands.
 277
 278 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 279             Michael Collison <michael.collison@arm.com>
 280
 281         * arm-dis.c (enum mve_instructions): Add new instructions.
 282         (enum mve_unpredictable): Add new values.
 283         (mve_opcodes): Add new instructions.
 284         (vec_condnames): New array with vector conditions.
 285         (mve_predicatenames): New array with predicate suffixes.
 286         (mve_vec_sizename): New array with vector sizes.
 287         (enum vpt_pred_state): New enum with vector predication states.
 288         (struct vpt_block): New struct type for vpt blocks.
 289         (vpt_block_state): Global struct to keep track of state.
 290         (mve_extract_pred_mask): New helper function.
 291         (num_instructions_vpt_block): Likewise.
 292         (mark_outside_vpt_block): Likewise.
 293         (mark_inside_vpt_block): Likewise.
 294         (invert_next_predicate_state): Likewise.
 295         (update_next_predicate_state): Likewise.
 296         (update_vpt_block_state): Likewise.
 297         (is_vpt_instruction): Likewise.
 298         (is_mve_encoding_conflict): Add entries for new instructions.
 299         (is_mve_unpredictable): Likewise.
 300         (print_mve_unpredictable): Handle new cases.
 301         (print_instruction_predicate): Likewise.
 302         (print_mve_size): New function.
 303         (print_vec_condition): New function.
 304         (print_insn_mve): Handle vpt blocks and new print operands.
 305
 306 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 307
 308         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 309         8, 14 and 15 for Armv8.1-M Mainline.
 310
 311 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 312             Michael Collison <michael.collison@arm.com>
 313
 314         * arm-dis.c (enum mve_instructions): New enum.
 315         (enum mve_unpredictable): Likewise.
 316         (enum mve_undefined): Likewise.
 317         (struct mopcode32): New struct.
 318         (is_mve_okay_in_it): New function.
 319         (is_mve_architecture): Likewise.
 320         (arm_decode_field): Likewise.
 321         (arm_decode_field_multiple): Likewise.
 322         (is_mve_encoding_conflict): Likewise.
 323         (is_mve_undefined): Likewise.
 324         (is_mve_unpredictable): Likewise.
 325         (print_mve_undefined): Likewise.
 326         (print_mve_unpredictable): Likewise.
 327         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 328         (print_insn_mve): New function.
 329         (print_insn_thumb32): Handle MVE architecture.
 330         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 331
 332 2019-05-10  Nick Clifton  <nickc@redhat.com>
 333
 334         PR 24538
 335         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 336         end of the table prematurely.
 337
 338 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 339
 340         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 341         macros for R6.
 342
 343 2019-05-11  Alan Modra  <amodra@gmail.com>
 344
 345         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 346         when -Mraw is in effect.
 347
 348 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 349
 350         * aarch64-dis-2.c: Regenerate.
 351         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 352         (OP_SVE_BBB): New variant set.
 353         (OP_SVE_DDDD): New variant set.
 354         (OP_SVE_HHH): New variant set.
 355         (OP_SVE_HHHU): New variant set.
 356         (OP_SVE_SSS): New variant set.
 357         (OP_SVE_SSSU): New variant set.
 358         (OP_SVE_SHH): New variant set.
 359         (OP_SVE_SBBU): New variant set.
 360         (OP_SVE_DSS): New variant set.
 361         (OP_SVE_DHHU): New variant set.
 362         (OP_SVE_VMV_HSD_BHS): New variant set.
 363         (OP_SVE_VVU_HSD_BHS): New variant set.
 364         (OP_SVE_VVVU_SD_BH): New variant set.
 365         (OP_SVE_VVVU_BHSD): New variant set.
 366         (OP_SVE_VVV_QHD_DBS): New variant set.
 367         (OP_SVE_VVV_HSD_BHS): New variant set.
 368         (OP_SVE_VVV_HSD_BHS2): New variant set.
 369         (OP_SVE_VVV_BHS_HSD): New variant set.
 370         (OP_SVE_VV_BHS_HSD): New variant set.
 371         (OP_SVE_VVV_SD): New variant set.
 372         (OP_SVE_VVU_BHS_HSD): New variant set.
 373         (OP_SVE_VZVV_SD): New variant set.
 374         (OP_SVE_VZVV_BH): New variant set.
 375         (OP_SVE_VZV_SD): New variant set.
 376         (aarch64_opcode_table): Add sve2 instructions.
 377
 378 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 379
 380         * aarch64-asm-2.c: Regenerated.
 381         * aarch64-dis-2.c: Regenerated.
 382         * aarch64-opc-2.c: Regenerated.
 383         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 384         for SVE_SHLIMM_UNPRED_22.
 385         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 386         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 387         operand.
 388
 389 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 390
 391         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 392         sve_size_tsz_bhs iclass encode.
 393         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 394         sve_size_tsz_bhs iclass decode.
 395
 396 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 397
 398         * aarch64-asm-2.c: Regenerated.
 399         * aarch64-dis-2.c: Regenerated.
 400         * aarch64-opc-2.c: Regenerated.
 401         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 402         for SVE_Zm4_11_INDEX.
 403         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 404         (fields): Handle SVE_i2h field.
 405         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 406         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 407
 408 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 409
 410         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 411         sve_shift_tsz_bhsd iclass encode.
 412         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 413         sve_shift_tsz_bhsd iclass decode.
 414
 415 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 416
 417         * aarch64-asm-2.c: Regenerated.
 418         * aarch64-dis-2.c: Regenerated.
 419         * aarch64-opc-2.c: Regenerated.
 420         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 421         (aarch64_encode_variant_using_iclass): Handle
 422         sve_shift_tsz_hsd iclass encode.
 423         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 424         sve_shift_tsz_hsd iclass decode.
 425         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 426         for SVE_SHRIMM_UNPRED_22.
 427         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 428         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 429         operand.
 430
 431 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 432
 433         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 434         sve_size_013 iclass encode.
 435         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 436         sve_size_013 iclass decode.
 437
 438 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 439
 440         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 441         sve_size_bh iclass encode.
 442         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 443         sve_size_bh iclass decode.
 444
 445 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 446
 447         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 448         sve_size_sd2 iclass encode.
 449         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 450         sve_size_sd2 iclass decode.
 451         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 452         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 453
 454 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 455
 456         * aarch64-asm-2.c: Regenerated.
 457         * aarch64-dis-2.c: Regenerated.
 458         * aarch64-opc-2.c: Regenerated.
 459         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 460         for SVE_ADDR_ZX.
 461         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 462         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 463
 464 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 465
 466         * aarch64-asm-2.c: Regenerated.
 467         * aarch64-dis-2.c: Regenerated.
 468         * aarch64-opc-2.c: Regenerated.
 469         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 470         for SVE_Zm3_11_INDEX.
 471         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 472         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 473         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 474         fields.
 475         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 476
 477 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 478
 479         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 480         sve_size_hsd2 iclass encode.
 481         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 482         sve_size_hsd2 iclass decode.
 483         * aarch64-opc.c (fields): Handle SVE_size field.
 484         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 485
 486 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 487
 488         * aarch64-asm-2.c: Regenerated.
 489         * aarch64-dis-2.c: Regenerated.
 490         * aarch64-opc-2.c: Regenerated.
 491         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 492         for SVE_IMM_ROT3.
 493         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 494         (fields): Handle SVE_rot3 field.
 495         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 496         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 497
 498 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 499
 500         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 501         instructions.
 502
 503 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 504
 505         * aarch64-tbl.h
 506         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 507         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 508         aarch64_feature_sve2bitperm): New feature sets.
 509         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 510         for feature set addresses.
 511         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 512         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 513
 514 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 515             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 516
 517         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 518         argument and set ASE_EVA_R6 appropriately.
 519         (set_default_mips_dis_options): Pass ISA to above.
 520         (parse_mips_dis_option): Likewise.
 521         * mips-opc.c (EVAR6): New macro.
 522         (mips_builtin_opcodes): Add llwpe, scwpe.
 523
 524 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 525
 526         * aarch64-asm-2.c: Regenerated.
 527         * aarch64-dis-2.c: Regenerated.
 528         * aarch64-opc-2.c: Regenerated.
 529         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 530         AARCH64_OPND_TME_UIMM16.
 531         (aarch64_print_operand): Likewise.
 532         * aarch64-tbl.h (QL_IMM_NIL): New.
 533         (TME): New.
 534         (_TME_INSN): New.
 535         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 536
 537 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 538
 539         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 540
 541 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 542             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 543
 544         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 545
 546 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 547
 548         * s12z-opc.h: Add extern "C" bracketing to help
 549         users who wish to use this interface in c++ code.
 550
 551 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 552
 553         * s12z-opc.c (bm_decode): Handle bit map operations with the
 554         "reserved0" mode.
 555
 556 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 557
 558         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 559         specifier.  Add entries for VLDR and VSTR of system registers.
 560         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 561         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 562         of %J and %K format specifier.
 563
 564 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 565
 566         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 567         Add new entries for VSCCLRM instruction.
 568         (print_insn_coprocessor): Handle new %C format control code.
 569
 570 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 571
 572         * arm-dis.c (enum isa): New enum.
 573         (struct sopcode32): New structure.
 574         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 575         set isa field of all current entries to ANY.
 576         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 577         Only match an entry if its isa field allows the current mode.
 578
 579 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 580
 581         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 582         CLRM.
 583         (print_insn_thumb32): Add logic to print %n CLRM register list.
 584
 585 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 586
 587         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 588         and %Q patterns.
 589
 590 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 591
 592         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 593         (print_insn_thumb32): Edit the switch case for %Z.
 594
 595 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 596
 597         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 598
 599 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 600
 601         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 602
 603 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 604
 605         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 606
 607 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 608
 609         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 610         Arm register with r13 and r15 unpredictable.
 611         (thumb32_opcodes): New instructions for bfx and bflx.
 612
 613 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 614
 615         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 616
 617 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 618
 619         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 620
 621 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 622
 623         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 624
 625 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 626
 627         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 628
 629 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 630
 631         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 632         "optr". ("operator" is a reserved word in c++).
 633
 634 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 635
 636         * aarch64-opc.c (aarch64_print_operand): Add case for
 637         AARCH64_OPND_Rt_SP.
 638         (verify_constraints): Likewise.
 639         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 640         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 641         to accept Rt|SP as first operand.
 642         (AARCH64_OPERANDS): Add new Rt_SP.
 643         * aarch64-asm-2.c: Regenerated.
 644         * aarch64-dis-2.c: Regenerated.
 645         * aarch64-opc-2.c: Regenerated.
 646
 647 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 648
 649         * aarch64-asm-2.c: Regenerated.
 650         * aarch64-dis-2.c: Likewise.
 651         * aarch64-opc-2.c: Likewise.
 652         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 653
 654 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 655
 656         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 657
 658 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 659
 660         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 661         * i386-init.h: Regenerated.
 662
 663 2019-04-07  Alan Modra  <amodra@gmail.com>
 664
 665         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 666         op_separator to control printing of spaces, comma and parens
 667         rather than need_comma, need_paren and spaces vars.
 668
 669 2019-04-07  Alan Modra  <amodra@gmail.com>
 670
 671         PR 24421
 672         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 673         (print_insn_neon, print_insn_arm): Likewise.
 674
 675 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 676
 677         * i386-dis-evex.h (evex_table): Updated to support BF16
 678         instructions.
 679         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 680         and EVEX_W_0F3872_P_3.
 681         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 682         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 683         * i386-opc.h (enum): Add CpuAVX512_BF16.
 684         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 685         * i386-opc.tbl: Add AVX512 BF16 instructions.
 686         * i386-init.h: Regenerated.
 687         * i386-tbl.h: Likewise.
 688
 689 2019-04-05  Alan Modra  <amodra@gmail.com>
 690
 691         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 692         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 693         to favour printing of "-" branch hint when using the "y" bit.
 694         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 695
 696 2019-04-05  Alan Modra  <amodra@gmail.com>
 697
 698         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 699         opcode until first operand is output.
 700
 701 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 702
 703         PR gas/24349
 704         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 705         (valid_bo_post_v2): Add support for 'at' branch hints.
 706         (insert_bo): Only error on branch on ctr.
 707         (get_bo_hint_mask): New function.
 708         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 709         for inserting 'at' branch hints.
 710         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 711         for extracting 'at' branch hints.
 712         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 713         (BOE): Delete operand.
 714         (BOM, BOP): New operands.
 715         (RM): Update value.
 716         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 717         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 718         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 719         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 720         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 721         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 722         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 723         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 724         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 725         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 726         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 727         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 728         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 729         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 730         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 731         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 732         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 733         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 734         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 735         bttarl+>: New extended mnemonics.
 736
 737 2019-03-28  Alan Modra  <amodra@gmail.com>
 738
 739         PR 24390
 740         * ppc-opc.c (BTF): Define.
 741         (powerpc_opcodes): Use for mtfsb*.
 742         * ppc-dis.c (print_insn_powerpc): Print fields with both
 743         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 744
 745 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 746
 747         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 748         (mapping_symbol_for_insn): Implement new algorithm.
 749         (print_insn): Remove duplicate code.
 750
 751 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 752
 753         * aarch64-dis.c (print_insn_aarch64):
 754         Implement override.
 755
 756 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 757
 758         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 759         order.
 760
 761 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 762
 763         * aarch64-dis.c (last_stop_offset): New.
 764         (print_insn_aarch64): Use stop_offset.
 765
 766 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 767
 768         PR gas/24359
 769         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 770         CPU_ANY_AVX2_FLAGS.
 771         * i386-init.h: Regenerated.
 772
 773 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 774
 775         PR gas/24348
 776         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 777         vmovdqu16, vmovdqu32 and vmovdqu64.
 778         * i386-tbl.h: Regenerated.
 779
 780 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 781
 782         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 783         from vstrszb, vstrszh, and vstrszf.
 784
 785 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 786
 787         * s390-opc.txt: Add instruction descriptions.
 788
 789 2019-02-08  Jim Wilson  <jimw@sifive.com>
 790
 791         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 792         <bne>: Likewise.
 793
 794 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 795
 796         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 797
 798 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 799
 800         PR binutils/23212
 801         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 802         * aarch64-opc.c (verify_elem_sd): New.
 803         (fields): Add FLD_sz entr.
 804         * aarch64-tbl.h (_SIMD_INSN): New.
 805         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 806         fmulx scalar and vector by element isns.
 807
 808 2019-02-07  Nick Clifton  <nickc@redhat.com>
 809
 810         * po/sv.po: Updated Swedish translation.
 811
 812 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 813
 814         * s390-mkopc.c (main): Accept arch13 as cpu string.
 815         * s390-opc.c: Add new instruction formats and instruction opcode
 816         masks.
 817         * s390-opc.txt: Add new arch13 instructions.
 818
 819 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 820
 821         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 822         (aarch64_opcode): Change encoding for stg, stzg
 823         st2g and st2zg.
 824         * aarch64-asm-2.c: Regenerated.
 825         * aarch64-dis-2.c: Regenerated.
 826         * aarch64-opc-2.c: Regenerated.
 827
 828 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 829
 830         * aarch64-asm-2.c: Regenerated.
 831         * aarch64-dis-2.c: Likewise.
 832         * aarch64-opc-2.c: Likewise.
 833         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 834
 835 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 836             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 837
 838         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 839         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 840         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 841         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 842         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 843         case for ldstgv_indexed.
 844         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 845         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 846         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 847         * aarch64-asm-2.c: Regenerated.
 848         * aarch64-dis-2.c: Regenerated.
 849         * aarch64-opc-2.c: Regenerated.
 850
 851 2019-01-23  Nick Clifton  <nickc@redhat.com>
 852
 853         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 854
 855 2019-01-21  Nick Clifton  <nickc@redhat.com>
 856
 857         * po/de.po: Updated German translation.
 858         * po/uk.po: Updated Ukranian translation.
 859
 860 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 861         * mips-dis.c (mips_arch_choices): Fix typo in
 862         gs464, gs464e and gs264e descriptors.
 863
 864 2019-01-19  Nick Clifton  <nickc@redhat.com>
 865
 866         * configure: Regenerate.
 867         * po/opcodes.pot: Regenerate.
 868
 869 2018-06-24  Nick Clifton  <nickc@redhat.com>
 870
 871         2.32 branch created.
 872
 873 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 874
 875         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 876         if it is null.
 877         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 878         zero.
 879
 880 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 881
 882         * configure: Regenerate.
 883
 884 2019-01-07  Alan Modra  <amodra@gmail.com>
 885
 886         * configure: Regenerate.
 887         * po/POTFILES.in: Regenerate.
 888
 889 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 890
 891         * s12z-opc.c: New file.
 892         * s12z-opc.h: New file.
 893         * s12z-dis.c: Removed all code not directly related to display
 894         of instructions.  Used the interface provided by the new files
 895         instead.
 896         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 897         * Makefile.in: Regenerate.
 898         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 899         * configure: Regenerate.
 900
 901 2019-01-01  Alan Modra  <amodra@gmail.com>
 902
 903         Update year range in copyright notice of all files.
 904
 905 For older changes see ChangeLog-2018
 906 \f
 907 Copyright (C) 2019 Free Software Foundation, Inc.
 908
 909 Copying and distribution of this file, with or without modification,
 910 are permitted in any medium without royalty provided the copyright
 911 notice and this notice are preserved.
 912
 913 Local Variables:
 914 mode: change-log
 915 left-margin: 8
 916 fill-column: 74
 917 version-control: never
 918 End: