opcodes/ChangeLog

   1 2017-06-16  Alan Modra  <amodra@gmail.com>
   2
   3         * rx-decode.c: Regenerate.
   4
   5 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         PR binutils/21594
   8         * i386-dis.c (OP_E_register): Check valid bnd register.
   9         (OP_G): Likewise.
  10
  11 2017-06-15  Nick Clifton  <nickc@redhat.com>
  12
  13         PR binutils/21595
  14         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
  15         range value.
  16
  17 2017-06-15  Nick Clifton  <nickc@redhat.com>
  18
  19         PR binutils/21588
  20         * rl78-decode.opc (OP_BUF_LEN): Define.
  21         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
  22         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
  23         array.
  24         * rl78-decode.c: Regenerate.
  25
  26 2017-06-15  Nick Clifton  <nickc@redhat.com>
  27
  28         PR binutils/21586
  29         * bfin-dis.c (gregs): Clip index to prevent overflow.
  30         (regs): Likewise.
  31         (regs_lo): Likewise.
  32         (regs_hi): Likewise.
  33
  34 2017-06-14  Nick Clifton  <nickc@redhat.com>
  35
  36         PR binutils/21576
  37         * score7-dis.c (score_opcodes): Add sentinel.
  38
  39 2017-06-14  Yao Qi  <yao.qi@linaro.org>
  40
  41         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
  42         * arm-dis.c: Likewise.
  43         * ia64-dis.c: Likewise.
  44         * mips-dis.c: Likewise.
  45         * spu-dis.c: Likewise.
  46         * disassemble.h (print_insn_aarch64): New declaration, moved from
  47         include/dis-asm.h.
  48         (print_insn_big_arm, print_insn_big_mips): Likewise.
  49         (print_insn_i386, print_insn_ia64): Likewise.
  50         (print_insn_little_arm, print_insn_little_mips): Likewise.
  51
  52 2017-06-14  Nick Clifton  <nickc@redhat.com>
  53
  54         PR binutils/21587
  55         * rx-decode.opc: Include libiberty.h
  56         (GET_SCALE): New macro - validates access to SCALE array.
  57         (GET_PSCALE): New macro - validates access to PSCALE array.
  58         (DIs, SIs, S2Is, rx_disp): Use new macros.
  59         * rx-decode.c: Regenerate.
  60
  61 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  62
  63         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
  64
  65 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
  66
  67         * arc-dis.c (enforced_isa_mask): Declare.
  68         (cpu_types): Likewise.
  69         (parse_cpu_option): New function.
  70         (parse_disassembler_options): Use it.
  71         (print_insn_arc): Use enforced_isa_mask.
  72         (print_arc_disassembler_options): Document new options.
  73
  74 2017-05-24  Yao Qi  <yao.qi@linaro.org>
  75
  76         * alpha-dis.c: Include disassemble.h, don't include
  77         dis-asm.h.
  78         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
  79         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
  80         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
  81         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
  82         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
  83         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
  84         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
  85         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
  86         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
  87         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
  88         * moxie-dis.c, msp430-dis.c, mt-dis.c:
  89         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
  90         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
  91         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
  92         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
  93         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
  94         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
  95         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
  96         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
  97         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
  98         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
  99         * z80-dis.c, z8k-dis.c: Likewise.
 100         * disassemble.h: New file.
 101
 102 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 103
 104         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 105         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 106
 107 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 108
 109         * disassemble.c (disassembler): Add arguments a, big and mach.
 110         Use them.
 111
 112 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 113
 114         * i386-dis.c (NOTRACK_Fixup): New.
 115         (NOTRACK): Likewise.
 116         (NOTRACK_PREFIX): Likewise.
 117         (last_active_prefix): Likewise.
 118         (reg_table): Use NOTRACK on indirect call and jmp.
 119         (ckprefix): Set last_active_prefix.
 120         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 121         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 122         * i386-opc.h (NoTrackPrefixOk): New.
 123         (i386_opcode_modifier): Add notrackprefixok.
 124         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 125         Add notrack.
 126         * i386-tbl.h: Regenerated.
 127
 128 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 129
 130         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 131         (X_IMM2): Define.
 132         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 133         bfd_mach_sparc_v9m8.
 134         (print_insn_sparc): Handle new operand types.
 135         * sparc-opc.c (MASK_M8): Define.
 136         (v6): Add MASK_M8.
 137         (v6notlet): Likewise.
 138         (v7): Likewise.
 139         (v8): Likewise.
 140         (v9): Likewise.
 141         (v9a): Likewise.
 142         (v9b): Likewise.
 143         (v9c): Likewise.
 144         (v9d): Likewise.
 145         (v9e): Likewise.
 146         (v9v): Likewise.
 147         (v9m): Likewise.
 148         (v9andleon): Likewise.
 149         (m8): Define.
 150         (HWS_VM8): Define.
 151         (HWS2_VM8): Likewise.
 152         (sparc_opcode_archs): Add entry for "m8".
 153         (sparc_opcodes): Add OSA2017 and M8 instructions
 154         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 155         fpx{ll,ra,rl}64x,
 156         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 157         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 158         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 159         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 160         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 161         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 162         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 163         ASI_CORE_SELECT_COMMIT_NHT.
 164
 165 2017-05-18  Alan Modra  <amodra@gmail.com>
 166
 167         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 168         * aarch64-dis.c: Likewise.
 169         * aarch64-gen.c: Likewise.
 170         * aarch64-opc.c: Likewise.
 171
 172 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 173             Matthew Fortune  <matthew.fortune@imgtec.com>
 174
 175         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 176         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 177         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 178         (print_insn_arg) <OP_REG28>: Add handler.
 179         (validate_insn_args) <OP_REG28>: Handle.
 180         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 181         32-bit encoding and 9-bit immediates.
 182         (print_insn_mips16): Handle MIPS16 instructions that require
 183         32-bit encoding and MFC0/MTC0 operand decoding.
 184         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 185         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 186         (RD_C0, WR_C0, E2, E2MT): New macros.
 187         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 188         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 189         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 190         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 191         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 192         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 193         instructions, "swl", "swr", "sync" and its "sync_acquire",
 194         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 195         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 196         regular/extended entries for original MIPS16 ISA revision
 197         instructions whose extended forms are subdecoded in the MIPS16e2
 198         ISA revision: "li", "sll" and "srl".
 199
 200 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 201
 202         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 203         reference in CP0 move operand decoding.
 204
 205 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 206
 207         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 208         type to hexadecimal.
 209         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 210
 211 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 212
 213         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 214         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 215         "sync_rmb" and "sync_wmb" as aliases.
 216         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 217         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 218
 219 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 220
 221         * arc-dis.c (parse_option): Update quarkse_em option..
 222         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 223         QUARKSE1.
 224         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 225
 226 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 227
 228         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 229
 230 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 231
 232         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 233         register.
 234
 235 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 236
 237         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 238         and branches and not synthetic data instructions.
 239
 240 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 241
 242         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 243
 244 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 245
 246         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 247         * arc-opc.c (insert_r13el): New function.
 248         (R13_EL): Define.
 249         * arc-tbl.h: Add new enter/leave variants.
 250
 251 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 252
 253         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 254
 255 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 256
 257         * mips-dis.c (print_mips_disassembler_options): Add
 258         `no-aliases'.
 259
 260 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 261
 262         * mips16-opc.c (AL): New macro.
 263         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 264         of "ld" and "lw" as aliases.
 265
 266 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 267
 268         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 269         arguments.
 270
 271 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 272             Alan Modra  <amodra@gmail.com>
 273
 274         * ppc-opc.c (ELEV): Define.
 275         (vle_opcodes): Add se_rfgi and e_sc.
 276         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 277         for E200Z4.
 278
 279 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 280
 281         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 282
 283 2017-04-21  Nick Clifton  <nickc@redhat.com>
 284
 285         PR binutils/21380
 286         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 287         LD3R and LD4R.
 288
 289 2017-04-13  Alan Modra  <amodra@gmail.com>
 290
 291         * epiphany-desc.c: Regenerate.
 292         * fr30-desc.c: Regenerate.
 293         * frv-desc.c: Regenerate.
 294         * ip2k-desc.c: Regenerate.
 295         * iq2000-desc.c: Regenerate.
 296         * lm32-desc.c: Regenerate.
 297         * m32c-desc.c: Regenerate.
 298         * m32r-desc.c: Regenerate.
 299         * mep-desc.c: Regenerate.
 300         * mt-desc.c: Regenerate.
 301         * or1k-desc.c: Regenerate.
 302         * xc16x-desc.c: Regenerate.
 303         * xstormy16-desc.c: Regenerate.
 304
 305 2017-04-11  Alan Modra  <amodra@gmail.com>
 306
 307         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 308         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 309         PPC_OPCODE_TMR for e6500.
 310         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 311         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 312         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 313         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 314         (PPCHTM): Define as PPC_OPCODE_POWER8.
 315         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 316
 317 2017-04-10  Alan Modra  <amodra@gmail.com>
 318
 319         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 320         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 321         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 322         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 323
 324 2017-04-09  Pip Cet  <pipcet@gmail.com>
 325
 326         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 327         appropriate floating-point precision directly.
 328
 329 2017-04-07  Alan Modra  <amodra@gmail.com>
 330
 331         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 332         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 333         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 334         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 335         vector instructions with E6500 not PPCVEC2.
 336
 337 2017-04-06  Pip Cet  <pipcet@gmail.com>
 338
 339         * Makefile.am: Add wasm32-dis.c.
 340         * configure.ac: Add wasm32-dis.c to wasm32 target.
 341         * disassemble.c: Add wasm32 disassembler code.
 342         * wasm32-dis.c: New file.
 343         * Makefile.in: Regenerate.
 344         * configure: Regenerate.
 345         * po/POTFILES.in: Regenerate.
 346         * po/opcodes.pot: Regenerate.
 347
 348 2017-04-05  Pedro Alves  <palves@redhat.com>
 349
 350         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 351         * arm-dis.c (parse_arm_disassembler_options): Constify.
 352         * ppc-dis.c (powerpc_init_dialect): Constify local.
 353         * vax-dis.c (parse_disassembler_options): Constify.
 354
 355 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 356
 357         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 358         RISCV_GP_SYMBOL.
 359
 360 2017-03-30  Pip Cet  <pipcet@gmail.com>
 361
 362         * configure.ac: Add (empty) bfd_wasm32_arch target.
 363         * configure: Regenerate
 364         * po/opcodes.pot: Regenerate.
 365
 366 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 367
 368         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 369         OSA2015.
 370         * opcodes/sparc-opc.c (asi_table): New ASIs.
 371
 372 2017-03-29  Alan Modra  <amodra@gmail.com>
 373
 374         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 375         "raw" option.
 376         (lookup_powerpc): Don't special case -1 dialect.  Handle
 377         PPC_OPCODE_RAW.
 378         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 379         lookup_powerpc call, pass it on second.
 380
 381 2017-03-27  Alan Modra  <amodra@gmail.com>
 382
 383         PR 21303
 384         * ppc-dis.c (struct ppc_mopt): Comment.
 385         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 386
 387 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 388
 389         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 390         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 391         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 392         (insert_nps_misc_imm_offset): New function.
 393         (extract_nps_misc imm_offset): New function.
 394         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 395         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 396
 397 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 398
 399         * s390-mkopc.c (main): Remove vx2 check.
 400         * s390-opc.txt: Remove vx2 instruction flags.
 401
 402 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 403
 404         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 405         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 406         (insert_nps_imm_offset): New function.
 407         (extract_nps_imm_offset): New function.
 408         (insert_nps_imm_entry): New function.
 409         (extract_nps_imm_entry): New function.
 410
 411 2017-03-17  Alan Modra  <amodra@gmail.com>
 412
 413         PR 21248
 414         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 415         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 416         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 417
 418 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 419
 420         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 421         <c.andi>: Likewise.
 422         <c.addiw> Likewise.
 423
 424 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 425
 426         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 427
 428 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 429
 430         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 431         <srl> Likewise.
 432         <srai> Likewise.
 433         <sra> Likewise.
 434
 435 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 436
 437         * i386-gen.c (opcode_modifiers): Replace S with Load.
 438         * i386-opc.h (S): Removed.
 439         (Load): New.
 440         (i386_opcode_modifier): Replace s with load.
 441         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 442         and {evex}.  Replace S with Load.
 443         * i386-tbl.h: Regenerated.
 444
 445 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         * i386-opc.tbl: Use CpuCET on rdsspq.
 448         * i386-tbl.h: Regenerated.
 449
 450 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 451
 452         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 453         <vsx>: Do not use PPC_OPCODE_VSX3;
 454
 455 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 456
 457         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 458
 459 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 460
 461         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 462         (MOD_0F1E_PREFIX_1): Likewise.
 463         (MOD_0F38F5_PREFIX_2): Likewise.
 464         (MOD_0F38F6_PREFIX_0): Likewise.
 465         (RM_0F1E_MOD_3_REG_7): Likewise.
 466         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 467         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 468         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 469         (PREFIX_0F1E): Likewise.
 470         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 471         (PREFIX_0F38F5): Likewise.
 472         (dis386_twobyte): Use PREFIX_0F1E.
 473         (reg_table): Add REG_0F1E_MOD_3.
 474         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 475         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 476         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 477         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 478         (three_byte_table): Use PREFIX_0F38F5.
 479         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 480         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 481         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 482         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 483         PREFIX_MOD_3_0F01_REG_5_RM_2.
 484         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 485         (cpu_flags): Add CpuCET.
 486         * i386-opc.h (CpuCET): New enum.
 487         (CpuUnused): Commented out.
 488         (i386_cpu_flags): Add cpucet.
 489         * i386-opc.tbl: Add Intel CET instructions.
 490         * i386-init.h: Regenerated.
 491         * i386-tbl.h: Likewise.
 492
 493 2017-03-06  Alan Modra  <amodra@gmail.com>
 494
 495         PR 21124
 496         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 497         (extract_raq, extract_ras, extract_rbx): New functions.
 498         (powerpc_operands): Use opposite corresponding insert function.
 499         (Q_MASK): Define.
 500         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 501         register restriction.
 502
 503 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 504
 505         * disassemble.c Include "safe-ctype.h".
 506         (disassemble_init_for_target): Handle s390 init.
 507         (remove_whitespace_and_extra_commas): New function.
 508         (disassembler_options_cmp): Likewise.
 509         * arm-dis.c: Include "libiberty.h".
 510         (NUM_ELEM): Delete.
 511         (regnames): Use long disassembler style names.
 512         Add force-thumb and no-force-thumb options.
 513         (NUM_ARM_REGNAMES): Rename from this...
 514         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 515         (get_arm_regname_num_options): Delete.
 516         (set_arm_regname_option): Likewise.
 517         (get_arm_regnames): Likewise.
 518         (parse_disassembler_options): Likewise.
 519         (parse_arm_disassembler_option): Rename from this...
 520         (parse_arm_disassembler_options): ...to this.  Make static.
 521         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 522         (print_insn): Use parse_arm_disassembler_options.
 523         (disassembler_options_arm): New function.
 524         (print_arm_disassembler_options): Handle updated regnames.
 525         * ppc-dis.c: Include "libiberty.h".
 526         (ppc_opts): Add "32" and "64" entries.
 527         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 528         (powerpc_init_dialect): Add break to switch statement.
 529         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 530         (disassembler_options_powerpc): New function.
 531         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 532         Remove printing of "32" and "64".
 533         * s390-dis.c: Include "libiberty.h".
 534         (init_flag): Remove unneeded variable.
 535         (struct s390_options_t): New structure type.
 536         (options): New structure.
 537         (init_disasm): Rename from this...
 538         (disassemble_init_s390): ...to this.  Add initializations for
 539         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 540         (print_insn_s390): Delete call to init_disasm.
 541         (disassembler_options_s390): New function.
 542         (print_s390_disassembler_options): Print using information from
 543         struct 'options'.
 544         * po/opcodes.pot: Regenerate.
 545
 546 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-dis.c (PCMPESTR_Fixup): New.
 549         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 550         (prefix_table): Use PCMPESTR_Fixup.
 551         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 552         PCMPESTR_Fixup.
 553         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 554         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 555         Split 64-bit and non-64-bit variants.
 556         * opcodes/i386-tbl.h: Re-generate.
 557
 558 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 559
 560         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 561         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 562         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 563         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 564         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 565         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 566         (OP_SVE_V_HSD): New macros.
 567         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 568         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 569         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 570         (aarch64_opcode_table): Add new SVE instructions.
 571         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 572         for rotation operands.  Add new SVE operands.
 573         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 574         (ins_sve_quad_index): Likewise.
 575         (ins_imm_rotate): Split into...
 576         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 577         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 578         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 579         functions.
 580         (aarch64_ins_sve_addr_ri_s4): New function.
 581         (aarch64_ins_sve_quad_index): Likewise.
 582         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 583         * aarch64-asm-2.c: Regenerate.
 584         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 585         (ext_sve_quad_index): Likewise.
 586         (ext_imm_rotate): Split into...
 587         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 588         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 589         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 590         functions.
 591         (aarch64_ext_sve_addr_ri_s4): New function.
 592         (aarch64_ext_sve_quad_index): Likewise.
 593         (aarch64_ext_sve_index): Allow quad indices.
 594         (do_misc_decoding): Likewise.
 595         * aarch64-dis-2.c: Regenerate.
 596         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 597         aarch64_field_kinds.
 598         (OPD_F_OD_MASK): Widen by one bit.
 599         (OPD_F_NO_ZR): Bump accordingly.
 600         (get_operand_field_width): New function.
 601         * aarch64-opc.c (fields): Add new SVE fields.
 602         (operand_general_constraint_met_p): Handle new SVE operands.
 603         (aarch64_print_operand): Likewise.
 604         * aarch64-opc-2.c: Regenerate.
 605
 606 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 607
 608         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 609         (aarch64_feature_compnum): ...this.
 610         (SIMD_V8_3): Replace with...
 611         (COMPNUM): ...this.
 612         (CNUM_INSN): New macro.
 613         (aarch64_opcode_table): Use it for the complex number instructions.
 614
 615 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 616
 617         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 618
 619 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 620
 621         Add support for associating SPARC ASIs with an architecture level.
 622         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 623         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 624         decoding of SPARC ASIs.
 625
 626 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 627
 628         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 629         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 630
 631 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 632
 633         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 634         1 (instead of to itself). Correct typo.
 635
 636 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 637
 638         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 639         pseudoinstructions.
 640
 641 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 642
 643         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 644         (aarch64_sys_reg_supported_p): Handle them.
 645
 646 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 647
 648         * arc-opc.c (UIMM6_20R): Define.
 649         (SIMM12_20): Use above.
 650         (SIMM12_20R): Define.
 651         (SIMM3_5_S): Use above.
 652         (UIMM7_A32_11R_S): Define.
 653         (UIMM7_9_S): Use above.
 654         (UIMM3_13R_S): Define.
 655         (SIMM11_A32_7_S): Use above.
 656         (SIMM9_8R): Define.
 657         (UIMM10_A32_8_S): Use above.
 658         (UIMM8_8R_S): Define.
 659         (W6): Use above.
 660         (arc_relax_opcodes): Use all above defines.
 661
 662 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 663
 664         * arc-regs.h: Distinguish some of the registers different on
 665         ARC700 and HS38 cpus.
 666
 667 2017-02-14  Alan Modra  <amodra@gmail.com>
 668
 669         PR 21118
 670         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 671         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 672
 673 2017-02-11  Stafford Horne  <shorne@gmail.com>
 674             Alan Modra  <amodra@gmail.com>
 675
 676         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 677         Use insn_bytes_value and insn_int_value directly instead.  Don't
 678         free allocated memory until function exit.
 679
 680 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 681
 682         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 683
 684 2017-02-03  Nick Clifton  <nickc@redhat.com>
 685
 686         PR 21096
 687         * aarch64-opc.c (print_register_list): Ensure that the register
 688         list index will fir into the tb buffer.
 689         (print_register_offset_address): Likewise.
 690         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 691
 692 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 693
 694         PR 21056
 695         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 696         instructions when the previous fetch packet ends with a 32-bit
 697         instruction.
 698
 699 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 700
 701         * pru-opc.c: Remove vague reference to a future GDB port.
 702
 703 2017-01-20  Nick Clifton  <nickc@redhat.com>
 704
 705         * po/ga.po: Updated Irish translation.
 706
 707 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 708
 709         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 710
 711 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 712
 713         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 714         if FETCH_DATA returns 0.
 715         (m68k_scan_mask): Likewise.
 716         (print_insn_m68k): Update code to handle -1 return value.
 717
 718 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 719
 720         * m68k-dis.c (enum print_insn_arg_error): New.
 721         (NEXTBYTE): Replace -3 with
 722         PRINT_INSN_ARG_MEMORY_ERROR.
 723         (NEXTULONG): Likewise.
 724         (NEXTSINGLE): Likewise.
 725         (NEXTDOUBLE): Likewise.
 726         (NEXTDOUBLE): Likewise.
 727         (NEXTPACKED): Likewise.
 728         (FETCH_ARG): Likewise.
 729         (FETCH_DATA): Update comments.
 730         (print_insn_arg): Update comments. Replace magic numbers with
 731         enum.
 732         (match_insn_m68k): Likewise.
 733
 734 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 735
 736         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 737         * i386-dis-evex.h (evex_table): Updated.
 738         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 739         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 740         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 741         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 742         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 743         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 744         * i386-init.h: Regenerate.
 745         * i386-tbl.h: Ditto.
 746
 747 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 748
 749         * msp430-dis.c (msp430_singleoperand): Return -1 if
 750         msp430dis_opcode_signed returns false.
 751         (msp430_doubleoperand): Likewise.
 752         (msp430_branchinstr): Return -1 if
 753         msp430dis_opcode_unsigned returns false.
 754         (msp430x_calla_instr): Likewise.
 755         (print_insn_msp430): Likewise.
 756
 757 2017-01-05  Nick Clifton  <nickc@redhat.com>
 758
 759         PR 20946
 760         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 761         could not be matched.
 762         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 763         NULL.
 764
 765 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 766
 767         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 768         (aarch64_opcode_table): Use RCPC_INSN.
 769
 770 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 771
 772         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 773         extension.
 774         * riscv-opcodes/all-opcodes: Likewise.
 775
 776 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 777
 778         * riscv-dis.c (print_insn_args): Add fall through comment.
 779
 780 2017-01-03  Nick Clifton  <nickc@redhat.com>
 781
 782         * po/sr.po: New Serbian translation.
 783         * configure.ac (ALL_LINGUAS): Add sr.
 784         * configure: Regenerate.
 785
 786 2017-01-02  Alan Modra  <amodra@gmail.com>
 787
 788         * epiphany-desc.h: Regenerate.
 789         * epiphany-opc.h: Regenerate.
 790         * fr30-desc.h: Regenerate.
 791         * fr30-opc.h: Regenerate.
 792         * frv-desc.h: Regenerate.
 793         * frv-opc.h: Regenerate.
 794         * ip2k-desc.h: Regenerate.
 795         * ip2k-opc.h: Regenerate.
 796         * iq2000-desc.h: Regenerate.
 797         * iq2000-opc.h: Regenerate.
 798         * lm32-desc.h: Regenerate.
 799         * lm32-opc.h: Regenerate.
 800         * m32c-desc.h: Regenerate.
 801         * m32c-opc.h: Regenerate.
 802         * m32r-desc.h: Regenerate.
 803         * m32r-opc.h: Regenerate.
 804         * mep-desc.h: Regenerate.
 805         * mep-opc.h: Regenerate.
 806         * mt-desc.h: Regenerate.
 807         * mt-opc.h: Regenerate.
 808         * or1k-desc.h: Regenerate.
 809         * or1k-opc.h: Regenerate.
 810         * xc16x-desc.h: Regenerate.
 811         * xc16x-opc.h: Regenerate.
 812         * xstormy16-desc.h: Regenerate.
 813         * xstormy16-opc.h: Regenerate.
 814
 815 2017-01-02  Alan Modra  <amodra@gmail.com>
 816
 817         Update year range in copyright notice of all files.
 818
 819 For older changes see ChangeLog-2016
 820 \f
 821 Copyright (C) 2017 Free Software Foundation, Inc.
 822
 823 Copying and distribution of this file, with or without modification,
 824 are permitted in any medium without royalty provided the copyright
 825 notice and this notice are preserved.
 826
 827 Local Variables:
 828 mode: change-log
 829 left-margin: 8
 830 fill-column: 74
 831 version-control: never
 832 End: