opcodes/ChangeLog

   1 2019-06-25  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
   4         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
   5         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
   6         OPERAND_TYPE_ACC64 entries.
   7         * i386-init.h: Re-generate.
   8
   9 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
  12         Delete.
  13         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
  14         of dqa_mode.
  15         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
  16         entries here.
  17         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
  18         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
  19
  20 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
  23         variables.
  24
  25 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
  28         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
  29         movnti.
  30         * i386-opc.tbl (movnti): Add IgnoreSize.
  31         * i386-tbl.h: Re-generate.
  32
  33 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.tbl (and): Mark Imm8S form for optimization.
  36         * i386-tbl.h: Re-generate.
  37
  38 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  39
  40         * i386-dis-evex.h: Break into ...
  41         * i386-dis-evex-len.h: New file.
  42         * i386-dis-evex-mod.h: Likewise.
  43         * i386-dis-evex-prefix.h: Likewise.
  44         * i386-dis-evex-reg.h: Likewise.
  45         * i386-dis-evex-w.h: Likewise.
  46         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
  47         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
  48         i386-dis-evex-mod.h.
  49
  50 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
  51
  52         PR binutils/24700
  53         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
  54         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
  55         EVEX_W_0F385B_P_2.
  56         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
  57         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
  58         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
  59         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
  60         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
  61         EVEX_LEN_0F385B_P_2_W_1.
  62         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
  63         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
  64         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
  65         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
  66         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
  67         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
  68         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
  69         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
  70         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
  71         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
  72
  73 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
  74
  75         PR binutils/24691
  76         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
  77         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
  78         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
  79         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
  80         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
  81         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
  82         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
  83         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
  84         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
  85         EVEX_LEN_0F3A43_P_2_W_1.
  86         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
  87         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
  88         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
  89         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
  90         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
  91         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
  92         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
  93         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
  94         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
  95         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
  96         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
  97         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
  98
  99 2019-06-14  Nick Clifton  <nickc@redhat.com>
 100
 101         * po/fr.po; Updated French translation.
 102
 103 2019-06-13  Stafford Horne  <shorne@gmail.com>
 104
 105         * or1k-asm.c: Regenerated.
 106         * or1k-desc.c: Regenerated.
 107         * or1k-desc.h: Regenerated.
 108         * or1k-dis.c: Regenerated.
 109         * or1k-ibld.c: Regenerated.
 110         * or1k-opc.c: Regenerated.
 111         * or1k-opc.h: Regenerated.
 112         * or1k-opinst.c: Regenerated.
 113
 114 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 115
 116         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 117
 118 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         PR binutils/24633
 121         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 122         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 123         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 124         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 125         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 126         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 127         EVEX_LEN_0F3A1B_P_2_W_1.
 128         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 129         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 130         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 131         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 132         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 133         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 134         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 135         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 136
 137 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         PR binutils/24626
 140         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 141         EVEX.vvvv when disassembling VEX and EVEX instructions.
 142         (OP_VEX): Set vex.register_specifier to 0 after readding
 143         vex.register_specifier.
 144         (OP_Vex_2src_1): Likewise.
 145         (OP_Vex_2src_2): Likewise.
 146         (OP_LWP_E): Likewise.
 147         (OP_EX_Vex): Don't check vex.register_specifier.
 148         (OP_XMM_Vex): Likewise.
 149
 150 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 151             Lili Cui  <lili.cui@intel.com>
 152
 153         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 154         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 155         instructions.
 156         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 157         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 158         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 159         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 160         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 161         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 162         * i386-init.h: Regenerated.
 163         * i386-tbl.h: Likewise.
 164
 165 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 166             Lili Cui  <lili.cui@intel.com>
 167
 168         * doc/c-i386.texi: Document enqcmd.
 169         * testsuite/gas/i386/enqcmd-intel.d: New file.
 170         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 171         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 172         * testsuite/gas/i386/enqcmd.d: Likewise.
 173         * testsuite/gas/i386/enqcmd.s: Likewise.
 174         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 175         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 176         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 177         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 178         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 179         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 180         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 181         and x86-64-enqcmd.
 182
 183 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 184
 185         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 186
 187 2019-06-03  Alan Modra  <amodra@gmail.com>
 188
 189         * ppc-dis.c (prefix_opcd_indices): Correct size.
 190
 191 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         PR gas/24625
 194         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 195         Disp8ShiftVL.
 196         * i386-tbl.h: Regenerated.
 197
 198 2019-05-24  Alan Modra  <amodra@gmail.com>
 199
 200         * po/POTFILES.in: Regenerate.
 201
 202 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 203             Alan Modra  <amodra@gmail.com>
 204
 205         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 206         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 207         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 208         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 209         XTOP>): Define and add entries.
 210         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 211         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 212         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 213         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 214
 215 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 216             Alan Modra  <amodra@gmail.com>
 217
 218         * ppc-dis.c (ppc_opts): Add "future" entry.
 219         (PREFIX_OPCD_SEGS): Define.
 220         (prefix_opcd_indices): New array.
 221         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 222         (lookup_prefix): New function.
 223         (print_insn_powerpc): Handle 64-bit prefix instructions.
 224         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 225         (PMRR, POWERXX): Define.
 226         (prefix_opcodes): New instruction table.
 227         (prefix_num_opcodes): New constant.
 228
 229 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 230
 231         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 232         * configure: Regenerated.
 233         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 234         and cpu/bpf.opc.
 235         (HFILES): Add bpf-desc.h and bpf-opc.h.
 236         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 237         bpf-ibld.c and bpf-opc.c.
 238         (BPF_DEPS): Define.
 239         * Makefile.in: Regenerated.
 240         * disassemble.c (ARCH_bpf): Define.
 241         (disassembler): Add case for bfd_arch_bpf.
 242         (disassemble_init_for_target): Likewise.
 243         (enum epbf_isa_attr): Define.
 244         * disassemble.h: extern print_insn_bpf.
 245         * bpf-asm.c: Generated.
 246         * bpf-opc.h: Likewise.
 247         * bpf-opc.c: Likewise.
 248         * bpf-ibld.c: Likewise.
 249         * bpf-dis.c: Likewise.
 250         * bpf-desc.h: Likewise.
 251         * bpf-desc.c: Likewise.
 252
 253 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 254
 255         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 256         and VMSR with the new operands.
 257
 258 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 259
 260         * arm-dis.c (enum mve_instructions): New enum
 261         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 262         and cneg.
 263         (mve_opcodes): New instructions as above.
 264         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 265         csneg and csel.
 266         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 267
 268 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 269
 270         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 271         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 272         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 273         uqshl, urshrl and urshr.
 274         (is_mve_okay_in_it): Add new instructions to TRUE list.
 275         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 276         (print_insn_mve): Updated to accept new %j,
 277         %<bitfield>m and %<bitfield>n patterns.
 278
 279 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 280
 281         * mips-opc.c (mips_builtin_opcodes): Change source register
 282         constraint for DAUI.
 283
 284 2019-05-20  Nick Clifton  <nickc@redhat.com>
 285
 286         * po/fr.po: Updated French translation.
 287
 288 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 289             Michael Collison <michael.collison@arm.com>
 290
 291         * arm-dis.c (thumb32_opcodes): Add new instructions.
 292         (enum mve_instructions): Likewise.
 293         (enum mve_undefined): Add new reasons.
 294         (is_mve_encoding_conflict): Handle new instructions.
 295         (is_mve_undefined): Likewise.
 296         (is_mve_unpredictable): Likewise.
 297         (print_mve_undefined): Likewise.
 298         (print_mve_size): Likewise.
 299
 300 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 301             Michael Collison <michael.collison@arm.com>
 302
 303         * arm-dis.c (thumb32_opcodes): Add new instructions.
 304         (enum mve_instructions): Likewise.
 305         (is_mve_encoding_conflict): Handle new instructions.
 306         (is_mve_undefined): Likewise.
 307         (is_mve_unpredictable): Likewise.
 308         (print_mve_size): Likewise.
 309
 310 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 311             Michael Collison <michael.collison@arm.com>
 312
 313         * arm-dis.c (thumb32_opcodes): Add new instructions.
 314         (enum mve_instructions): Likewise.
 315         (is_mve_encoding_conflict): Likewise.
 316         (is_mve_unpredictable): Likewise.
 317         (print_mve_size): Likewise.
 318
 319 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 320             Michael Collison <michael.collison@arm.com>
 321
 322         * arm-dis.c (thumb32_opcodes): Add new instructions.
 323         (enum mve_instructions): Likewise.
 324         (is_mve_encoding_conflict): Handle new instructions.
 325         (is_mve_undefined): Likewise.
 326         (is_mve_unpredictable): Likewise.
 327         (print_mve_size): Likewise.
 328
 329 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 330             Michael Collison <michael.collison@arm.com>
 331
 332         * arm-dis.c (thumb32_opcodes): Add new instructions.
 333         (enum mve_instructions): Likewise.
 334         (is_mve_encoding_conflict): Handle new instructions.
 335         (is_mve_undefined): Likewise.
 336         (is_mve_unpredictable): Likewise.
 337         (print_mve_size): Likewise.
 338         (print_insn_mve): Likewise.
 339
 340 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 341             Michael Collison <michael.collison@arm.com>
 342
 343         * arm-dis.c (thumb32_opcodes): Add new instructions.
 344         (print_insn_thumb32): Handle new instructions.
 345
 346 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 347             Michael Collison <michael.collison@arm.com>
 348
 349         * arm-dis.c (enum mve_instructions): Add new instructions.
 350         (enum mve_undefined): Add new reasons.
 351         (is_mve_encoding_conflict): Handle new instructions.
 352         (is_mve_undefined): Likewise.
 353         (is_mve_unpredictable): Likewise.
 354         (print_mve_undefined): Likewise.
 355         (print_mve_size): Likewise.
 356         (print_mve_shift_n): Likewise.
 357         (print_insn_mve): Likewise.
 358
 359 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 360             Michael Collison <michael.collison@arm.com>
 361
 362         * arm-dis.c (enum mve_instructions): Add new instructions.
 363         (is_mve_encoding_conflict): Handle new instructions.
 364         (is_mve_unpredictable): Likewise.
 365         (print_mve_rotate): Likewise.
 366         (print_mve_size): Likewise.
 367         (print_insn_mve): Likewise.
 368
 369 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 370             Michael Collison <michael.collison@arm.com>
 371
 372         * arm-dis.c (enum mve_instructions): Add new instructions.
 373         (is_mve_encoding_conflict): Handle new instructions.
 374         (is_mve_unpredictable): Likewise.
 375         (print_mve_size): Likewise.
 376         (print_insn_mve): Likewise.
 377
 378 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 379             Michael Collison <michael.collison@arm.com>
 380
 381         * arm-dis.c (enum mve_instructions): Add new instructions.
 382         (enum mve_undefined): Add new reasons.
 383         (is_mve_encoding_conflict): Handle new instructions.
 384         (is_mve_undefined): Likewise.
 385         (is_mve_unpredictable): Likewise.
 386         (print_mve_undefined): Likewise.
 387         (print_mve_size): Likewise.
 388         (print_insn_mve): Likewise.
 389
 390 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 391             Michael Collison <michael.collison@arm.com>
 392
 393         * arm-dis.c (enum mve_instructions): Add new instructions.
 394         (is_mve_encoding_conflict): Handle new instructions.
 395         (is_mve_undefined): Likewise.
 396         (is_mve_unpredictable): Likewise.
 397         (print_mve_size): Likewise.
 398         (print_insn_mve): Likewise.
 399
 400 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 401             Michael Collison <michael.collison@arm.com>
 402
 403         * arm-dis.c (enum mve_instructions): Add new instructions.
 404         (enum mve_unpredictable): Add new reasons.
 405         (enum mve_undefined): Likewise.
 406         (is_mve_okay_in_it): Handle new isntructions.
 407         (is_mve_encoding_conflict): Likewise.
 408         (is_mve_undefined): Likewise.
 409         (is_mve_unpredictable): Likewise.
 410         (print_mve_vmov_index): Likewise.
 411         (print_simd_imm8): Likewise.
 412         (print_mve_undefined): Likewise.
 413         (print_mve_unpredictable): Likewise.
 414         (print_mve_size): Likewise.
 415         (print_insn_mve): Likewise.
 416
 417 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 418             Michael Collison <michael.collison@arm.com>
 419
 420         * arm-dis.c (enum mve_instructions): Add new instructions.
 421         (enum mve_unpredictable): Add new reasons.
 422         (enum mve_undefined): Likewise.
 423         (is_mve_encoding_conflict): Handle new instructions.
 424         (is_mve_undefined): Likewise.
 425         (is_mve_unpredictable): Likewise.
 426         (print_mve_undefined): Likewise.
 427         (print_mve_unpredictable): Likewise.
 428         (print_mve_rounding_mode): Likewise.
 429         (print_mve_vcvt_size): Likewise.
 430         (print_mve_size): Likewise.
 431         (print_insn_mve): Likewise.
 432
 433 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 434             Michael Collison <michael.collison@arm.com>
 435
 436         * arm-dis.c (enum mve_instructions): Add new instructions.
 437         (enum mve_unpredictable): Add new reasons.
 438         (enum mve_undefined): Likewise.
 439         (is_mve_undefined): Handle new instructions.
 440         (is_mve_unpredictable): Likewise.
 441         (print_mve_undefined): Likewise.
 442         (print_mve_unpredictable): Likewise.
 443         (print_mve_size): Likewise.
 444         (print_insn_mve): Likewise.
 445
 446 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 447             Michael Collison <michael.collison@arm.com>
 448
 449         * arm-dis.c (enum mve_instructions): Add new instructions.
 450         (enum mve_undefined): Add new reasons.
 451         (insns): Add new instructions.
 452         (is_mve_encoding_conflict):
 453         (print_mve_vld_str_addr): New print function.
 454         (is_mve_undefined): Handle new instructions.
 455         (is_mve_unpredictable): Likewise.
 456         (print_mve_undefined): Likewise.
 457         (print_mve_size): Likewise.
 458         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 459         (print_insn_mve):  Handle new operands.
 460
 461 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 462             Michael Collison <michael.collison@arm.com>
 463
 464         * arm-dis.c (enum mve_instructions): Add new instructions.
 465         (enum mve_unpredictable): Add new reasons.
 466         (is_mve_encoding_conflict): Handle new instructions.
 467         (is_mve_unpredictable): Likewise.
 468         (mve_opcodes): Add new instructions.
 469         (print_mve_unpredictable): Handle new reasons.
 470         (print_mve_register_blocks): New print function.
 471         (print_mve_size): Handle new instructions.
 472         (print_insn_mve): Likewise.
 473
 474 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 475             Michael Collison <michael.collison@arm.com>
 476
 477         * arm-dis.c (enum mve_instructions): Add new instructions.
 478         (enum mve_unpredictable): Add new reasons.
 479         (enum mve_undefined): Likewise.
 480         (is_mve_encoding_conflict): Handle new instructions.
 481         (is_mve_undefined): Likewise.
 482         (is_mve_unpredictable): Likewise.
 483         (coprocessor_opcodes): Move NEON VDUP from here...
 484         (neon_opcodes): ... to here.
 485         (mve_opcodes): Add new instructions.
 486         (print_mve_undefined):  Handle new reasons.
 487         (print_mve_unpredictable): Likewise.
 488         (print_mve_size): Handle new instructions.
 489         (print_insn_neon): Handle vdup.
 490         (print_insn_mve): Handle new operands.
 491
 492 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 493             Michael Collison <michael.collison@arm.com>
 494
 495         * arm-dis.c (enum mve_instructions): Add new instructions.
 496         (enum mve_unpredictable): Add new values.
 497         (mve_opcodes): Add new instructions.
 498         (vec_condnames): New array with vector conditions.
 499         (mve_predicatenames): New array with predicate suffixes.
 500         (mve_vec_sizename): New array with vector sizes.
 501         (enum vpt_pred_state): New enum with vector predication states.
 502         (struct vpt_block): New struct type for vpt blocks.
 503         (vpt_block_state): Global struct to keep track of state.
 504         (mve_extract_pred_mask): New helper function.
 505         (num_instructions_vpt_block): Likewise.
 506         (mark_outside_vpt_block): Likewise.
 507         (mark_inside_vpt_block): Likewise.
 508         (invert_next_predicate_state): Likewise.
 509         (update_next_predicate_state): Likewise.
 510         (update_vpt_block_state): Likewise.
 511         (is_vpt_instruction): Likewise.
 512         (is_mve_encoding_conflict): Add entries for new instructions.
 513         (is_mve_unpredictable): Likewise.
 514         (print_mve_unpredictable): Handle new cases.
 515         (print_instruction_predicate): Likewise.
 516         (print_mve_size): New function.
 517         (print_vec_condition): New function.
 518         (print_insn_mve): Handle vpt blocks and new print operands.
 519
 520 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 521
 522         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 523         8, 14 and 15 for Armv8.1-M Mainline.
 524
 525 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 526             Michael Collison <michael.collison@arm.com>
 527
 528         * arm-dis.c (enum mve_instructions): New enum.
 529         (enum mve_unpredictable): Likewise.
 530         (enum mve_undefined): Likewise.
 531         (struct mopcode32): New struct.
 532         (is_mve_okay_in_it): New function.
 533         (is_mve_architecture): Likewise.
 534         (arm_decode_field): Likewise.
 535         (arm_decode_field_multiple): Likewise.
 536         (is_mve_encoding_conflict): Likewise.
 537         (is_mve_undefined): Likewise.
 538         (is_mve_unpredictable): Likewise.
 539         (print_mve_undefined): Likewise.
 540         (print_mve_unpredictable): Likewise.
 541         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 542         (print_insn_mve): New function.
 543         (print_insn_thumb32): Handle MVE architecture.
 544         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 545
 546 2019-05-10  Nick Clifton  <nickc@redhat.com>
 547
 548         PR 24538
 549         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 550         end of the table prematurely.
 551
 552 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 553
 554         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 555         macros for R6.
 556
 557 2019-05-11  Alan Modra  <amodra@gmail.com>
 558
 559         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 560         when -Mraw is in effect.
 561
 562 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 563
 564         * aarch64-dis-2.c: Regenerate.
 565         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 566         (OP_SVE_BBB): New variant set.
 567         (OP_SVE_DDDD): New variant set.
 568         (OP_SVE_HHH): New variant set.
 569         (OP_SVE_HHHU): New variant set.
 570         (OP_SVE_SSS): New variant set.
 571         (OP_SVE_SSSU): New variant set.
 572         (OP_SVE_SHH): New variant set.
 573         (OP_SVE_SBBU): New variant set.
 574         (OP_SVE_DSS): New variant set.
 575         (OP_SVE_DHHU): New variant set.
 576         (OP_SVE_VMV_HSD_BHS): New variant set.
 577         (OP_SVE_VVU_HSD_BHS): New variant set.
 578         (OP_SVE_VVVU_SD_BH): New variant set.
 579         (OP_SVE_VVVU_BHSD): New variant set.
 580         (OP_SVE_VVV_QHD_DBS): New variant set.
 581         (OP_SVE_VVV_HSD_BHS): New variant set.
 582         (OP_SVE_VVV_HSD_BHS2): New variant set.
 583         (OP_SVE_VVV_BHS_HSD): New variant set.
 584         (OP_SVE_VV_BHS_HSD): New variant set.
 585         (OP_SVE_VVV_SD): New variant set.
 586         (OP_SVE_VVU_BHS_HSD): New variant set.
 587         (OP_SVE_VZVV_SD): New variant set.
 588         (OP_SVE_VZVV_BH): New variant set.
 589         (OP_SVE_VZV_SD): New variant set.
 590         (aarch64_opcode_table): Add sve2 instructions.
 591
 592 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 593
 594         * aarch64-asm-2.c: Regenerated.
 595         * aarch64-dis-2.c: Regenerated.
 596         * aarch64-opc-2.c: Regenerated.
 597         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 598         for SVE_SHLIMM_UNPRED_22.
 599         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 600         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 601         operand.
 602
 603 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 604
 605         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 606         sve_size_tsz_bhs iclass encode.
 607         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 608         sve_size_tsz_bhs iclass decode.
 609
 610 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 611
 612         * aarch64-asm-2.c: Regenerated.
 613         * aarch64-dis-2.c: Regenerated.
 614         * aarch64-opc-2.c: Regenerated.
 615         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 616         for SVE_Zm4_11_INDEX.
 617         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 618         (fields): Handle SVE_i2h field.
 619         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 620         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 621
 622 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 623
 624         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 625         sve_shift_tsz_bhsd iclass encode.
 626         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 627         sve_shift_tsz_bhsd iclass decode.
 628
 629 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 630
 631         * aarch64-asm-2.c: Regenerated.
 632         * aarch64-dis-2.c: Regenerated.
 633         * aarch64-opc-2.c: Regenerated.
 634         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 635         (aarch64_encode_variant_using_iclass): Handle
 636         sve_shift_tsz_hsd iclass encode.
 637         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 638         sve_shift_tsz_hsd iclass decode.
 639         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 640         for SVE_SHRIMM_UNPRED_22.
 641         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 642         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 643         operand.
 644
 645 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 646
 647         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 648         sve_size_013 iclass encode.
 649         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 650         sve_size_013 iclass decode.
 651
 652 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 653
 654         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 655         sve_size_bh iclass encode.
 656         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 657         sve_size_bh iclass decode.
 658
 659 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 660
 661         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 662         sve_size_sd2 iclass encode.
 663         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 664         sve_size_sd2 iclass decode.
 665         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 666         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 667
 668 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 669
 670         * aarch64-asm-2.c: Regenerated.
 671         * aarch64-dis-2.c: Regenerated.
 672         * aarch64-opc-2.c: Regenerated.
 673         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 674         for SVE_ADDR_ZX.
 675         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 676         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 677
 678 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 679
 680         * aarch64-asm-2.c: Regenerated.
 681         * aarch64-dis-2.c: Regenerated.
 682         * aarch64-opc-2.c: Regenerated.
 683         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 684         for SVE_Zm3_11_INDEX.
 685         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 686         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 687         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 688         fields.
 689         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 690
 691 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 692
 693         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 694         sve_size_hsd2 iclass encode.
 695         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 696         sve_size_hsd2 iclass decode.
 697         * aarch64-opc.c (fields): Handle SVE_size field.
 698         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 699
 700 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 701
 702         * aarch64-asm-2.c: Regenerated.
 703         * aarch64-dis-2.c: Regenerated.
 704         * aarch64-opc-2.c: Regenerated.
 705         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 706         for SVE_IMM_ROT3.
 707         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 708         (fields): Handle SVE_rot3 field.
 709         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 710         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 711
 712 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 713
 714         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 715         instructions.
 716
 717 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 718
 719         * aarch64-tbl.h
 720         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 721         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 722         aarch64_feature_sve2bitperm): New feature sets.
 723         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 724         for feature set addresses.
 725         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 726         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 727
 728 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 729             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 730
 731         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 732         argument and set ASE_EVA_R6 appropriately.
 733         (set_default_mips_dis_options): Pass ISA to above.
 734         (parse_mips_dis_option): Likewise.
 735         * mips-opc.c (EVAR6): New macro.
 736         (mips_builtin_opcodes): Add llwpe, scwpe.
 737
 738 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 739
 740         * aarch64-asm-2.c: Regenerated.
 741         * aarch64-dis-2.c: Regenerated.
 742         * aarch64-opc-2.c: Regenerated.
 743         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 744         AARCH64_OPND_TME_UIMM16.
 745         (aarch64_print_operand): Likewise.
 746         * aarch64-tbl.h (QL_IMM_NIL): New.
 747         (TME): New.
 748         (_TME_INSN): New.
 749         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 750
 751 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 752
 753         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 754
 755 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 756             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 757
 758         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 759
 760 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 761
 762         * s12z-opc.h: Add extern "C" bracketing to help
 763         users who wish to use this interface in c++ code.
 764
 765 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 766
 767         * s12z-opc.c (bm_decode): Handle bit map operations with the
 768         "reserved0" mode.
 769
 770 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 771
 772         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 773         specifier.  Add entries for VLDR and VSTR of system registers.
 774         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 775         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 776         of %J and %K format specifier.
 777
 778 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 779
 780         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 781         Add new entries for VSCCLRM instruction.
 782         (print_insn_coprocessor): Handle new %C format control code.
 783
 784 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 785
 786         * arm-dis.c (enum isa): New enum.
 787         (struct sopcode32): New structure.
 788         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 789         set isa field of all current entries to ANY.
 790         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 791         Only match an entry if its isa field allows the current mode.
 792
 793 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 794
 795         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 796         CLRM.
 797         (print_insn_thumb32): Add logic to print %n CLRM register list.
 798
 799 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 800
 801         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 802         and %Q patterns.
 803
 804 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 805
 806         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 807         (print_insn_thumb32): Edit the switch case for %Z.
 808
 809 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 810
 811         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 812
 813 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 814
 815         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 816
 817 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 818
 819         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 820
 821 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 822
 823         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 824         Arm register with r13 and r15 unpredictable.
 825         (thumb32_opcodes): New instructions for bfx and bflx.
 826
 827 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 828
 829         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 830
 831 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 832
 833         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 834
 835 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 836
 837         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 838
 839 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 840
 841         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 842
 843 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 844
 845         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 846         "optr". ("operator" is a reserved word in c++).
 847
 848 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 849
 850         * aarch64-opc.c (aarch64_print_operand): Add case for
 851         AARCH64_OPND_Rt_SP.
 852         (verify_constraints): Likewise.
 853         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 854         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 855         to accept Rt|SP as first operand.
 856         (AARCH64_OPERANDS): Add new Rt_SP.
 857         * aarch64-asm-2.c: Regenerated.
 858         * aarch64-dis-2.c: Regenerated.
 859         * aarch64-opc-2.c: Regenerated.
 860
 861 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 862
 863         * aarch64-asm-2.c: Regenerated.
 864         * aarch64-dis-2.c: Likewise.
 865         * aarch64-opc-2.c: Likewise.
 866         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 867
 868 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 869
 870         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 871
 872 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 873
 874         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 875         * i386-init.h: Regenerated.
 876
 877 2019-04-07  Alan Modra  <amodra@gmail.com>
 878
 879         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 880         op_separator to control printing of spaces, comma and parens
 881         rather than need_comma, need_paren and spaces vars.
 882
 883 2019-04-07  Alan Modra  <amodra@gmail.com>
 884
 885         PR 24421
 886         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 887         (print_insn_neon, print_insn_arm): Likewise.
 888
 889 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 890
 891         * i386-dis-evex.h (evex_table): Updated to support BF16
 892         instructions.
 893         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 894         and EVEX_W_0F3872_P_3.
 895         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 896         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 897         * i386-opc.h (enum): Add CpuAVX512_BF16.
 898         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 899         * i386-opc.tbl: Add AVX512 BF16 instructions.
 900         * i386-init.h: Regenerated.
 901         * i386-tbl.h: Likewise.
 902
 903 2019-04-05  Alan Modra  <amodra@gmail.com>
 904
 905         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 906         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 907         to favour printing of "-" branch hint when using the "y" bit.
 908         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 909
 910 2019-04-05  Alan Modra  <amodra@gmail.com>
 911
 912         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 913         opcode until first operand is output.
 914
 915 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 916
 917         PR gas/24349
 918         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 919         (valid_bo_post_v2): Add support for 'at' branch hints.
 920         (insert_bo): Only error on branch on ctr.
 921         (get_bo_hint_mask): New function.
 922         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 923         for inserting 'at' branch hints.
 924         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 925         for extracting 'at' branch hints.
 926         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 927         (BOE): Delete operand.
 928         (BOM, BOP): New operands.
 929         (RM): Update value.
 930         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 931         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 932         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 933         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 934         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 935         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 936         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 937         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 938         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 939         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 940         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 941         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 942         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 943         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 944         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 945         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 946         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 947         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 948         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 949         bttarl+>: New extended mnemonics.
 950
 951 2019-03-28  Alan Modra  <amodra@gmail.com>
 952
 953         PR 24390
 954         * ppc-opc.c (BTF): Define.
 955         (powerpc_opcodes): Use for mtfsb*.
 956         * ppc-dis.c (print_insn_powerpc): Print fields with both
 957         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 958
 959 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 960
 961         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 962         (mapping_symbol_for_insn): Implement new algorithm.
 963         (print_insn): Remove duplicate code.
 964
 965 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 966
 967         * aarch64-dis.c (print_insn_aarch64):
 968         Implement override.
 969
 970 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 971
 972         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 973         order.
 974
 975 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 976
 977         * aarch64-dis.c (last_stop_offset): New.
 978         (print_insn_aarch64): Use stop_offset.
 979
 980 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 981
 982         PR gas/24359
 983         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 984         CPU_ANY_AVX2_FLAGS.
 985         * i386-init.h: Regenerated.
 986
 987 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 988
 989         PR gas/24348
 990         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 991         vmovdqu16, vmovdqu32 and vmovdqu64.
 992         * i386-tbl.h: Regenerated.
 993
 994 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 995
 996         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 997         from vstrszb, vstrszh, and vstrszf.
 998
 999 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1000
1001         * s390-opc.txt: Add instruction descriptions.
1002
1003 2019-02-08  Jim Wilson  <jimw@sifive.com>
1004
1005         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1006         <bne>: Likewise.
1007
1008 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1009
1010         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1011
1012 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1013
1014         PR binutils/23212
1015         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1016         * aarch64-opc.c (verify_elem_sd): New.
1017         (fields): Add FLD_sz entr.
1018         * aarch64-tbl.h (_SIMD_INSN): New.
1019         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1020         fmulx scalar and vector by element isns.
1021
1022 2019-02-07  Nick Clifton  <nickc@redhat.com>
1023
1024         * po/sv.po: Updated Swedish translation.
1025
1026 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1027
1028         * s390-mkopc.c (main): Accept arch13 as cpu string.
1029         * s390-opc.c: Add new instruction formats and instruction opcode
1030         masks.
1031         * s390-opc.txt: Add new arch13 instructions.
1032
1033 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1034
1035         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1036         (aarch64_opcode): Change encoding for stg, stzg
1037         st2g and st2zg.
1038         * aarch64-asm-2.c: Regenerated.
1039         * aarch64-dis-2.c: Regenerated.
1040         * aarch64-opc-2.c: Regenerated.
1041
1042 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1043
1044         * aarch64-asm-2.c: Regenerated.
1045         * aarch64-dis-2.c: Likewise.
1046         * aarch64-opc-2.c: Likewise.
1047         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1048
1049 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1050             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1051
1052         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1053         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1054         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1055         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1056         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1057         case for ldstgv_indexed.
1058         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1059         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1060         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1061         * aarch64-asm-2.c: Regenerated.
1062         * aarch64-dis-2.c: Regenerated.
1063         * aarch64-opc-2.c: Regenerated.
1064
1065 2019-01-23  Nick Clifton  <nickc@redhat.com>
1066
1067         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1068
1069 2019-01-21  Nick Clifton  <nickc@redhat.com>
1070
1071         * po/de.po: Updated German translation.
1072         * po/uk.po: Updated Ukranian translation.
1073
1074 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1075         * mips-dis.c (mips_arch_choices): Fix typo in
1076         gs464, gs464e and gs264e descriptors.
1077
1078 2019-01-19  Nick Clifton  <nickc@redhat.com>
1079
1080         * configure: Regenerate.
1081         * po/opcodes.pot: Regenerate.
1082
1083 2018-06-24  Nick Clifton  <nickc@redhat.com>
1084
1085         2.32 branch created.
1086
1087 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1088
1089         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1090         if it is null.
1091         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1092         zero.
1093
1094 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1095
1096         * configure: Regenerate.
1097
1098 2019-01-07  Alan Modra  <amodra@gmail.com>
1099
1100         * configure: Regenerate.
1101         * po/POTFILES.in: Regenerate.
1102
1103 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1104
1105         * s12z-opc.c: New file.
1106         * s12z-opc.h: New file.
1107         * s12z-dis.c: Removed all code not directly related to display
1108         of instructions.  Used the interface provided by the new files
1109         instead.
1110         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1111         * Makefile.in: Regenerate.
1112         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1113         * configure: Regenerate.
1114
1115 2019-01-01  Alan Modra  <amodra@gmail.com>
1116
1117         Update year range in copyright notice of all files.
1118
1119 For older changes see ChangeLog-2018
1120 \f
1121 Copyright (C) 2019 Free Software Foundation, Inc.
1122
1123 Copying and distribution of this file, with or without modification,
1124 are permitted in any medium without royalty provided the copyright
1125 notice and this notice are preserved.
1126
1127 Local Variables:
1128 mode: change-log
1129 left-margin: 8
1130 fill-column: 74
1131 version-control: never
1132 End: